1/* 2 * Kernel execution entry point code. 3 * 4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> 5 * Initial PowerPC version. 6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> 7 * Rewritten for PReP 8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> 9 * Low-level exception handers, MMU support, and rewrite. 10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> 11 * PowerPC 8xx modifications. 12 * Copyright (c) 1998-1999 TiVo, Inc. 13 * PowerPC 403GCX modifications. 14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> 15 * PowerPC 403GCX/405GP modifications. 16 * Copyright 2000 MontaVista Software Inc. 17 * PPC405 modifications 18 * PowerPC 403GCX/405GP modifications. 19 * Author: MontaVista Software, Inc. 20 * frank_rowand@mvista.com or source@mvista.com 21 * debbie_chu@mvista.com 22 * Copyright 2002-2004 MontaVista Software, Inc. 23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> 24 * Copyright 2004 Freescale Semiconductor, Inc 25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> 26 * 27 * This program is free software; you can redistribute it and/or modify it 28 * under the terms of the GNU General Public License as published by the 29 * Free Software Foundation; either version 2 of the License, or (at your 30 * option) any later version. 31 */ 32 33#include <linux/init.h> 34#include <linux/threads.h> 35#include <asm/processor.h> 36#include <asm/page.h> 37#include <asm/mmu.h> 38#include <asm/pgtable.h> 39#include <asm/cputable.h> 40#include <asm/thread_info.h> 41#include <asm/ppc_asm.h> 42#include <asm/asm-offsets.h> 43#include <asm/cache.h> 44#include <asm/ptrace.h> 45#include "head_booke.h" 46 47/* As with the other PowerPC ports, it is expected that when code 48 * execution begins here, the following registers contain valid, yet 49 * optional, information: 50 * 51 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) 52 * r4 - Starting address of the init RAM disk 53 * r5 - Ending address of the init RAM disk 54 * r6 - Start of kernel command line string (e.g. "mem=128") 55 * r7 - End of kernel command line string 56 * 57 */ 58 __HEAD 59_ENTRY(_stext); 60_ENTRY(_start); 61 /* 62 * Reserve a word at a fixed location to store the address 63 * of abatron_pteptrs 64 */ 65 nop 66 67 /* Translate device tree address to physical, save in r30/r31 */ 68 bl get_phys_addr 69 mr r30,r3 70 mr r31,r4 71 72 li r25,0 /* phys kernel start (low) */ 73 li r24,0 /* CPU number */ 74 li r23,0 /* phys kernel start (high) */ 75 76#ifdef CONFIG_RELOCATABLE 77 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ 78 79 /* Translate _stext address to physical, save in r23/r25 */ 80 bl get_phys_addr 81 mr r23,r3 82 mr r25,r4 83 84 bl 0f 850: mflr r8 86 addis r3,r8,(is_second_reloc - 0b)@ha 87 lwz r19,(is_second_reloc - 0b)@l(r3) 88 89 /* Check if this is the second relocation. */ 90 cmpwi r19,1 91 bne 1f 92 93 /* 94 * For the second relocation, we already get the real memstart_addr 95 * from device tree. So we will map PAGE_OFFSET to memstart_addr, 96 * then the virtual address of start kernel should be: 97 * PAGE_OFFSET + (kernstart_addr - memstart_addr) 98 * Since the offset between kernstart_addr and memstart_addr should 99 * never be beyond 1G, so we can just use the lower 32bit of them 100 * for the calculation. 101 */ 102 lis r3,PAGE_OFFSET@h 103 104 addis r4,r8,(kernstart_addr - 0b)@ha 105 addi r4,r4,(kernstart_addr - 0b)@l 106 lwz r5,4(r4) 107 108 addis r6,r8,(memstart_addr - 0b)@ha 109 addi r6,r6,(memstart_addr - 0b)@l 110 lwz r7,4(r6) 111 112 subf r5,r7,r5 113 add r3,r3,r5 114 b 2f 115 1161: 117 /* 118 * We have the runtime (virutal) address of our base. 119 * We calculate our shift of offset from a 64M page. 120 * We could map the 64M page we belong to at PAGE_OFFSET and 121 * get going from there. 122 */ 123 lis r4,KERNELBASE@h 124 ori r4,r4,KERNELBASE@l 125 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ 126 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ 127 subf r3,r5,r6 /* r3 = r6 - r5 */ 128 add r3,r4,r3 /* Required Virtual Address */ 129 1302: bl relocate 131 132 /* 133 * For the second relocation, we already set the right tlb entries 134 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S 135 */ 136 cmpwi r19,1 137 beq set_ivor 138#endif 139 140/* We try to not make any assumptions about how the boot loader 141 * setup or used the TLBs. We invalidate all mappings from the 142 * boot loader and load a single entry in TLB1[0] to map the 143 * first 64M of kernel memory. Any boot info passed from the 144 * bootloader needs to live in this first 64M. 145 * 146 * Requirement on bootloader: 147 * - The page we're executing in needs to reside in TLB1 and 148 * have IPROT=1. If not an invalidate broadcast could 149 * evict the entry we're currently executing in. 150 * 151 * r3 = Index of TLB1 were executing in 152 * r4 = Current MSR[IS] 153 * r5 = Index of TLB1 temp mapping 154 * 155 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] 156 * if needed 157 */ 158 159_ENTRY(__early_start) 160 161#define ENTRY_MAPPING_BOOT_SETUP 162#include "fsl_booke_entry_mapping.S" 163#undef ENTRY_MAPPING_BOOT_SETUP 164 165set_ivor: 166 /* Establish the interrupt vector offsets */ 167 SET_IVOR(0, CriticalInput); 168 SET_IVOR(1, MachineCheck); 169 SET_IVOR(2, DataStorage); 170 SET_IVOR(3, InstructionStorage); 171 SET_IVOR(4, ExternalInput); 172 SET_IVOR(5, Alignment); 173 SET_IVOR(6, Program); 174 SET_IVOR(7, FloatingPointUnavailable); 175 SET_IVOR(8, SystemCall); 176 SET_IVOR(9, AuxillaryProcessorUnavailable); 177 SET_IVOR(10, Decrementer); 178 SET_IVOR(11, FixedIntervalTimer); 179 SET_IVOR(12, WatchdogTimer); 180 SET_IVOR(13, DataTLBError); 181 SET_IVOR(14, InstructionTLBError); 182 SET_IVOR(15, DebugCrit); 183 184 /* Establish the interrupt vector base */ 185 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 186 mtspr SPRN_IVPR,r4 187 188 /* Setup the defaults for TLB entries */ 189 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 190#ifdef CONFIG_E200 191 oris r2,r2,MAS4_TLBSELD(1)@h 192#endif 193 mtspr SPRN_MAS4, r2 194 195#if 0 196 /* Enable DOZE */ 197 mfspr r2,SPRN_HID0 198 oris r2,r2,HID0_DOZE@h 199 mtspr SPRN_HID0, r2 200#endif 201 202#if !defined(CONFIG_BDI_SWITCH) 203 /* 204 * The Abatron BDI JTAG debugger does not tolerate others 205 * mucking with the debug registers. 206 */ 207 lis r2,DBCR0_IDM@h 208 mtspr SPRN_DBCR0,r2 209 isync 210 /* clear any residual debug events */ 211 li r2,-1 212 mtspr SPRN_DBSR,r2 213#endif 214 215#ifdef CONFIG_SMP 216 /* Check to see if we're the second processor, and jump 217 * to the secondary_start code if so 218 */ 219 LOAD_REG_ADDR_PIC(r24, boot_cpuid) 220 lwz r24, 0(r24) 221 cmpwi r24, -1 222 mfspr r24,SPRN_PIR 223 bne __secondary_start 224#endif 225 226 /* 227 * This is where the main kernel code starts. 228 */ 229 230 /* ptr to current */ 231 lis r2,init_task@h 232 ori r2,r2,init_task@l 233 234 /* ptr to current thread */ 235 addi r4,r2,THREAD /* init task's THREAD */ 236 mtspr SPRN_SPRG_THREAD,r4 237 238 /* stack */ 239 lis r1,init_thread_union@h 240 ori r1,r1,init_thread_union@l 241 li r0,0 242 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) 243 244 CURRENT_THREAD_INFO(r22, r1) 245 stw r24, TI_CPU(r22) 246 247 bl early_init 248 249#ifdef CONFIG_RELOCATABLE 250 mr r3,r30 251 mr r4,r31 252#ifdef CONFIG_PHYS_64BIT 253 mr r5,r23 254 mr r6,r25 255#else 256 mr r5,r25 257#endif 258 bl relocate_init 259#endif 260 261#ifdef CONFIG_DYNAMIC_MEMSTART 262 lis r3,kernstart_addr@ha 263 la r3,kernstart_addr@l(r3) 264#ifdef CONFIG_PHYS_64BIT 265 stw r23,0(r3) 266 stw r25,4(r3) 267#else 268 stw r25,0(r3) 269#endif 270#endif 271 272/* 273 * Decide what sort of machine this is and initialize the MMU. 274 */ 275 mr r3,r30 276 mr r4,r31 277 bl machine_init 278 bl MMU_init 279 280 /* Setup PTE pointers for the Abatron bdiGDB */ 281 lis r6, swapper_pg_dir@h 282 ori r6, r6, swapper_pg_dir@l 283 lis r5, abatron_pteptrs@h 284 ori r5, r5, abatron_pteptrs@l 285 lis r4, KERNELBASE@h 286 ori r4, r4, KERNELBASE@l 287 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ 288 stw r6, 0(r5) 289 290 /* Let's move on */ 291 lis r4,start_kernel@h 292 ori r4,r4,start_kernel@l 293 lis r3,MSR_KERNEL@h 294 ori r3,r3,MSR_KERNEL@l 295 mtspr SPRN_SRR0,r4 296 mtspr SPRN_SRR1,r3 297 rfi /* change context and jump to start_kernel */ 298 299/* Macros to hide the PTE size differences 300 * 301 * FIND_PTE -- walks the page tables given EA & pgdir pointer 302 * r10 -- EA of fault 303 * r11 -- PGDIR pointer 304 * r12 -- free 305 * label 2: is the bailout case 306 * 307 * if we find the pte (fall through): 308 * r11 is low pte word 309 * r12 is pointer to the pte 310 * r10 is the pshift from the PGD, if we're a hugepage 311 */ 312#ifdef CONFIG_PTE_64BIT 313#ifdef CONFIG_HUGETLB_PAGE 314#define FIND_PTE \ 315 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 316 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 317 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 318 blt 1000f; /* Normal non-huge page */ \ 319 beq 2f; /* Bail if no table */ \ 320 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ 321 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ 322 xor r12, r10, r11; /* drop size bits from pointer */ \ 323 b 1001f; \ 3241000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 325 li r10, 0; /* clear r10 */ \ 3261001: lwz r11, 4(r12); /* Get pte entry */ 327#else 328#define FIND_PTE \ 329 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ 330 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ 331 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ 332 beq 2f; /* Bail if no table */ \ 333 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ 334 lwz r11, 4(r12); /* Get pte entry */ 335#endif /* HUGEPAGE */ 336#else /* !PTE_64BIT */ 337#define FIND_PTE \ 338 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ 339 lwz r11, 0(r11); /* Get L1 entry */ \ 340 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ 341 beq 2f; /* Bail if no table */ \ 342 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ 343 lwz r11, 0(r12); /* Get Linux PTE */ 344#endif 345 346/* 347 * Interrupt vector entry code 348 * 349 * The Book E MMUs are always on so we don't need to handle 350 * interrupts in real mode as with previous PPC processors. In 351 * this case we handle interrupts in the kernel virtual address 352 * space. 353 * 354 * Interrupt vectors are dynamically placed relative to the 355 * interrupt prefix as determined by the address of interrupt_base. 356 * The interrupt vectors offsets are programmed using the labels 357 * for each interrupt vector entry. 358 * 359 * Interrupt vectors must be aligned on a 16 byte boundary. 360 * We align on a 32 byte cache line boundary for good measure. 361 */ 362 363interrupt_base: 364 /* Critical Input Interrupt */ 365 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) 366 367 /* Machine Check Interrupt */ 368#ifdef CONFIG_E200 369 /* no RFMCI, MCSRRs on E200 */ 370 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \ 371 machine_check_exception) 372#else 373 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) 374#endif 375 376 /* Data Storage Interrupt */ 377 START_EXCEPTION(DataStorage) 378 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE) 379 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ 380 stw r5,_ESR(r11) 381 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ 382 andis. r10,r5,(ESR_ILK|ESR_DLK)@h 383 bne 1f 384 EXC_XFER_LITE(0x0300, handle_page_fault) 3851: 386 addi r3,r1,STACK_FRAME_OVERHEAD 387 EXC_XFER_EE_LITE(0x0300, CacheLockingException) 388 389 /* Instruction Storage Interrupt */ 390 INSTRUCTION_STORAGE_EXCEPTION 391 392 /* External Input Interrupt */ 393 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE) 394 395 /* Alignment Interrupt */ 396 ALIGNMENT_EXCEPTION 397 398 /* Program Interrupt */ 399 PROGRAM_EXCEPTION 400 401 /* Floating Point Unavailable Interrupt */ 402#ifdef CONFIG_PPC_FPU 403 FP_UNAVAILABLE_EXCEPTION 404#else 405#ifdef CONFIG_E200 406 /* E200 treats 'normal' floating point instructions as FP Unavail exception */ 407 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ 408 program_check_exception, EXC_XFER_EE) 409#else 410 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ 411 unknown_exception, EXC_XFER_EE) 412#endif 413#endif 414 415 /* System Call Interrupt */ 416 START_EXCEPTION(SystemCall) 417 NORMAL_EXCEPTION_PROLOG(SYSCALL) 418 EXC_XFER_EE_LITE(0x0c00, DoSyscall) 419 420 /* Auxiliary Processor Unavailable Interrupt */ 421 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \ 422 unknown_exception, EXC_XFER_EE) 423 424 /* Decrementer Interrupt */ 425 DECREMENTER_EXCEPTION 426 427 /* Fixed Internal Timer Interrupt */ 428 /* TODO: Add FIT support */ 429 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \ 430 unknown_exception, EXC_XFER_EE) 431 432 /* Watchdog Timer Interrupt */ 433#ifdef CONFIG_BOOKE_WDT 434 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) 435#else 436 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) 437#endif 438 439 /* Data TLB Error Interrupt */ 440 START_EXCEPTION(DataTLBError) 441 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 442 mfspr r10, SPRN_SPRG_THREAD 443 stw r11, THREAD_NORMSAVE(0)(r10) 444#ifdef CONFIG_KVM_BOOKE_HV 445BEGIN_FTR_SECTION 446 mfspr r11, SPRN_SRR1 447END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 448#endif 449 stw r12, THREAD_NORMSAVE(1)(r10) 450 stw r13, THREAD_NORMSAVE(2)(r10) 451 mfcr r13 452 stw r13, THREAD_NORMSAVE(3)(r10) 453 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 454 mfspr r10, SPRN_DEAR /* Get faulting address */ 455 456 /* If we are faulting a kernel address, we have to use the 457 * kernel page tables. 458 */ 459 lis r11, PAGE_OFFSET@h 460 cmplw 5, r10, r11 461 blt 5, 3f 462 lis r11, swapper_pg_dir@h 463 ori r11, r11, swapper_pg_dir@l 464 465 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 466 rlwinm r12,r12,0,16,1 467 mtspr SPRN_MAS1,r12 468 469 b 4f 470 471 /* Get the PGD for the current thread */ 4723: 473 mfspr r11,SPRN_SPRG_THREAD 474 lwz r11,PGDIR(r11) 475 4764: 477 /* Mask of required permission bits. Note that while we 478 * do copy ESR:ST to _PAGE_RW position as trying to write 479 * to an RO page is pretty common, we don't do it with 480 * _PAGE_DIRTY. We could do it, but it's a fairly rare 481 * event so I'd rather take the overhead when it happens 482 * rather than adding an instruction here. We should measure 483 * whether the whole thing is worth it in the first place 484 * as we could avoid loading SPRN_ESR completely in the first 485 * place... 486 * 487 * TODO: Is it worth doing that mfspr & rlwimi in the first 488 * place or can we save a couple of instructions here ? 489 */ 490 mfspr r12,SPRN_ESR 491#ifdef CONFIG_PTE_64BIT 492 li r13,_PAGE_PRESENT 493 oris r13,r13,_PAGE_ACCESSED@h 494#else 495 li r13,_PAGE_PRESENT|_PAGE_ACCESSED 496#endif 497 rlwimi r13,r12,11,29,29 498 499 FIND_PTE 500 andc. r13,r13,r11 /* Check permission */ 501 502#ifdef CONFIG_PTE_64BIT 503#ifdef CONFIG_SMP 504 subf r13,r11,r12 /* create false data dep */ 505 lwzx r13,r11,r13 /* Get upper pte bits */ 506#else 507 lwz r13,0(r12) /* Get upper pte bits */ 508#endif 509#endif 510 511 bne 2f /* Bail if permission/valid mismach */ 512 513 /* Jump to common tlb load */ 514 b finish_tlb_load 5152: 516 /* The bailout. Restore registers to pre-exception conditions 517 * and call the heavyweights to help us out. 518 */ 519 mfspr r10, SPRN_SPRG_THREAD 520 lwz r11, THREAD_NORMSAVE(3)(r10) 521 mtcr r11 522 lwz r13, THREAD_NORMSAVE(2)(r10) 523 lwz r12, THREAD_NORMSAVE(1)(r10) 524 lwz r11, THREAD_NORMSAVE(0)(r10) 525 mfspr r10, SPRN_SPRG_RSCRATCH0 526 b DataStorage 527 528 /* Instruction TLB Error Interrupt */ 529 /* 530 * Nearly the same as above, except we get our 531 * information from different registers and bailout 532 * to a different point. 533 */ 534 START_EXCEPTION(InstructionTLBError) 535 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ 536 mfspr r10, SPRN_SPRG_THREAD 537 stw r11, THREAD_NORMSAVE(0)(r10) 538#ifdef CONFIG_KVM_BOOKE_HV 539BEGIN_FTR_SECTION 540 mfspr r11, SPRN_SRR1 541END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) 542#endif 543 stw r12, THREAD_NORMSAVE(1)(r10) 544 stw r13, THREAD_NORMSAVE(2)(r10) 545 mfcr r13 546 stw r13, THREAD_NORMSAVE(3)(r10) 547 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 548 mfspr r10, SPRN_SRR0 /* Get faulting address */ 549 550 /* If we are faulting a kernel address, we have to use the 551 * kernel page tables. 552 */ 553 lis r11, PAGE_OFFSET@h 554 cmplw 5, r10, r11 555 blt 5, 3f 556 lis r11, swapper_pg_dir@h 557 ori r11, r11, swapper_pg_dir@l 558 559 mfspr r12,SPRN_MAS1 /* Set TID to 0 */ 560 rlwinm r12,r12,0,16,1 561 mtspr SPRN_MAS1,r12 562 563 /* Make up the required permissions for kernel code */ 564#ifdef CONFIG_PTE_64BIT 565 li r13,_PAGE_PRESENT | _PAGE_BAP_SX 566 oris r13,r13,_PAGE_ACCESSED@h 567#else 568 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 569#endif 570 b 4f 571 572 /* Get the PGD for the current thread */ 5733: 574 mfspr r11,SPRN_SPRG_THREAD 575 lwz r11,PGDIR(r11) 576 577 /* Make up the required permissions for user code */ 578#ifdef CONFIG_PTE_64BIT 579 li r13,_PAGE_PRESENT | _PAGE_BAP_UX 580 oris r13,r13,_PAGE_ACCESSED@h 581#else 582 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC 583#endif 584 5854: 586 FIND_PTE 587 andc. r13,r13,r11 /* Check permission */ 588 589#ifdef CONFIG_PTE_64BIT 590#ifdef CONFIG_SMP 591 subf r13,r11,r12 /* create false data dep */ 592 lwzx r13,r11,r13 /* Get upper pte bits */ 593#else 594 lwz r13,0(r12) /* Get upper pte bits */ 595#endif 596#endif 597 598 bne 2f /* Bail if permission mismach */ 599 600 /* Jump to common TLB load point */ 601 b finish_tlb_load 602 6032: 604 /* The bailout. Restore registers to pre-exception conditions 605 * and call the heavyweights to help us out. 606 */ 607 mfspr r10, SPRN_SPRG_THREAD 608 lwz r11, THREAD_NORMSAVE(3)(r10) 609 mtcr r11 610 lwz r13, THREAD_NORMSAVE(2)(r10) 611 lwz r12, THREAD_NORMSAVE(1)(r10) 612 lwz r11, THREAD_NORMSAVE(0)(r10) 613 mfspr r10, SPRN_SPRG_RSCRATCH0 614 b InstructionStorage 615 616/* Define SPE handlers for e200 and e500v2 */ 617#ifdef CONFIG_SPE 618 /* SPE Unavailable */ 619 START_EXCEPTION(SPEUnavailable) 620 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL) 621 beq 1f 622 bl load_up_spe 623 b fast_exception_return 6241: addi r3,r1,STACK_FRAME_OVERHEAD 625 EXC_XFER_EE_LITE(0x2010, KernelSPE) 626#elif defined(CONFIG_SPE_POSSIBLE) 627 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ 628 unknown_exception, EXC_XFER_EE) 629#endif /* CONFIG_SPE_POSSIBLE */ 630 631 /* SPE Floating Point Data */ 632#ifdef CONFIG_SPE 633 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, 634 SPEFloatingPointException, EXC_XFER_EE) 635 636 /* SPE Floating Point Round */ 637 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ 638 SPEFloatingPointRoundException, EXC_XFER_EE) 639#elif defined(CONFIG_SPE_POSSIBLE) 640 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, 641 unknown_exception, EXC_XFER_EE) 642 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ 643 unknown_exception, EXC_XFER_EE) 644#endif /* CONFIG_SPE_POSSIBLE */ 645 646 647 /* Performance Monitor */ 648 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ 649 performance_monitor_exception, EXC_XFER_STD) 650 651 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD) 652 653 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ 654 CriticalDoorbell, unknown_exception) 655 656 /* Debug Interrupt */ 657 DEBUG_DEBUG_EXCEPTION 658 DEBUG_CRIT_EXCEPTION 659 660 GUEST_DOORBELL_EXCEPTION 661 662 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ 663 unknown_exception) 664 665 /* Hypercall */ 666 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE) 667 668 /* Embedded Hypervisor Privilege */ 669 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE) 670 671interrupt_end: 672 673/* 674 * Local functions 675 */ 676 677/* 678 * Both the instruction and data TLB miss get to this 679 * point to load the TLB. 680 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use 681 * r11 - TLB (info from Linux PTE) 682 * r12 - available to use 683 * r13 - upper bits of PTE (if PTE_64BIT) or available to use 684 * CR5 - results of addr >= PAGE_OFFSET 685 * MAS0, MAS1 - loaded with proper value when we get here 686 * MAS2, MAS3 - will need additional info from Linux PTE 687 * Upon exit, we reload everything and RFI. 688 */ 689finish_tlb_load: 690#ifdef CONFIG_HUGETLB_PAGE 691 cmpwi 6, r10, 0 /* check for huge page */ 692 beq 6, finish_tlb_load_cont /* !huge */ 693 694 /* Alas, we need more scratch registers for hugepages */ 695 mfspr r12, SPRN_SPRG_THREAD 696 stw r14, THREAD_NORMSAVE(4)(r12) 697 stw r15, THREAD_NORMSAVE(5)(r12) 698 stw r16, THREAD_NORMSAVE(6)(r12) 699 stw r17, THREAD_NORMSAVE(7)(r12) 700 701 /* Get the next_tlbcam_idx percpu var */ 702#ifdef CONFIG_SMP 703 lwz r12, THREAD_INFO-THREAD(r12) 704 lwz r15, TI_CPU(r12) 705 lis r14, __per_cpu_offset@h 706 ori r14, r14, __per_cpu_offset@l 707 rlwinm r15, r15, 2, 0, 29 708 lwzx r16, r14, r15 709#else 710 li r16, 0 711#endif 712 lis r17, next_tlbcam_idx@h 713 ori r17, r17, next_tlbcam_idx@l 714 add r17, r17, r16 /* r17 = *next_tlbcam_idx */ 715 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ 716 717 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ 718 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ 719 mtspr SPRN_MAS0, r14 720 721 /* Extract TLB1CFG(NENTRY) */ 722 mfspr r16, SPRN_TLB1CFG 723 andi. r16, r16, 0xfff 724 725 /* Update next_tlbcam_idx, wrapping when necessary */ 726 addi r15, r15, 1 727 cmpw r15, r16 728 blt 100f 729 lis r14, tlbcam_index@h 730 ori r14, r14, tlbcam_index@l 731 lwz r15, 0(r14) 732100: stw r15, 0(r17) 733 734 /* 735 * Calc MAS1_TSIZE from r10 (which has pshift encoded) 736 * tlb_enc = (pshift - 10). 737 */ 738 subi r15, r10, 10 739 mfspr r16, SPRN_MAS1 740 rlwimi r16, r15, 7, 20, 24 741 mtspr SPRN_MAS1, r16 742 743 /* copy the pshift for use later */ 744 mr r14, r10 745 746 /* fall through */ 747 748#endif /* CONFIG_HUGETLB_PAGE */ 749 750 /* 751 * We set execute, because we don't have the granularity to 752 * properly set this at the page level (Linux problem). 753 * Many of these bits are software only. Bits we don't set 754 * here we (properly should) assume have the appropriate value. 755 */ 756finish_tlb_load_cont: 757#ifdef CONFIG_PTE_64BIT 758 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ 759 andi. r10, r11, _PAGE_DIRTY 760 bne 1f 761 li r10, MAS3_SW | MAS3_UW 762 andc r12, r12, r10 7631: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ 764 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ 7652: mtspr SPRN_MAS3, r12 766BEGIN_MMU_FTR_SECTION 767 srwi r10, r13, 12 /* grab RPN[12:31] */ 768 mtspr SPRN_MAS7, r10 769END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) 770#else 771 li r10, (_PAGE_EXEC | _PAGE_PRESENT) 772 mr r13, r11 773 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ 774 and r12, r11, r10 775 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ 776 slwi r10, r12, 1 777 or r10, r10, r12 778 iseleq r12, r12, r10 779 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ 780 mtspr SPRN_MAS3, r13 781#endif 782 783 mfspr r12, SPRN_MAS2 784#ifdef CONFIG_PTE_64BIT 785 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ 786#else 787 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ 788#endif 789#ifdef CONFIG_HUGETLB_PAGE 790 beq 6, 3f /* don't mask if page isn't huge */ 791 li r13, 1 792 slw r13, r13, r14 793 subi r13, r13, 1 794 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ 795 andc r12, r12, r13 /* mask off ea bits within the page */ 796#endif 7973: mtspr SPRN_MAS2, r12 798 799#ifdef CONFIG_E200 800 /* Round robin TLB1 entries assignment */ 801 mfspr r12, SPRN_MAS0 802 803 /* Extract TLB1CFG(NENTRY) */ 804 mfspr r11, SPRN_TLB1CFG 805 andi. r11, r11, 0xfff 806 807 /* Extract MAS0(NV) */ 808 andi. r13, r12, 0xfff 809 addi r13, r13, 1 810 cmpw 0, r13, r11 811 addi r12, r12, 1 812 813 /* check if we need to wrap */ 814 blt 7f 815 816 /* wrap back to first free tlbcam entry */ 817 lis r13, tlbcam_index@ha 818 lwz r13, tlbcam_index@l(r13) 819 rlwimi r12, r13, 0, 20, 31 8207: 821 mtspr SPRN_MAS0,r12 822#endif /* CONFIG_E200 */ 823 824tlb_write_entry: 825 tlbwe 826 827 /* Done...restore registers and get out of here. */ 828 mfspr r10, SPRN_SPRG_THREAD 829#ifdef CONFIG_HUGETLB_PAGE 830 beq 6, 8f /* skip restore for 4k page faults */ 831 lwz r14, THREAD_NORMSAVE(4)(r10) 832 lwz r15, THREAD_NORMSAVE(5)(r10) 833 lwz r16, THREAD_NORMSAVE(6)(r10) 834 lwz r17, THREAD_NORMSAVE(7)(r10) 835#endif 8368: lwz r11, THREAD_NORMSAVE(3)(r10) 837 mtcr r11 838 lwz r13, THREAD_NORMSAVE(2)(r10) 839 lwz r12, THREAD_NORMSAVE(1)(r10) 840 lwz r11, THREAD_NORMSAVE(0)(r10) 841 mfspr r10, SPRN_SPRG_RSCRATCH0 842 rfi /* Force context change */ 843 844#ifdef CONFIG_SPE 845/* Note that the SPE support is closely modeled after the AltiVec 846 * support. Changes to one are likely to be applicable to the 847 * other! */ 848_GLOBAL(load_up_spe) 849/* 850 * Disable SPE for the task which had SPE previously, 851 * and save its SPE registers in its thread_struct. 852 * Enables SPE for use in the kernel on return. 853 * On SMP we know the SPE units are free, since we give it up every 854 * switch. -- Kumar 855 */ 856 mfmsr r5 857 oris r5,r5,MSR_SPE@h 858 mtmsr r5 /* enable use of SPE now */ 859 isync 860/* 861 * For SMP, we don't do lazy SPE switching because it just gets too 862 * horrendously complex, especially when a task switches from one CPU 863 * to another. Instead we call giveup_spe in switch_to. 864 */ 865#ifndef CONFIG_SMP 866 lis r3,last_task_used_spe@ha 867 lwz r4,last_task_used_spe@l(r3) 868 cmpi 0,r4,0 869 beq 1f 870 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ 871 SAVE_32EVRS(0,r10,r4,THREAD_EVR0) 872 evxor evr10, evr10, evr10 /* clear out evr10 */ 873 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ 874 li r5,THREAD_ACC 875 evstddx evr10, r4, r5 /* save off accumulator */ 876 lwz r5,PT_REGS(r4) 877 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 878 lis r10,MSR_SPE@h 879 andc r4,r4,r10 /* disable SPE for previous task */ 880 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 8811: 882#endif /* !CONFIG_SMP */ 883 /* enable use of SPE after return */ 884 oris r9,r9,MSR_SPE@h 885 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ 886 li r4,1 887 li r10,THREAD_ACC 888 stw r4,THREAD_USED_SPE(r5) 889 evlddx evr4,r10,r5 890 evmra evr4,evr4 891 REST_32EVRS(0,r10,r5,THREAD_EVR0) 892#ifndef CONFIG_SMP 893 subi r4,r5,THREAD 894 stw r4,last_task_used_spe@l(r3) 895#endif /* !CONFIG_SMP */ 896 blr 897 898/* 899 * SPE unavailable trap from kernel - print a message, but let 900 * the task use SPE in the kernel until it returns to user mode. 901 */ 902KernelSPE: 903 lwz r3,_MSR(r1) 904 oris r3,r3,MSR_SPE@h 905 stw r3,_MSR(r1) /* enable use of SPE after return */ 906#ifdef CONFIG_PRINTK 907 lis r3,87f@h 908 ori r3,r3,87f@l 909 mr r4,r2 /* current */ 910 lwz r5,_NIP(r1) 911 bl printk 912#endif 913 b ret_from_except 914#ifdef CONFIG_PRINTK 91587: .string "SPE used in kernel (task=%p, pc=%x) \n" 916#endif 917 .align 4,0 918 919#endif /* CONFIG_SPE */ 920 921/* 922 * Translate the effec addr in r3 to phys addr. The phys addr will be put 923 * into r3(higher 32bit) and r4(lower 32bit) 924 */ 925get_phys_addr: 926 mfmsr r8 927 mfspr r9,SPRN_PID 928 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 929 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ 930 mtspr SPRN_MAS6,r9 931 932 tlbsx 0,r3 /* must succeed */ 933 934 mfspr r8,SPRN_MAS1 935 mfspr r12,SPRN_MAS3 936 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ 937 li r10,1024 938 slw r10,r10,r9 /* r10 = page size */ 939 addi r10,r10,-1 940 and r11,r3,r10 /* r11 = page offset */ 941 andc r4,r12,r10 /* r4 = page base */ 942 or r4,r4,r11 /* r4 = devtree phys addr */ 943#ifdef CONFIG_PHYS_64BIT 944 mfspr r3,SPRN_MAS7 945#endif 946 blr 947 948/* 949 * Global functions 950 */ 951 952#ifdef CONFIG_E200 953/* Adjust or setup IVORs for e200 */ 954_GLOBAL(__setup_e200_ivors) 955 li r3,DebugDebug@l 956 mtspr SPRN_IVOR15,r3 957 li r3,SPEUnavailable@l 958 mtspr SPRN_IVOR32,r3 959 li r3,SPEFloatingPointData@l 960 mtspr SPRN_IVOR33,r3 961 li r3,SPEFloatingPointRound@l 962 mtspr SPRN_IVOR34,r3 963 sync 964 blr 965#endif 966 967#ifdef CONFIG_E500 968#ifndef CONFIG_PPC_E500MC 969/* Adjust or setup IVORs for e500v1/v2 */ 970_GLOBAL(__setup_e500_ivors) 971 li r3,DebugCrit@l 972 mtspr SPRN_IVOR15,r3 973 li r3,SPEUnavailable@l 974 mtspr SPRN_IVOR32,r3 975 li r3,SPEFloatingPointData@l 976 mtspr SPRN_IVOR33,r3 977 li r3,SPEFloatingPointRound@l 978 mtspr SPRN_IVOR34,r3 979 li r3,PerformanceMonitor@l 980 mtspr SPRN_IVOR35,r3 981 sync 982 blr 983#else 984/* Adjust or setup IVORs for e500mc */ 985_GLOBAL(__setup_e500mc_ivors) 986 li r3,DebugDebug@l 987 mtspr SPRN_IVOR15,r3 988 li r3,PerformanceMonitor@l 989 mtspr SPRN_IVOR35,r3 990 li r3,Doorbell@l 991 mtspr SPRN_IVOR36,r3 992 li r3,CriticalDoorbell@l 993 mtspr SPRN_IVOR37,r3 994 sync 995 blr 996 997/* setup ehv ivors for */ 998_GLOBAL(__setup_ehv_ivors) 999 li r3,GuestDoorbell@l 1000 mtspr SPRN_IVOR38,r3 1001 li r3,CriticalGuestDoorbell@l 1002 mtspr SPRN_IVOR39,r3 1003 li r3,Hypercall@l 1004 mtspr SPRN_IVOR40,r3 1005 li r3,Ehvpriv@l 1006 mtspr SPRN_IVOR41,r3 1007 sync 1008 blr 1009#endif /* CONFIG_PPC_E500MC */ 1010#endif /* CONFIG_E500 */ 1011 1012#ifdef CONFIG_SPE 1013/* 1014 * extern void giveup_spe(struct task_struct *prev) 1015 * 1016 */ 1017_GLOBAL(giveup_spe) 1018 mfmsr r5 1019 oris r5,r5,MSR_SPE@h 1020 mtmsr r5 /* enable use of SPE now */ 1021 isync 1022 cmpi 0,r3,0 1023 beqlr- /* if no previous owner, done */ 1024 addi r3,r3,THREAD /* want THREAD of task */ 1025 lwz r5,PT_REGS(r3) 1026 cmpi 0,r5,0 1027 SAVE_32EVRS(0, r4, r3, THREAD_EVR0) 1028 evxor evr6, evr6, evr6 /* clear out evr6 */ 1029 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ 1030 li r4,THREAD_ACC 1031 evstddx evr6, r4, r3 /* save off accumulator */ 1032 beq 1f 1033 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) 1034 lis r3,MSR_SPE@h 1035 andc r4,r4,r3 /* disable SPE for previous task */ 1036 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) 10371: 1038#ifndef CONFIG_SMP 1039 li r5,0 1040 lis r4,last_task_used_spe@ha 1041 stw r5,last_task_used_spe@l(r4) 1042#endif /* !CONFIG_SMP */ 1043 blr 1044#endif /* CONFIG_SPE */ 1045 1046/* 1047 * extern void abort(void) 1048 * 1049 * At present, this routine just applies a system reset. 1050 */ 1051_GLOBAL(abort) 1052 li r13,0 1053 mtspr SPRN_DBCR0,r13 /* disable all debug events */ 1054 isync 1055 mfmsr r13 1056 ori r13,r13,MSR_DE@l /* Enable Debug Events */ 1057 mtmsr r13 1058 isync 1059 mfspr r13,SPRN_DBCR0 1060 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h 1061 mtspr SPRN_DBCR0,r13 1062 isync 1063 1064_GLOBAL(set_context) 1065 1066#ifdef CONFIG_BDI_SWITCH 1067 /* Context switch the PTE pointer for the Abatron BDI2000. 1068 * The PGDIR is the second parameter. 1069 */ 1070 lis r5, abatron_pteptrs@h 1071 ori r5, r5, abatron_pteptrs@l 1072 stw r4, 0x4(r5) 1073#endif 1074 mtspr SPRN_PID,r3 1075 isync /* Force context change */ 1076 blr 1077 1078_GLOBAL(flush_dcache_L1) 1079 mfspr r3,SPRN_L1CFG0 1080 1081 rlwinm r5,r3,9,3 /* Extract cache block size */ 1082 twlgti r5,1 /* Only 32 and 64 byte cache blocks 1083 * are currently defined. 1084 */ 1085 li r4,32 1086 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - 1087 * log2(number of ways) 1088 */ 1089 slw r5,r4,r5 /* r5 = cache block size */ 1090 1091 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ 1092 mulli r7,r7,13 /* An 8-way cache will require 13 1093 * loads per set. 1094 */ 1095 slw r7,r7,r6 1096 1097 /* save off HID0 and set DCFA */ 1098 mfspr r8,SPRN_HID0 1099 ori r9,r8,HID0_DCFA@l 1100 mtspr SPRN_HID0,r9 1101 isync 1102 1103 lis r4,KERNELBASE@h 1104 mtctr r7 1105 11061: lwz r3,0(r4) /* Load... */ 1107 add r4,r4,r5 1108 bdnz 1b 1109 1110 msync 1111 lis r4,KERNELBASE@h 1112 mtctr r7 1113 11141: dcbf 0,r4 /* ...and flush. */ 1115 add r4,r4,r5 1116 bdnz 1b 1117 1118 /* restore HID0 */ 1119 mtspr SPRN_HID0,r8 1120 isync 1121 1122 blr 1123 1124/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */ 1125_GLOBAL(__flush_disable_L1) 1126 mflr r10 1127 bl flush_dcache_L1 /* Flush L1 d-cache */ 1128 mtlr r10 1129 1130 mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */ 1131 li r5, 2 1132 rlwimi r4, r5, 0, 3 1133 1134 msync 1135 isync 1136 mtspr SPRN_L1CSR0, r4 1137 isync 1138 11391: mfspr r4, SPRN_L1CSR0 /* Wait for the invalidate to finish */ 1140 andi. r4, r4, 2 1141 bne 1b 1142 1143 mfspr r4, SPRN_L1CSR1 /* Invalidate and disable i-cache */ 1144 li r5, 2 1145 rlwimi r4, r5, 0, 3 1146 1147 mtspr SPRN_L1CSR1, r4 1148 isync 1149 1150 blr 1151 1152#ifdef CONFIG_SMP 1153/* When we get here, r24 needs to hold the CPU # */ 1154 .globl __secondary_start 1155__secondary_start: 1156 LOAD_REG_ADDR_PIC(r3, tlbcam_index) 1157 lwz r3,0(r3) 1158 mtctr r3 1159 li r26,0 /* r26 safe? */ 1160 1161 bl switch_to_as1 1162 mr r27,r3 /* tlb entry */ 1163 /* Load each CAM entry */ 11641: mr r3,r26 1165 bl loadcam_entry 1166 addi r26,r26,1 1167 bdnz 1b 1168 mr r3,r27 /* tlb entry */ 1169 LOAD_REG_ADDR_PIC(r4, memstart_addr) 1170 lwz r4,0(r4) 1171 mr r5,r25 /* phys kernel start */ 1172 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ 1173 subf r4,r5,r4 /* memstart_addr - phys kernel start */ 1174 li r5,0 /* no device tree */ 1175 li r6,0 /* not boot cpu */ 1176 bl restore_to_as0 1177 1178 1179 lis r3,__secondary_hold_acknowledge@h 1180 ori r3,r3,__secondary_hold_acknowledge@l 1181 stw r24,0(r3) 1182 1183 li r3,0 1184 mr r4,r24 /* Why? */ 1185 bl call_setup_cpu 1186 1187 /* get current_thread_info and current */ 1188 lis r1,secondary_ti@ha 1189 lwz r1,secondary_ti@l(r1) 1190 lwz r2,TI_TASK(r1) 1191 1192 /* stack */ 1193 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 1194 li r0,0 1195 stw r0,0(r1) 1196 1197 /* ptr to current thread */ 1198 addi r4,r2,THREAD /* address of our thread_struct */ 1199 mtspr SPRN_SPRG_THREAD,r4 1200 1201 /* Setup the defaults for TLB entries */ 1202 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l 1203 mtspr SPRN_MAS4,r4 1204 1205 /* Jump to start_secondary */ 1206 lis r4,MSR_KERNEL@h 1207 ori r4,r4,MSR_KERNEL@l 1208 lis r3,start_secondary@h 1209 ori r3,r3,start_secondary@l 1210 mtspr SPRN_SRR0,r3 1211 mtspr SPRN_SRR1,r4 1212 sync 1213 rfi 1214 sync 1215 1216 .globl __secondary_hold_acknowledge 1217__secondary_hold_acknowledge: 1218 .long -1 1219#endif 1220 1221/* 1222 * Create a tlb entry with the same effective and physical address as 1223 * the tlb entry used by the current running code. But set the TS to 1. 1224 * Then switch to the address space 1. It will return with the r3 set to 1225 * the ESEL of the new created tlb. 1226 */ 1227_GLOBAL(switch_to_as1) 1228 mflr r5 1229 1230 /* Find a entry not used */ 1231 mfspr r3,SPRN_TLB1CFG 1232 andi. r3,r3,0xfff 1233 mfspr r4,SPRN_PID 1234 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ 1235 mtspr SPRN_MAS6,r4 12361: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1237 addi r3,r3,-1 1238 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1239 mtspr SPRN_MAS0,r4 1240 tlbre 1241 mfspr r4,SPRN_MAS1 1242 andis. r4,r4,MAS1_VALID@h 1243 bne 1b 1244 1245 /* Get the tlb entry used by the current running code */ 1246 bl 0f 12470: mflr r4 1248 tlbsx 0,r4 1249 1250 mfspr r4,SPRN_MAS1 1251 ori r4,r4,MAS1_TS /* Set the TS = 1 */ 1252 mtspr SPRN_MAS1,r4 1253 1254 mfspr r4,SPRN_MAS0 1255 rlwinm r4,r4,0,~MAS0_ESEL_MASK 1256 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1257 mtspr SPRN_MAS0,r4 1258 tlbwe 1259 isync 1260 sync 1261 1262 mfmsr r4 1263 ori r4,r4,MSR_IS | MSR_DS 1264 mtspr SPRN_SRR0,r5 1265 mtspr SPRN_SRR1,r4 1266 sync 1267 rfi 1268 1269/* 1270 * Restore to the address space 0 and also invalidate the tlb entry created 1271 * by switch_to_as1. 1272 * r3 - the tlb entry which should be invalidated 1273 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) 1274 * r5 - device tree virtual address. If r4 is 0, r5 is ignored. 1275 * r6 - boot cpu 1276*/ 1277_GLOBAL(restore_to_as0) 1278 mflr r0 1279 1280 bl 0f 12810: mflr r9 1282 addi r9,r9,1f - 0b 1283 1284 /* 1285 * We may map the PAGE_OFFSET in AS0 to a different physical address, 1286 * so we need calculate the right jump and device tree address based 1287 * on the offset passed by r4. 1288 */ 1289 add r9,r9,r4 1290 add r5,r5,r4 1291 add r0,r0,r4 1292 12932: mfmsr r7 1294 li r8,(MSR_IS | MSR_DS) 1295 andc r7,r7,r8 1296 1297 mtspr SPRN_SRR0,r9 1298 mtspr SPRN_SRR1,r7 1299 sync 1300 rfi 1301 1302 /* Invalidate the temporary tlb entry for AS1 */ 13031: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ 1304 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 1305 mtspr SPRN_MAS0,r9 1306 tlbre 1307 mfspr r9,SPRN_MAS1 1308 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ 1309 mtspr SPRN_MAS1,r9 1310 tlbwe 1311 isync 1312 1313 cmpwi r4,0 1314 cmpwi cr1,r6,0 1315 cror eq,4*cr1+eq,eq 1316 bne 3f /* offset != 0 && is_boot_cpu */ 1317 mtlr r0 1318 blr 1319 1320 /* 1321 * The PAGE_OFFSET will map to a different physical address, 1322 * jump to _start to do another relocation again. 1323 */ 13243: mr r3,r5 1325 bl _start 1326 1327/* 1328 * We put a few things here that have to be page-aligned. This stuff 1329 * goes at the beginning of the data segment, which is page-aligned. 1330 */ 1331 .data 1332 .align 12 1333 .globl sdata 1334sdata: 1335 .globl empty_zero_page 1336empty_zero_page: 1337 .space 4096 1338 .globl swapper_pg_dir 1339swapper_pg_dir: 1340 .space PGD_TABLE_SIZE 1341 1342/* 1343 * Room for two PTE pointers, usually the kernel and current user pointers 1344 * to their respective root page table. 1345 */ 1346abatron_pteptrs: 1347 .space 8 1348