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Searched refs:pll (Results 1 – 200 of 310) sorted by relevance

12

/linux-4.1.27/drivers/video/fbdev/aty/
Dmach64_ct.c17 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
20 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
126 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
127 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
129 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
135 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
141 if (pll->xres != 0) { in aty_dsp_gt()
[all …]
Dmach64_gx.c80 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
123 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
153 pll->ibm514.m = RGB514_clocks[i].m; in aty_var_to_pll_514()
154 pll->ibm514.n = RGB514_clocks[i].n; in aty_var_to_pll_514()
161 const union aty_pll *pll) in aty_pll_514_to_var() argument
166 df = pll->ibm514.m >> 6; in aty_pll_514_to_var()
167 vco_div_count = pll->ibm514.m & 0x3f; in aty_pll_514_to_var()
168 ref_div_count = pll->ibm514.n; in aty_pll_514_to_var()
175 const union aty_pll *pll) in aty_set_pll_514() argument
185 aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */ in aty_set_pll_514()
[all …]
Dradeon_base.c439 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
443 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
447 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
583 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
584 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
585 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
586 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
604 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
605 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
606 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
[all …]
Datyfb.h136 union aty_pll pll; member
303 const union aty_pll * pll, u32 bpp, u32 accel);
318 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
319 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
320 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
321 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
322 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
323 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
335 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
Datyfb_base.c310 static int pll; variable
373 int pll, mclk, xclk, ecp_max; member
446 par->pll_limits.pll_max = aty_chips[i].pll; in correct_chipset()
574 par->pll.ct.xres = 0; in atyfb_get_pixclock()
578 par->pll.ct.xres = var->xres; in atyfb_get_pixclock()
1321 var->bits_per_pixel, &par->pll); in atyfb_set_par()
1340 par->dac_ops->set_dac(info, &par->pll, in atyfb_set_par()
1342 par->pll_ops->set_pll(info, &par->pll); in atyfb_set_par()
1346 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll); in atyfb_set_par()
1534 union aty_pll pll; in atyfb_check_var() local
[all …]
Daty128fb.c451 struct aty128_pll pll; member
1340 static void aty128_set_pll(struct aty128_pll *pll, in aty128_set_pll() argument
1362 div3 |= pll->feedback_divider; in aty128_set_pll()
1364 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1380 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, in aty128_var_to_pll() argument
1402 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1414 pll->feedback_divider = round_div(n, d); in aty128_var_to_pll()
1415 pll->vclk = vclk; in aty128_var_to_pll()
1418 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
1419 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
/linux-4.1.27/drivers/clk/tegra/
Dclk-pll.c223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
227 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
230 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
233 val = pll_readl_misc(pll); in clk_pll_enable_lock()
234 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
235 pll_writel_misc(val, pll); in clk_pll_enable_lock()
238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
244 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
245 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
249 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
[all …]
DMakefile6 obj-y += clk-pll.o
7 obj-y += clk-pll-out.o
/linux-4.1.27/drivers/media/i2c/
Dsmiapp-pll.c61 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
63 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
64 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
65 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
66 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
67 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
69 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
70 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
72 dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz); in print_pll()
73 dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz); in print_pll()
[all …]
Daptina-pll.c31 struct aptina_pll *pll) in aptina_pll_calculate() argument
41 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
43 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
44 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
49 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
55 div = gcd(pll->pix_clock, pll->ext_clock); in aptina_pll_calculate()
56 pll->m = pll->pix_clock / div; in aptina_pll_calculate()
57 div = pll->ext_clock / div; in aptina_pll_calculate()
69 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); in aptina_pll_calculate()
71 (pll->ext_clock / limits->n_min * pll->m)); in aptina_pll_calculate()
[all …]
Dmt9m032.c282 struct aptina_pll pll; in mt9m032_setup_pll() local
286 pll.ext_clock = pdata->ext_clock; in mt9m032_setup_pll()
287 pll.pix_clock = pdata->pix_clock; in mt9m032_setup_pll()
289 ret = aptina_pll_calculate(&client->dev, &limits, &pll); in mt9m032_setup_pll()
296 (pll.m << MT9M032_PLL_CONFIG1_MUL_SHIFT) | in mt9m032_setup_pll()
297 ((pll.n - 1) & MT9M032_PLL_CONFIG1_PREDIV_MASK)); in mt9m032_setup_pll()
307 reg_val = (pll.p1 == 6 ? MT9M032_FORMATTER1_PLL_P1_6 : 0) in mt9m032_setup_pll()
Daptina-pll.h54 struct aptina_pll *pll);
Dov2659.c233 struct ov2659_pll_ctrl pll; member
943 ov2659->pll.ctrl1 = ctrl1_reg; in ov2659_pll_calc_params()
944 ov2659->pll.ctrl2 = ctrl2_reg; in ov2659_pll_calc_params()
945 ov2659->pll.ctrl3 = ctrl3_reg; in ov2659_pll_calc_params()
956 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1}, in ov2659_set_pixel_clock()
957 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2}, in ov2659_set_pixel_clock()
958 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3}, in ov2659_set_pixel_clock()
DMakefile9 obj-$(CONFIG_VIDEO_APTINA_PLL) += aptina-pll.o
76 obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
Dmt9p031.c135 struct aptina_pll pll; member
260 mt9p031->pll.ext_clock = pdata->ext_freq; in mt9p031_clk_setup()
261 mt9p031->pll.pix_clock = pdata->target_freq; in mt9p031_clk_setup()
264 return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); in mt9p031_clk_setup()
281 (mt9p031->pll.m << 8) | (mt9p031->pll.n - 1)); in mt9p031_pll_enable()
285 ret = mt9p031_write(client, MT9P031_PLL_CONFIG_2, mt9p031->pll.p1 - 1); in mt9p031_pll_enable()
Dsmiapp-pll.h105 struct smiapp_pll *pll);
/linux-4.1.27/drivers/clk/qcom/
Dclk-pll.c39 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
80 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
84 regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_disable()
89 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0); in clk_pll_disable()
95 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
100 regmap_read(pll->clkr.regmap, pll->l_reg, &l); in clk_pll_recalc_rate()
[all …]
Dclk-pll.h83 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
85 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
DMakefile5 clk-qcom-y += clk-pll.o
/linux-4.1.27/drivers/clk/pistachio/
Dclk-pll.c60 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
62 return readl(pll->base + reg); in pll_readl()
65 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
67 writel(val, pll->base + reg); in pll_writel()
84 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref, in pll_get_params() argument
89 for (i = 0; i < pll->nr_rates; i++) { in pll_get_params()
90 if (pll->rates[i].fref == fref && pll->rates[i].fout == fout) in pll_get_params()
91 return &pll->rates[i]; in pll_get_params()
100 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_round_rate() local
103 for (i = 0; i < pll->nr_rates; i++) { in pll_round_rate()
[all …]
DMakefile2 obj-y += clk-pll.o
/linux-4.1.27/arch/arm/mach-imx/
Dclk-pllv3.c49 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
52 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; in clk_pllv3_wait_lock()
55 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
60 if (readl_relaxed(pll->base) & BM_PLL_LOCK) in clk_pllv3_wait_lock()
67 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; in clk_pllv3_wait_lock()
72 struct clk_pllv3 *pll = to_clk_pllv3(hw); in clk_pllv3_prepare() local
75 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
76 if (pll->powerup_set) in clk_pllv3_prepare()
80 writel_relaxed(val, pll->base); in clk_pllv3_prepare()
82 return clk_pllv3_wait_lock(pll); in clk_pllv3_prepare()
[all …]
Dclk-pllv1.c41 struct clk_pllv1 *pll = to_clk_pllv1(hw); in clk_pllv1_recalc_rate() local
48 reg = readl(pll->base); in clk_pllv1_recalc_rate()
103 struct clk_pllv1 *pll; in imx_clk_pllv1() local
107 pll = kmalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pllv1()
108 if (!pll) in imx_clk_pllv1()
111 pll->base = base; in imx_clk_pllv1()
119 pll->hw.init = &init; in imx_clk_pllv1()
121 clk = clk_register(NULL, &pll->hw); in imx_clk_pllv1()
123 kfree(pll); in imx_clk_pllv1()
Dclk-pllv2.c116 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_recalc_rate() local
118 pllbase = pll->base; in clk_pllv2_recalc_rate()
160 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_set_rate() local
165 pllbase = pll->base; in clk_pllv2_set_rate()
195 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_prepare() local
200 pllbase = pll->base; in clk_pllv2_prepare()
223 struct clk_pllv2 *pll = to_clk_pllv2(hw); in clk_pllv2_unprepare() local
227 pllbase = pll->base; in clk_pllv2_unprepare()
243 struct clk_pllv2 *pll; in imx_clk_pllv2() local
247 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pllv2()
[all …]
Dclk-cpu.c20 struct clk *pll; member
42 return clk_round_rate(cpu->pll, rate); in clk_cpu_round_rate()
57 ret = clk_set_rate(cpu->pll, rate); in clk_cpu_set_rate()
59 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
63 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
78 struct clk *div, struct clk *mux, struct clk *pll, in imx_clk_cpu() argument
91 cpu->pll = pll; in imx_clk_cpu()
/linux-4.1.27/drivers/clk/rockchip/
Dclk-pll.c53 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
55 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
58 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
69 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
70 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
74 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
88 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) in rockchip_pll_wait_lock() argument
95 ret = regmap_read(grf, pll->lock_offset, &val); in rockchip_pll_wait_lock()
102 if (val & BIT(pll->lock_shift)) in rockchip_pll_wait_lock()
133 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_rk3066_pll_recalc_rate() local
[all …]
DMakefile7 obj-y += clk-pll.o
/linux-4.1.27/drivers/clk/mxs/
Dclk-pll.c41 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
43 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
54 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
59 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
61 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
68 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable() local
70 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
76 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
78 return pll->rate; in clk_pll_recalc_rate()
[all …]
DMakefile5 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
Dclk-imx23.c88 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, enumerator
120 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Dhdmi_pll.c25 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s) in hdmi_pll_dump() argument
28 hdmi_read_reg(pll->base, r)) in hdmi_pll_dump()
41 void hdmi_pll_compute(struct hdmi_pll_data *pll, in hdmi_pll_compute() argument
49 const struct dss_pll_hw *hw = pll->pll.hw; in hdmi_pll_compute()
51 clkin = clk_get_rate(pll->pll.clkin); in hdmi_pll_compute()
103 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_enable() local
104 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable()
118 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); in hdmi_pll_disable() local
119 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable()
181 struct dss_pll *pll = &hpll->pll; in dsi_init_pll_data() local
[all …]
Dvideo-pll.c26 struct dss_pll pll; member
62 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
71 dss_ctrl_pll_enable(pll->id, true); in dss_video_pll_enable()
75 r = dss_pll_wait_reset_done(pll); in dss_video_pll_enable()
85 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_enable()
91 static void dss_video_pll_disable(struct dss_pll *pll) in dss_video_pll_disable() argument
93 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_disable()
99 dss_ctrl_pll_enable(pll->id, false); in dss_video_pll_disable()
142 struct dss_pll *pll; in dss_video_pll_init() local
[all …]
Dpll.c41 int dss_pll_register(struct dss_pll *pll) in dss_pll_register() argument
47 dss_plls[i] = pll; in dss_pll_register()
55 void dss_pll_unregister(struct dss_pll *pll) in dss_pll_unregister() argument
60 if (dss_plls[i] == pll) { in dss_pll_unregister()
79 int dss_pll_enable(struct dss_pll *pll) in dss_pll_enable() argument
83 r = clk_prepare_enable(pll->clkin); in dss_pll_enable()
87 if (pll->regulator) { in dss_pll_enable()
88 r = regulator_enable(pll->regulator); in dss_pll_enable()
93 r = pll->ops->enable(pll); in dss_pll_enable()
100 if (pll->regulator) in dss_pll_enable()
[all …]
Ddpi.c47 struct dss_pll *pll; member
142 struct dss_pll *pll; member
214 return dss_pll_hsdiv_calc(ctx->pll, clkdco, in dpi_calc_pll_cb()
236 ctx->pll = dpi->pll; in dpi_dsi_clk_calc()
243 clkin = clk_get_rate(ctx->pll->clkin); in dpi_dsi_clk_calc()
245 return dss_pll_calc(ctx->pll, clkin, in dpi_dsi_clk_calc()
293 r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo); in dpi_set_dsi_clk()
343 if (dpi->pll) in dpi_set_mode()
417 if (dpi->pll) { in dpi_display_enable()
418 r = dss_pll_enable(dpi->pll); in dpi_display_enable()
[all …]
Ddss.h134 int (*enable)(struct dss_pll *pll);
135 void (*disable)(struct dss_pll *pll);
136 int (*set_config)(struct dss_pll *pll,
275 void dss_video_pll_uninit(struct dss_pll *pll);
452 int dss_pll_register(struct dss_pll *pll);
453 void dss_pll_unregister(struct dss_pll *pll);
455 int dss_pll_enable(struct dss_pll *pll);
456 void dss_pll_disable(struct dss_pll *pll);
457 int dss_pll_set_config(struct dss_pll *pll,
460 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
[all …]
Dhdmi4.c183 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
185 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
191 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); in hdmi_power_on_full()
236 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_on_full()
254 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_off_full()
298 hdmi_pll_dump(&hdmi.pll, s); in hdmi_dump_regs()
669 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); in omapdss_hdmihw_probe()
712 hdmi_pll_uninit(&hdmi.pll); in omapdss_hdmihw_probe()
723 hdmi_pll_uninit(&hdmi.pll); in omapdss_hdmihw_remove()
Dhdmi5.c195 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
202 r = dss_pll_enable(&hdmi.pll.pll); in hdmi_power_on_full()
208 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); in hdmi_power_on_full()
253 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_on_full()
271 dss_pll_disable(&hdmi.pll.pll); in hdmi_power_off_full()
319 hdmi_pll_dump(&hdmi.pll, s); in hdmi_dump_regs()
704 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); in omapdss_hdmihw_probe()
747 hdmi_pll_uninit(&hdmi.pll); in omapdss_hdmihw_probe()
758 hdmi_pll_uninit(&hdmi.pll); in omapdss_hdmihw_remove()
Dhdmi.h239 struct dss_pll pll; member
308 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
309 void hdmi_pll_compute(struct hdmi_pll_data *pll,
311 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
345 struct hdmi_pll_data pll; member
DMakefile5 output.o dss-of.o pll.o video-pll.o
Ddsi.c278 struct dss_pll *pll; member
320 struct dss_pll pll; member
1251 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; in dsi_get_pll_hsdiv_dispc_rate()
1258 return dsi->pll.cinfo.clkout[HSDIV_DSI]; in dsi_get_pll_hsdiv_dsi_rate()
1265 return dsi->pll.cinfo.clkdco / 16; in dsi_get_txbyteclkhs()
1395 static int dsi_pll_enable(struct dss_pll *pll) in dsi_pll_enable() argument
1397 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); in dsi_pll_enable()
1473 static void dsi_pll_disable(struct dss_pll *pll) in dsi_pll_disable() argument
1475 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); in dsi_pll_disable()
1485 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; in dsi_dump_dsidev_clocks()
[all …]
/linux-4.1.27/drivers/clk/samsung/
Dclk-pll.c32 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
34 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
37 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
48 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
49 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
53 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
76 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll2126_recalc_rate() local
80 pll_con = __raw_readl(pll->con_reg); in samsung_pll2126_recalc_rate()
109 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll3000_recalc_rate() local
113 pll_con = __raw_readl(pll->con_reg); in samsung_pll3000_recalc_rate()
[all …]
DMakefile5 obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
/linux-4.1.27/arch/mips/ath79/
Dclock.c57 u32 pll; in ar71xx_clocks_init() local
63 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
65 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; in ar71xx_clocks_init()
68 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
71 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
74 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
92 u32 pll; in ar724x_clocks_init() local
97 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
99 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); in ar724x_clocks_init()
102 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_clocks_init()
[all …]
/linux-4.1.27/drivers/clk/at91/
Dclk-pll.c74 struct clk_pll *pll = (struct clk_pll *)dev_id; in clk_pll_irq_handler() local
76 wake_up(&pll->wait); in clk_pll_irq_handler()
77 disable_irq_nosync(pll->irq); in clk_pll_irq_handler()
84 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
85 struct at91_pmc *pmc = pll->pmc; in clk_pll_prepare()
86 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
88 pll->characteristics; in clk_pll_prepare()
89 u8 id = pll->id; in clk_pll_prepare()
102 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
106 out = characteristics->out[pll->range]; in clk_pll_prepare()
[all …]
DMakefile6 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
/linux-4.1.27/arch/arm/mach-davinci/
Dclock.c286 struct pll_data *pll; in clk_sysclk_recalc() local
302 pll = clk->parent->pll_data; in clk_sysclk_recalc()
306 rate = pll->input_rate; in clk_sysclk_recalc()
311 v = __raw_readl(pll->base + clk->div_reg); in clk_sysclk_recalc()
313 plldiv = (v & pll->div_ratio_mask) + 1; in clk_sysclk_recalc()
324 struct pll_data *pll; in davinci_set_sysclk_rate() local
344 pll = clk->parent->pll_data; in davinci_set_sysclk_rate()
350 input = pll->input_rate; in davinci_set_sysclk_rate()
370 if (ratio > pll->div_ratio_mask) in davinci_set_sysclk_rate()
374 v = __raw_readl(pll->base + PLLSTAT); in davinci_set_sysclk_rate()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/c6x/
Dclocks.txt10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
37 ti,c64x+pll-bypass-delay = <200>;
[all …]
/linux-4.1.27/drivers/clk/berlin/
Dberlin2-pll.c62 struct berlin2_pll *pll = to_berlin2_pll(hw); in berlin2_pll_recalc_rate() local
63 struct berlin2_pll_map *map = &pll->map; in berlin2_pll_recalc_rate()
67 val = readl_relaxed(pll->base + SPLL_CTRL0); in berlin2_pll_recalc_rate()
75 val = readl_relaxed(pll->base + SPLL_CTRL1); in berlin2_pll_recalc_rate()
100 struct berlin2_pll *pll; in berlin2_pll_register() local
102 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in berlin2_pll_register()
103 if (!pll) in berlin2_pll_register()
107 memcpy(&pll->map, map, sizeof(*map)); in berlin2_pll_register()
108 pll->base = base; in berlin2_pll_register()
109 pll->hw.init = &init; in berlin2_pll_register()
[all …]
DMakefile1 obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
/linux-4.1.27/drivers/clk/spear/
Dclk-vco-pll.c87 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index() local
97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
127 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate() local
131 if (pll->vco->lock) in clk_pll_recalc_rate()
132 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_recalc_rate()
134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
136 if (pll->vco->lock) in clk_pll_recalc_rate()
137 spin_unlock_irqrestore(pll->vco->lock, flags); in clk_pll_recalc_rate()
147 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate() local
[all …]
DMakefile5 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
/linux-4.1.27/drivers/clk/zynq/
Dpll.c200 struct zynq_pll *pll; in clk_register_zynq_pll() local
213 pll = kmalloc(sizeof(*pll), GFP_KERNEL); in clk_register_zynq_pll()
214 if (!pll) in clk_register_zynq_pll()
218 pll->hw.init = &initd; in clk_register_zynq_pll()
219 pll->pll_ctrl = pll_ctrl; in clk_register_zynq_pll()
220 pll->pll_status = pll_status; in clk_register_zynq_pll()
221 pll->lockbit = lock_index; in clk_register_zynq_pll()
222 pll->lock = lock; in clk_register_zynq_pll()
224 spin_lock_irqsave(pll->lock, flags); in clk_register_zynq_pll()
226 reg = clk_readl(pll->pll_ctrl); in clk_register_zynq_pll()
[all …]
DMakefile3 obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
/linux-4.1.27/drivers/video/fbdev/matrox/
Dg450_pll.c35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; in g450_mnp2vco()
99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; in g450_nextpll()
137 unsigned int mnp, unsigned int pll) in g450_setpll() argument
139 switch (pll) { in g450_setpll()
174 unsigned int mnp, unsigned int pll) in g450_cmppll() argument
180 switch (pll) { in g450_cmppll()
230 unsigned int pll) in g450_testpll() argument
232 return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); in g450_testpll()
235 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { in updatehwstate_clk() argument
236 switch (pll) { in updatehwstate_clk()
[all …]
Dmatroxfb_misc.c128 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f… in matroxfb_PLL_calcclock() argument
132 unsigned int fxtal = pll->ref_freq; in matroxfb_PLL_calcclock()
141 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); in matroxfb_PLL_calcclock()
142 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); in matroxfb_PLL_calcclock()
144 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); in matroxfb_PLL_calcclock()
145 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); in matroxfb_PLL_calcclock()
146 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); in matroxfb_PLL_calcclock()
147 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); in matroxfb_PLL_calcclock()
148 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); in matroxfb_PLL_calcclock()
151 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_calcclock()
[all …]
Dg450_pll.h7 unsigned int pll);
10 unsigned int pll);
Dmatroxfb_misc.h7 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int f…
14 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
Dmatroxfb_DAC1064.c180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
588 minfo->features.pll.vco_freq_min = 62000; in MGA1064_ramdac_init()
589 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
590 minfo->features.pll.feed_div_min = 100; in MGA1064_ramdac_init()
591 minfo->features.pll.feed_div_max = 127; in MGA1064_ramdac_init()
592 minfo->features.pll.in_div_min = 1; in MGA1064_ramdac_init()
593 minfo->features.pll.in_div_max = 31; in MGA1064_ramdac_init()
594 minfo->features.pll.post_shift_max = 3; in MGA1064_ramdac_init()
726 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); in g450_mclk_init()
736 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); in g450_mclk_init()
[all …]
Dmatroxfb_Ti3026.c545 minfo->features.pll.vco_freq_min = 110000; in ti3026_ramdac_init()
546 minfo->features.pll.ref_freq = 114545; in ti3026_ramdac_init()
547 minfo->features.pll.feed_div_min = 2; in ti3026_ramdac_init()
548 minfo->features.pll.feed_div_max = 24; in ti3026_ramdac_init()
549 minfo->features.pll.in_div_min = 2; in ti3026_ramdac_init()
550 minfo->features.pll.in_div_max = 63; in ti3026_ramdac_init()
551 minfo->features.pll.post_shift_max = 3; in ti3026_ramdac_init()
Dmatroxfb_maven.c223 static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, in matroxfb_PLL_mavenclock() argument
230 unsigned int fmin = pll->vco_freq_min / ctl->den; in matroxfb_PLL_mavenclock()
240 fmax = pll->vco_freq_max / ctl->den; in matroxfb_PLL_mavenclock()
244 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_mavenclock()
255 for (m = pll->in_div_min; m <= pll->in_div_max; m++) { in matroxfb_PLL_mavenclock()
261 if (n < pll->feed_div_min) in matroxfb_PLL_mavenclock()
263 if (n > pll->feed_div_max) in matroxfb_PLL_mavenclock()
/linux-4.1.27/drivers/media/pci/bt8xx/
Dbttv-cards.c99 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
121 module_param_array(pll, int, NULL, 0444);
134 MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)");
401 .pll = PLL_28,
465 .pll = PLL_28,
477 .pll = PLL_28,
490 .pll = PLL_28,
528 .pll = PLL_28,
543 .pll = PLL_28,
571 .pll = PLL_28,
[all …]
/linux-4.1.27/arch/m68k/q40/
Dconfig.c47 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
48 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
302 static int q40_get_rtc_pll(struct rtc_pll_info *pll) in q40_get_rtc_pll() argument
306 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()
308 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()
309 pll->pll_max = 31; in q40_get_rtc_pll()
310 pll->pll_min = -31; in q40_get_rtc_pll()
311 pll->pll_posmult = 512; in q40_get_rtc_pll()
312 pll->pll_negmult = 256; in q40_get_rtc_pll()
313 pll->pll_clock = 125829120; in q40_get_rtc_pll()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
17 - reg - pll control0 and pll multipler registers
19 post-divider registers are applicable only for main pll clock
26 compatible = "ti,keystone,main-pll-clock";
35 compatible = "ti,keystone,pll-clock";
37 clock-output-names = "pa-pll-clk";
44 - compatible : shall be "ti,keystone,pll-mux-clock"
46 - reg - pll mux register
56 compatible = "ti,keystone,pll-mux-clock";
66 - compatible : shall be "ti,keystone,pll-divider-clock"
[all …]
Dqoriq-clock.txt58 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
59 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
66 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
67 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
70 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
71 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
104 compatible = "fsl,qoriq-core-pll-1.0";
112 compatible = "fsl,qoriq-core-pll-1.0";
135 platform-pll: platform-pll@c00 {
138 compatible = "fsl,qoriq-platform-pll-1.0";
[all …]
Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
Dti-keystone-pllctrl.txt1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@0x02310000 {
Dsilabs,si5351.txt26 - silabs,pll-source: pair of (number, source) for each pll. Allows
27 to overwrite clock source of pll A (number=0) or B (number=1).
45 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
47 - silabs,pll-master: boolean, multisynth can change pll frequency.
78 silabs,pll-source = <0 0>, <1 0>;
93 silabs,pll-master;
109 pll-master;
Dclock-bindings.txt104 pll: pll@4c000 {
105 compatible = "vendor,some-pll-interface"
110 clock-output-names = "pll", "pll-switched";
120 clocks = <&osc 0>, <&pll 1>;
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
152 clocks = <&osc 0>, <&pll 1>;
155 assigned-clocks = <&clkcon 0>, <&pll 2>;
156 assigned-clock-parents = <&pll 2>;
160 In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
[all …]
Dat91-clock.txt49 "atmel,at91rm9200-clk-pll" or
50 "atmel,at91sam9g45-clk-pll" or
52 "atmel,sama5d3-clk-pll":
53 at91 pll clocks
280 Required properties for pll clocks:
285 - reg : pll id.
291 - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
299 - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
300 depending on #atmel,pll-output-range-cells
305 compatible = "atmel,at91sam9g45-clk-pll";
[all …]
Dcalxeda.txt9 "calxeda,hb-pll-clock" - for a PLL clock
16 either an oscillator or a pll output.
Drenesas,rz-cpg-clocks.txt15 - clock-output-names: The names of the clocks. Supported clocks are "pll",
28 clock-output-names = "pll", "i", "g";
Dmoxa,moxart-clock.txt14 - compatible : Must be "moxa,moxart-pll-clock"
38 compatible = "moxa,moxart-pll-clock";
Daltr_socfpga.txt9 "altr,socfpga-pll-clock" - for a PLL clock
17 either an oscillator or a pll output.
Drockchip,rk3288-cru.txt18 If missing pll rates are not changable, due to the missing pll lock status.
Drockchip,rk3188-cru.txt19 If missing pll rates are not changable, due to the missing pll lock status.
Dmvebu-corediv-clock.txt21 clocks = <&pll>;
Dimx23-clock.txt15 pll 1
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Dpcm512x.txt20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
50 pll-in = <3>;
51 pll-out = <6>;
Dadi,adau1701.txt14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
31 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
/linux-4.1.27/drivers/clk/st/
Dclkgen-fsyn.c427 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); in quadfs_pll_enable() local
430 if (pll->lock) in quadfs_pll_enable()
431 spin_lock_irqsave(pll->lock, flags); in quadfs_pll_enable()
436 if (pll->data->reset_present) in quadfs_pll_enable()
437 CLKGEN_WRITE(pll, nreset, 1); in quadfs_pll_enable()
442 if (pll->data->bwfilter_present) in quadfs_pll_enable()
443 CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF); in quadfs_pll_enable()
446 CLKGEN_WRITE(pll, ndiv, pll->ndiv); in quadfs_pll_enable()
451 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); in quadfs_pll_enable()
453 if (pll->lock) in quadfs_pll_enable()
[all …]
Dclkgen.h41 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ argument
42 &pll->data->field)
44 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \ argument
45 &pll->data->field, val)
Dclkgen-pll.c260 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
261 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
268 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
269 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
276 struct clkgen_pll *pll = to_clkgen_pll(hw); in recalc_stm_pll800c65() local
284 pdiv = CLKGEN_READ(pll, pdiv); in recalc_stm_pll800c65()
285 mdiv = CLKGEN_READ(pll, mdiv); in recalc_stm_pll800c65()
286 ndiv = CLKGEN_READ(pll, ndiv); in recalc_stm_pll800c65()
303 struct clkgen_pll *pll = to_clkgen_pll(hw); in recalc_stm_pll1600c65() local
310 mdiv = CLKGEN_READ(pll, mdiv); in recalc_stm_pll1600c65()
[all …]
DMakefile1 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_display.c928 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo() argument
936 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
946 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
947 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
949 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
955 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
956 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
958 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
960 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
961 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
[all …]
Datombios_crtc.c1064 struct radeon_pll *pll; in atombios_crtc_set_pll() local
1075 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1078 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1083 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1088 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1089 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1090 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1097 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
[all …]
Dradeon_legacy_crtc.c751 struct radeon_pll *pll; in radeon_set_pll() local
774 pll = &rdev->clock.p2pll; in radeon_set_pll()
776 pll = &rdev->clock.p1pll; in radeon_set_pll()
778 pll->flags = RADEON_PLL_LEGACY; in radeon_set_pll()
781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in radeon_set_pll()
783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in radeon_set_pll()
795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in radeon_set_pll()
810 pll->flags |= RADEON_PLL_USE_REF_DIV; in radeon_set_pll()
818 radeon_compute_pll_legacy(pll, mode->clock, in radeon_set_pll()
849 pll_gain = radeon_compute_pll_gain(pll->reference_freq, in radeon_set_pll()
Dradeon_legacy_tv.c242 struct radeon_pll *pll; in radeon_legacy_tv_get_std_mode() local
246 pll = &rdev->clock.p2pll; in radeon_legacy_tv_get_std_mode()
248 pll = &rdev->clock.p1pll; in radeon_legacy_tv_get_std_mode()
251 *pll_ref_freq = pll->reference_freq; in radeon_legacy_tv_get_std_mode()
256 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
261 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode()
434 struct radeon_pll *pll; in radeon_legacy_tv_init_restarts() local
438 pll = &rdev->clock.p2pll; in radeon_legacy_tv_init_restarts()
440 pll = &rdev->clock.p1pll; in radeon_legacy_tv_init_restarts()
/linux-4.1.27/arch/c6x/platforms/
Dplldata.c172 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks() local
173 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
175 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
210 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks() local
211 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
213 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
260 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks() local
261 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
264 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
309 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks() local
[all …]
Dpll.c204 static u32 pll_read(struct pll_data *pll, int reg) in pll_read() argument
206 return soc_readl(pll->base + reg); in pll_read()
212 struct pll_data *pll; in clk_sysclk_recalc() local
224 pll = clk->parent->pll_data; in clk_sysclk_recalc()
228 rate = pll->input_rate; in clk_sysclk_recalc()
243 v = pll_read(pll, clk->div); in clk_sysclk_recalc()
273 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc() local
279 ctrl = pll_read(pll, PLLCTL); in clk_pllclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; in clk_pllclk_recalc()
287 if (pll->flags & PLL_HAS_MUL) { in clk_pllclk_recalc()
[all …]
DMakefile7 obj-y = platform.o cache.o megamod-pic.o pll.o plldata.o timer64.o
/linux-4.1.27/drivers/video/fbdev/via/
Dvia_clock.h63 struct via_pll_config pll) in get_pll_internal_frequency() argument
65 return ref_freq / pll.divisor * pll.multiplier; in get_pll_internal_frequency()
69 struct via_pll_config pll) in get_pll_output_frequency() argument
71 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; in get_pll_output_frequency()
Dvia_clock.c36 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument
38 return (pll.multiplier << 8) in cle266_encode_pll()
39 | (pll.rshift << 6) in cle266_encode_pll()
40 | pll.divisor; in cle266_encode_pll()
43 static inline u32 k800_encode_pll(struct via_pll_config pll) in k800_encode_pll() argument
45 return ((pll.divisor - 2) << 16) in k800_encode_pll()
46 | (pll.rshift << 10) in k800_encode_pll()
47 | (pll.multiplier - 2); in k800_encode_pll()
50 static inline u32 vx855_encode_pll(struct via_pll_config pll) in vx855_encode_pll() argument
52 return (pll.divisor << 16) in vx855_encode_pll()
[all …]
/linux-4.1.27/drivers/clk/
Dclk-nomadik.c167 struct clk_pll *pll = to_pll(hw); in pll_clk_enable() local
172 if (pll->id == 1) { in pll_clk_enable()
177 } else if (pll->id == 2) { in pll_clk_enable()
187 struct clk_pll *pll = to_pll(hw); in pll_clk_disable() local
192 if (pll->id == 1) { in pll_clk_disable()
197 } else if (pll->id == 2) { in pll_clk_disable()
206 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled() local
210 if (pll->id == 1) { in pll_clk_is_enabled()
213 } else if (pll->id == 2) { in pll_clk_is_enabled()
222 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate() local
[all …]
Dclk-cdce706.c26 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) argument
27 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) argument
28 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) argument
39 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) argument
47 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) argument
88 struct cdce706_hw_data pll[3]; member
529 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { in cdce706_register_plls()
541 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); in cdce706_register_plls()
542 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << in cdce706_register_plls()
544 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); in cdce706_register_plls()
[all …]
Dclk-ls1x.c35 u32 pll, rate; in ls1x_pll_recalc_rate() local
37 pll = __raw_readl(LS1X_CLK_PLL_FREQ); in ls1x_pll_recalc_rate()
38 rate = 12 + (pll & 0x3f) + (((pll >> 8) & 0x3ff) >> 10); in ls1x_pll_recalc_rate()
Dclk-vt8500.c542 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate() local
549 switch (pll->type) { in vtwm_pll_set_rate()
571 spin_lock_irqsave(pll->lock, flags); in vtwm_pll_set_rate()
574 writel(pll_val, pll->reg); in vtwm_pll_set_rate()
577 spin_unlock_irqrestore(pll->lock, flags); in vtwm_pll_set_rate()
585 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate() local
589 switch (pll->type) { in vtwm_pll_round_rate()
616 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate() local
617 u32 pll_val = readl(pll->reg); in vtwm_pll_recalc_rate()
620 switch (pll->type) { in vtwm_pll_recalc_rate()
Dclk-xgene.c90 u32 pll; in xgene_clk_pll_recalc_rate() local
95 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
103 fvco = parent_rate * (N_DIV_RD(pll) + 4); in xgene_clk_pll_recalc_rate()
110 nref = CLKR_RD(pll) + 1; in xgene_clk_pll_recalc_rate()
111 nout = CLKOD_RD(pll) + 1; in xgene_clk_pll_recalc_rate()
112 nfb = CLKF_RD(pll); in xgene_clk_pll_recalc_rate()
Dclk-si5351.c66 struct si5351_hw_data pll[2]; member
1452 drvdata->pll[0].num = 0; in si5351_i2c_probe()
1453 drvdata->pll[0].drvdata = drvdata; in si5351_i2c_probe()
1454 drvdata->pll[0].hw.init = &init; in si5351_i2c_probe()
1461 clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw); in si5351_i2c_probe()
1469 drvdata->pll[1].num = 1; in si5351_i2c_probe()
1470 drvdata->pll[1].drvdata = drvdata; in si5351_i2c_probe()
1471 drvdata->pll[1].hw.init = &init; in si5351_i2c_probe()
1486 clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw); in si5351_i2c_probe()
/linux-4.1.27/drivers/char/
Dgenrtc.c270 struct rtc_pll_info pll; in gen_rtc_ioctl() local
276 if (get_rtc_pll(&pll)) in gen_rtc_ioctl()
279 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0; in gen_rtc_ioctl()
284 if (copy_from_user(&pll, argp, sizeof(pll))) in gen_rtc_ioctl()
286 return set_rtc_pll(&pll); in gen_rtc_ioctl()
394 struct rtc_pll_info pll; in gen_rtc_proc_show() local
442 if (!get_rtc_pll(&pll)) in gen_rtc_proc_show()
450 pll.pll_value, in gen_rtc_proc_show()
451 pll.pll_max, in gen_rtc_proc_show()
452 pll.pll_min, in gen_rtc_proc_show()
[all …]
/linux-4.1.27/drivers/cpufreq/
Dcpufreq-nforce2.c67 static int nforce2_calc_fsb(int pll) in nforce2_calc_fsb() argument
71 mul = (pll >> 8) & 0xff; in nforce2_calc_fsb()
72 div = pll & 0xff; in nforce2_calc_fsb()
116 static void nforce2_write_pll(int pll) in nforce2_write_pll() argument
125 pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll); in nforce2_write_pll()
174 int pll = 0; in nforce2_set_fsb() local
190 pll = nforce2_calc_pll(tfsb); in nforce2_set_fsb()
192 if (pll < 0) in nforce2_set_fsb()
195 nforce2_write_pll(pll); in nforce2_set_fsb()
214 pll = nforce2_calc_pll(tfsb); in nforce2_set_fsb()
[all …]
Ds3c24xx-cpufreq.c72 cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); in s3c_cpufreq_getcur()
73 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
83 unsigned long pll = cfg->pll.frequency; in s3c_cpufreq_calc() local
85 cfg->freq.fclk = pll; in s3c_cpufreq_calc()
86 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
87 cfg->freq.pclk = pll / cfg->divs.p_divisor; in s3c_cpufreq_calc()
105 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, in s3c_cpufreq_show()
155 struct cpufreq_frequency_table *pll) in s3c_cpufreq_settarget() argument
167 cpu_new.pll = pll ? *pll : cpu_cur.pll; in s3c_cpufreq_settarget()
169 if (pll) in s3c_cpufreq_settarget()
[all …]
Dcris-etraxfs-cpufreq.c27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
40 clk_ctrl.pll = 1; in cris_freq_target()
42 clk_ctrl.pll = 0; in cris_freq_target()
Dcris-artpec3-cpufreq.c27 return clk_ctrl.pll ? 200000 : 6000; in cris_freq_get_cpu_frequency()
40 clk_ctrl.pll = 1; in cris_freq_target()
42 clk_ctrl.pll = 0; in cris_freq_target()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgt215.c106 read_pll(struct gt215_clk_priv *priv, int clk, u32 pll) in read_pll() argument
108 u32 ctrl = nv_rd32(priv, pll + 0); in read_pll()
113 u32 coef = nv_rd32(priv, pll + 4); in read_pll()
121 if ((pll & 0x00ff00) == 0x00e800) in read_pll()
226 gt215_pll_info(struct nvkm_clk *clock, int clk, u32 pll, u32 khz, in gt215_pll_info() argument
235 info->pll = 0; in gt215_pll_info()
241 if (!pll || (diff >= -2000 && diff < 3000)) { in gt215_pll_info()
246 ret = nvbios_pll_parse(bios, pll, &limits); in gt215_pll_info()
256 info->pll = (P << 16) | (N << 8) | M; in gt215_pll_info()
266 int clk, u32 pll, int idx) in calc_clk() argument
[all …]
Dnv40.c134 struct nvbios_pll pll; in nv40_clk_calc_pll() local
137 ret = nvbios_pll_parse(bios, reg, &pll); in nv40_clk_calc_pll()
141 if (clk < pll.vco1.max_freq) in nv40_clk_calc_pll()
142 pll.vco2.max_freq = 0; in nv40_clk_calc_pll()
144 ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
Dmcp77.c165 struct nvbios_pll pll; in calc_pll() local
169 ret = nvbios_pll_parse(bios, reg, &pll); in calc_pll()
173 pll.vco2.max_freq = 0; in calc_pll()
174 pll.refclk = clk->read(clk, nv_clk_src_href); in calc_pll()
175 if (!pll.refclk) in calc_pll()
178 return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); in calc_pll()
Dgk104.c59 read_pll(struct gk104_clk_priv *priv, u32 pll) in read_pll() argument
61 u32 ctrl = nv_rd32(priv, pll + 0x00); in read_pll()
62 u32 coef = nv_rd32(priv, pll + 0x04); in read_pll()
72 switch (pll) { in read_pll()
84 fN = nv_rd32(priv, pll + 0x10) >> 16; in read_pll()
90 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
Dnv50.c324 struct nvbios_pll pll; in calc_pll() local
327 ret = nvbios_pll_parse(bios, reg, &pll); in calc_pll()
331 pll.vco2.max_freq = 0; in calc_pll()
332 pll.refclk = read_pll_ref(priv, reg); in calc_pll()
333 if (!pll.refclk) in calc_pll()
336 return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); in calc_pll()
Dgf100.c59 read_pll(struct gf100_clk_priv *priv, u32 pll) in read_pll() argument
62 u32 ctrl = nv_rd32(priv, pll + 0x00); in read_pll()
63 u32 coef = nv_rd32(priv, pll + 0x04); in read_pll()
72 switch (pll) { in read_pll()
88 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
Dgt215.h7 u32 pll; member
/linux-4.1.27/drivers/video/fbdev/nvidia/
Dnv_hw.c144 unsigned int pll, N, M, MB, NB, P; in nvGetClocks() local
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
148 P = (pll >> 16) & 0x07; in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
150 M = pll & 0xFF; in nvGetClocks()
151 N = (pll >> 8) & 0xFF; in nvGetClocks()
157 MB = (pll >> 16) & 0xFF; in nvGetClocks()
158 NB = (pll >> 24) & 0xFF; in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
163 P = (pll >> 16) & 0x07; in nvGetClocks()
[all …]
/linux-4.1.27/sound/soc/codecs/
Dak4671.c477 u8 pll; in ak4671_set_dai_sysclk() local
479 pll = snd_soc_read(codec, AK4671_PLL_MODE_SELECT0); in ak4671_set_dai_sysclk()
480 pll &= ~AK4671_PLL; in ak4671_set_dai_sysclk()
484 pll |= AK4671_PLL_11_2896MHZ; in ak4671_set_dai_sysclk()
487 pll |= AK4671_PLL_12MHZ; in ak4671_set_dai_sysclk()
490 pll |= AK4671_PLL_12_288MHZ; in ak4671_set_dai_sysclk()
493 pll |= AK4671_PLL_13MHZ; in ak4671_set_dai_sysclk()
496 pll |= AK4671_PLL_13_5MHZ; in ak4671_set_dai_sysclk()
499 pll |= AK4671_PLL_19_2MHZ; in ak4671_set_dai_sysclk()
502 pll |= AK4671_PLL_24MHZ; in ak4671_set_dai_sysclk()
[all …]
Dadav80x.c47 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
49 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
57 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
60 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
62 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
63 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
64 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
66 #define ADAV80X_PLL_CTRL2_SEL(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x02) argument
67 #define ADAV80X_PLL_CTRL2_DOUB(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x01) argument
[all …]
Dwm8955.c147 int Fref, int Fout, struct pll_factors *pll) in wm8995_pll_factors() argument
160 pll->outdiv = 1; in wm8995_pll_factors()
163 pll->outdiv = 0; in wm8995_pll_factors()
173 pll->n = Ndiv; in wm8995_pll_factors()
188 pll->k = K / 10; in wm8995_pll_factors()
190 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); in wm8995_pll_factors()
252 struct pll_factors pll; in wm8955_configure_clocking() local
286 clock_cfgs[sr].mclk, &pll); in wm8955_configure_clocking()
296 (pll.n << WM8955_N_SHIFT) | in wm8955_configure_clocking()
297 pll.k >> 18); in wm8955_configure_clocking()
[all …]
Dak4642.c344 u8 pll; in ak4642_dai_set_sysclk() local
349 pll = PLL2; in ak4642_dai_set_sysclk()
352 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
355 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
361 pll = PLL3 | PLL2; in ak4642_dai_set_sysclk()
364 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
[all …]
/linux-4.1.27/drivers/staging/sm750fb/
Dddk750_mode.c78 static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll) in programModeRegisters() argument
83 if(pll->clockType == SECONDARY_PLL) in programModeRegisters()
86 POKE32(CRT_PLL_CTRL,formatPllReg(pll)); in programModeRegisters()
123 else if(pll->clockType == PRIMARY_PLL) in programModeRegisters()
126 POKE32(PANEL_PLL_CTRL,formatPllReg(pll)); in programModeRegisters()
190 pll_value_t pll; in ddk750_setModeTiming() local
192 pll.inputFreq = DEFAULT_INPUT_CLOCK; in ddk750_setModeTiming()
193 pll.clockType = clock; in ddk750_setModeTiming()
195 uiActualPixelClk = calcPllValue(parm->pixel_clock,&pll); in ddk750_setModeTiming()
201 programModeRegisters(parm,&pll); in ddk750_setModeTiming()
Dddk750_chip.c88 pll_value_t pll; in getChipClock() local
94 return getPllValue(MXCLK_PLL, &pll); in getChipClock()
105 pll_value_t pll; in setChipClock() local
117 pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in setChipClock()
118 pll.clockType = MXCLK_PLL; in setChipClock()
125 ulActualMxClk = calcPllValue(frequency, &pll); in setChipClock()
128 POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll)); in setChipClock()
408 unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) in calcPllValue() argument
449 input = pll->inputFreq / 1000; in calcPllValue()
453 if (pll->clockType != MXCLK_PLL) { in calcPllValue()
[all …]
Dddk750_chip.h74 unsigned int calcPllValue(unsigned int request,pll_value_t *pll);
/linux-4.1.27/arch/avr32/boards/atstk1000/
Datstk1003.c84 struct clk *pll; in atstk1003_setup_extdac() local
89 pll = clk_get(NULL, "pll0"); in atstk1003_setup_extdac()
90 if (IS_ERR(pll)) in atstk1003_setup_extdac()
93 if (clk_set_parent(gclk, pll)) { in atstk1003_setup_extdac()
102 clk_put(pll); in atstk1003_setup_extdac()
Datstk1004.c89 struct clk *pll; in atstk1004_setup_extdac() local
94 pll = clk_get(NULL, "pll0"); in atstk1004_setup_extdac()
95 if (IS_ERR(pll)) in atstk1004_setup_extdac()
98 if (clk_set_parent(gclk, pll)) { in atstk1004_setup_extdac()
107 clk_put(pll); in atstk1004_setup_extdac()
Datstk1002.c217 struct clk *pll; in atstk1002_setup_extdac() local
222 pll = clk_get(NULL, "pll0"); in atstk1002_setup_extdac()
223 if (IS_ERR(pll)) in atstk1002_setup_extdac()
226 if (clk_set_parent(gclk, pll)) { in atstk1002_setup_extdac()
235 clk_put(pll); in atstk1002_setup_extdac()
/linux-4.1.27/drivers/clk/keystone/
Dpll.c83 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc() local
84 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
131 struct clk_pll *pll; in clk_register_pll() local
134 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in clk_register_pll()
135 if (!pll) in clk_register_pll()
144 pll->pll_data = pll_data; in clk_register_pll()
145 pll->hw.init = &init; in clk_register_pll()
147 clk = clk_register(NULL, &pll->hw); in clk_register_pll()
153 kfree(pll); in clk_register_pll()
DMakefile1 obj-y += pll.o gate.o
/linux-4.1.27/arch/m68k/include/asm/
Drtc.h63 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
66 return mach_get_rtc_pll(pll); in get_rtc_pll()
70 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
73 return mach_set_rtc_pll(pll); in set_rtc_pll()
/linux-4.1.27/arch/c6x/boot/dts/
Dtms320c6457.dtsi61 compatible = "ti,c6457-pll", "ti,c64x+pll";
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
Dtms320c6474.dtsi82 compatible = "ti,c6474-pll", "ti,c64x+pll";
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
Dtms320c6455.dtsi71 compatible = "ti,c6455-pll", "ti,c64x+pll";
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
Dtms320c6472.dtsi105 compatible = "ti,c6472-pll", "ti,c64x+pll";
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
Dtms320c6678.dtsi127 compatible = "ti,c6678-pll", "ti,c64x+pll";
129 ti,c64x+pll-bypass-delay = <200>;
130 ti,c64x+pll-reset-delay = <12000>;
131 ti,c64x+pll-lock-delay = <80000>;
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,clkgen-pll.txt1 Binding for a ST pll clock driver.
27 "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
28 "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
41 clk_s_a0_pll: clk-s-a0-pll {
Dst,clkgen.txt4 A Clockgen node can contain pll, diviser or multiplexer nodes.
48 [4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
64 clk_s_a0_pll: clk-s-a0-pll {
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_ddi.c830 u32 val, pll; in hsw_ddi_clock_get() local
850 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; in hsw_ddi_clock_get()
851 if (pll == SPLL_PLL_FREQ_810MHz) in hsw_ddi_clock_get()
853 else if (pll == SPLL_PLL_FREQ_1350MHz) in hsw_ddi_clock_get()
855 else if (pll == SPLL_PLL_FREQ_2700MHz) in hsw_ddi_clock_get()
964 struct intel_shared_dpll *pll; in hsw_ddi_pll_select() local
976 pll = intel_get_shared_dpll(intel_crtc, crtc_state); in hsw_ddi_pll_select()
977 if (pll == NULL) { in hsw_ddi_pll_select()
983 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); in hsw_ddi_pll_select()
1150 struct intel_shared_dpll *pll; in skl_ddi_pll_select() local
[all …]
Dintel_display.c1139 struct intel_shared_dpll *pll, in assert_shared_dpll() argument
1145 if (WARN (!pll, in assert_shared_dpll()
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1152 pll->name, state_string(state), state_string(cur_state)); in assert_shared_dpll()
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); in intel_prepare_shared_dpll() local
1857 if (WARN_ON(pll == NULL)) in intel_prepare_shared_dpll()
1860 WARN_ON(!pll->config.crtc_mask); in intel_prepare_shared_dpll()
1861 if (pll->active == 0) { in intel_prepare_shared_dpll()
1862 DRM_DEBUG_DRIVER("setting up %s\n", pll->name); in intel_prepare_shared_dpll()
1863 WARN_ON(pll->on); in intel_prepare_shared_dpll()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dti,omap5-dss.txt60 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
61 - reg-names: "proto", "phy", "pll"
65 - clocks: handles to fclk and pll clock
82 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
84 - reg-names: "wp", "pll", "phy", "core"
88 - clocks: handles to fclk and pll clock
Dti,dra7-dss.txt25 - clocks: handle to video1 pll clock and video2 pll clock
55 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
57 - reg-names: "wp", "pll", "phy", "core"
61 - clocks: handles to fclk and pll clock
Dti,omap4-dss.txt79 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
80 - reg-names: "proto", "phy", "pll"
84 - clocks: handles to fclk and pll clock
101 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
103 - reg-names: "wp", "pll", "phy", "core"
107 - clocks: handles to fclk and pll clock
Dti,omap3-dss.txt73 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
74 - reg-names: "proto", "phy", "pll"
78 - clocks: handles to fclk and pll clock
Dexynos_dsim.txt19 - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
59 samsung,pll-clock-frequency = <24000000>;
/linux-4.1.27/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen2.dtsi50 compatible = "fsl,qoriq-core-pll-2.0";
57 compatible = "fsl,qoriq-core-pll-2.0";
61 platform_pll: platform-pll@c00 {
64 compatible = "fsl,qoriq-platform-pll-2.0";
66 clock-output-names = "platform-pll", "platform-pll-div2";
Dqoriq-clockgen1.dtsi51 compatible = "fsl,qoriq-core-pll-1.0";
58 compatible = "fsl,qoriq-core-pll-1.0";
78 platform_pll: platform-pll@c00 {
81 compatible = "fsl,qoriq-platform-pll-1.0";
83 clock-output-names = "platform-pll", "platform-pll-div2";
/linux-4.1.27/arch/arm/boot/dts/
Dk2e-clocks.dtsi14 compatible = "ti,keystone,main-pll-clock";
22 compatible = "ti,keystone,pll-clock";
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";
Dwm8850.dtsi86 compatible = "wm,wm8850-pll-clock";
93 compatible = "wm,wm8850-pll-clock";
100 compatible = "wm,wm8850-pll-clock";
107 compatible = "wm,wm8850-pll-clock";
114 compatible = "wm,wm8850-pll-clock";
121 compatible = "wm,wm8850-pll-clock";
128 compatible = "wm,wm8850-pll-clock";
Dwm8650.dtsi83 compatible = "wm,wm8650-pll-clock";
90 compatible = "wm,wm8650-pll-clock";
97 compatible = "wm,wm8650-pll-clock";
104 compatible = "wm,wm8650-pll-clock";
111 compatible = "wm,wm8650-pll-clock";
Ddove-cubox.dts93 silabs,pll-source = <0 0>, <1 0>;
100 silabs,pll-master;
108 silabs,pll-master;
Dk2l-clocks.dtsi14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
23 compatible = "ti,keystone,main-pll-clock";
31 compatible = "ti,keystone,pll-clock";
40 compatible = "ti,keystone,pll-clock";
42 clock-output-names = "ddr-3a-pll-clk";
Dat91sam9g20.dtsi45 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
58 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
Dk2hk-clocks.dtsi14 compatible = "ti,keystone,pll-clock";
16 clock-output-names = "arm-pll-clk";
23 compatible = "ti,keystone,main-pll-clock";
31 compatible = "ti,keystone,pll-clock";
40 compatible = "ti,keystone,pll-clock";
42 clock-output-names = "ddr-3a-pll-clk";
49 compatible = "ti,keystone,pll-clock";
51 clock-output-names = "ddr-3b-pll-clk";
Dwm8750.dtsi89 compatible = "wm,wm8750-pll-clock";
96 compatible = "wm,wm8750-pll-clock";
103 compatible = "wm,wm8750-pll-clock";
110 compatible = "wm,wm8750-pll-clock";
117 compatible = "wm,wm8750-pll-clock";
Dwm8505.dtsi86 compatible = "via,vt8500-pll-clock";
93 compatible = "via,vt8500-pll-clock";
100 compatible = "via,vt8500-pll-clock";
107 compatible = "via,vt8500-pll-clock";
Dstih416-clock.dtsi33 clk_s_a0_pll: clk-s-a0-pll {
91 clk_s_a1_pll: clk-s-a1-pll {
503 clockgen_a9_pll: clockgen-a9-pll {
508 clock-output-names = "clockgen-a9-pll-odf";
615 "clk-s-hdmi-reject-pll",
731 clockgen_ddr_pll: clockgen-ddr-pll {
747 clockgen_gpu_pll: clockgen-gpu-pll {
749 compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
752 clock-output-names = "clockgen-gpu-pll";
Dstih407-clock.dtsi43 clockgen_a9_pll: clockgen-a9-pll {
49 clock-output-names = "clockgen-a9-pll-odf";
97 clk_s_a0_pll: clk-s-a0-pll {
103 clock-output-names = "clk-s-a0-pll-ofd-0";
Decx-common.dtsi157 compatible = "calxeda,hb-pll-clock";
164 compatible = "calxeda,hb-pll-clock";
185 compatible = "calxeda,hb-pll-clock";
Dstih410-clock.dtsi45 clockgen_a9_pll: clockgen-a9-pll {
51 clock-output-names = "clockgen-a9-pll-odf";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
Dstih418-clock.dtsi45 clockgen_a9_pll: clockgen-a9-pll {
51 clock-output-names = "clockgen-a9-pll-odf";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
Dat91sam9261.dtsi593 compatible = "atmel,at91rm9200-clk-pll";
599 #atmel,pll-clk-output-range-cells = <4>;
600 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
605 compatible = "atmel,at91rm9200-clk-pll";
611 #atmel,pll-clk-output-range-cells = <4>;
612 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
Dls1021a.dtsi159 cga_pll1: pll@800 {
160 compatible = "fsl,qoriq-core-pll-2.0";
168 platform_clk: pll@c00 {
169 compatible = "fsl,qoriq-core-pll-2.0";
/linux-4.1.27/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
17 access pll controller registers and the offset to use
40 pllctrl: pll-controller@02310000 {
52 ti,syscon-pll = <&pllctrl 0xe4>;
63 ti,syscon-pll = <&pllctrl 0xe4>;
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c39 struct nvbios_pll pll; in nv40_ram_calc() local
43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
49 ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq, in nv40_ram_calc()
55 ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; in nv40_ram_calc()
/linux-4.1.27/arch/mips/ar7/
Dclock.c62 u32 pll; member
178 u32 pll = readl(&clock->pll); in tnetd7300_get_clock() local
182 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; in tnetd7300_get_clock()
202 if ((pll & PLL_MODE_MASK) == 0) in tnetd7300_get_clock()
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()
243 writel(4, &clock->pll); in tnetd7300_set_clock()
244 while (readl(&clock->pll) & PLL_STATUS) in tnetd7300_set_clock()
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); in tnetd7300_set_clock()
/linux-4.1.27/drivers/media/radio/
Dtef6862.c108 u16 pll; in tef6862_s_frequency() local
116 pll = 1964 + ((freq - TEF6862_LO_FREQ) * 20) / FREQ_MUL; in tef6862_s_frequency()
118 i2cmsg[1] = (pll >> 8) & 0xff; in tef6862_s_frequency()
119 i2cmsg[2] = pll & 0xff; in tef6862_s_frequency()
/linux-4.1.27/arch/powerpc/include/asm/
Drtc.h68 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
72 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
/linux-4.1.27/drivers/video/fbdev/core/
Dsvgalib.c381 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) in svga_compute_pll() argument
388 ar = pll->r_max; in svga_compute_pll()
398 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { in svga_compute_pll()
404 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) in svga_compute_pll()
412 am = pll->m_min; in svga_compute_pll()
413 an = pll->n_min; in svga_compute_pll()
415 while ((am <= pll->m_max) && (an <= pll->n_max)) { in svga_compute_pll()
416 f_current = (pll->f_base * am) / an; in svga_compute_pll()
432 f_current = (pll->f_base * *m) / *n; in svga_compute_pll()
/linux-4.1.27/drivers/video/fbdev/intelfb/
Dintelfbhw.c667 struct pll_min_max *pll = &plls[index]; in calc_vclock() local
672 vco = pll->ref_clk * m / n; in calc_vclock()
883 struct pll_min_max *pll = &plls[index]; in splitm() local
886 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { in splitm()
887 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { in splitm()
904 struct pll_min_max *pll = &plls[index]; in splitp() local
921 if (p % 4 == 0 && p1 < pll->min_p1) { in splitp()
925 if (p1 < pll->min_p1 || p1 > pll->max_p1 || in splitp()
943 struct pll_min_max *pll = &plls[index]; in calc_pll_params() local
951 div_max = pll->max_vco / clock; in calc_pll_params()
[all …]
/linux-4.1.27/drivers/media/i2c/smiapp/
Dsmiapp-core.c200 struct smiapp_pll *pll = &sensor->pll; in smiapp_pll_configure() local
204 sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div); in smiapp_pll_configure()
209 sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div); in smiapp_pll_configure()
214 sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div); in smiapp_pll_configure()
219 sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier); in smiapp_pll_configure()
226 DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256)); in smiapp_pll_configure()
231 sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div); in smiapp_pll_configure()
236 sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div); in smiapp_pll_configure()
240 struct smiapp_pll *pll) in smiapp_pll_try() argument
275 return smiapp_pll_calculate(&client->dev, &lim, pll); in smiapp_pll_try()
[all …]
/linux-4.1.27/drivers/media/dvb-frontends/
Ddib8000.c691 const struct dibx000_bandwidth_config *pll = state->cfg.pll; in dib8000_reset_pll() local
696 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
698 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | in dib8000_reset_pll()
699 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | in dib8000_reset_pll()
700 (1 << 3) | (pll->pll_range << 1) | in dib8000_reset_pll()
701 (pll->pll_reset << 0); in dib8000_reset_pll()
704 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); in dib8000_reset_pll()
710 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
713 (pll->modulo << 8) | in dib8000_reset_pll()
714 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
[all …]
Dmb86a20s.c1766 u64 pll; in mb86a20s_initfe() local
1813 pll = (((u64)1) << 34) * state->if_freq; in mb86a20s_initfe()
1814 do_div(pll, 63 * fclk); in mb86a20s_initfe()
1815 pll = (1 << 25) - pll; in mb86a20s_initfe()
1819 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff); in mb86a20s_initfe()
1822 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff); in mb86a20s_initfe()
1825 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff); in mb86a20s_initfe()
1829 __func__, fclk, state->if_freq, (long long)pll); in mb86a20s_initfe()
1832 pll = state->if_freq * 1677721600L; in mb86a20s_initfe()
1833 do_div(pll, 1628571429L); in mb86a20s_initfe()
[all …]
Ddib8000.h14 struct dibx000_bandwidth_config *pll; member
45 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio);
Ddib0090.c2237 const struct dib0090_pll *pll = state->current_pll_table_index; in dib0090_tune() local
2351 pll = dib0090_pll_table; in dib0090_tune()
2353 pll = dib0090_p1g_pll_table; in dib0090_tune()
2358 while (state->rf_request > pll->max_freq) in dib0090_tune()
2359 pll++; in dib0090_tune()
2362 state->current_pll_table_index = pll; in dib0090_tune()
2366 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2; in dib0090_tune()
2372 FBDiv = (VCOF_kHz / pll->topresc / FREF); in dib0090_tune()
2373 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; in dib0090_tune()
2392 if (pll->vco_band) in dib0090_tune()
[all …]
/linux-4.1.27/drivers/video/fbdev/riva/
Driva_hw.c619 unsigned int M, N, P, pll, MClk; in nv3UpdateArbitrationSettings() local
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv3UpdateArbitrationSettings()
622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv3UpdateArbitrationSettings()
808 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv4UpdateArbitrationSettings() local
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv4UpdateArbitrationSettings()
811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); in nv4UpdateArbitrationSettings()
814 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; in nv4UpdateArbitrationSettings()
1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1; in nv10UpdateArbitrationSettings() local
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); in nv10UpdateArbitrationSettings()
[all …]
/linux-4.1.27/arch/arm/mach-s3c24xx/
DMakefile15 obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
28 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
29 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
Dcpufreq-utils.c65 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
/linux-4.1.27/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8960.c30 struct clk *pll; member
547 phy_8960->pll = devm_clk_register(&hdmi->pdev->dev, &phy_8960->pll_hw); in hdmi_phy_8960_init()
548 if (IS_ERR(phy_8960->pll)) { in hdmi_phy_8960_init()
549 ret = PTR_ERR(phy_8960->pll); in hdmi_phy_8960_init()
550 phy_8960->pll = NULL; in hdmi_phy_8960_init()
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dar5008_phy.c892 u32 pll; in ar9160_hw_compute_pll_control() local
894 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
897 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
899 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
902 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
904 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
906 return pll; in ar9160_hw_compute_pll_control()
912 u32 pll; in ar5008_hw_compute_pll_control() local
914 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; in ar5008_hw_compute_pll_control()
917 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
Dar9002_phy.c453 u32 pll; in ar9002_hw_compute_pll_control() local
464 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
465 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
472 return pll; in ar9002_hw_compute_pll_control()
Dar9003_phy.c605 u32 pll; in ar9003_hw_compute_pll_control_soc() local
607 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
610 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
612 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
614 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
616 return pll; in ar9003_hw_compute_pll_control_soc()
622 u32 pll; in ar9003_hw_compute_pll_control() local
624 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
627 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
629 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
[all …]
/linux-4.1.27/arch/parisc/include/asm/
Drtc.h121 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
125 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
/linux-4.1.27/arch/alpha/include/asm/
Dcore_marvel.h268 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7) argument
269 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7) argument
/linux-4.1.27/Documentation/devicetree/bindings/media/i2c/
Dadv7343.txt16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
39 adi,power-mode-pll-ctrl;
/linux-4.1.27/Documentation/devicetree/bindings/soc/fsl/
Dqman.txt145 platform_pll: platform-pll@c00 {
148 compatible = "fsl,qoriq-platform-pll-1.0";
150 clock-output-names = "platform-pll", "platform-pll-div2";
/linux-4.1.27/drivers/video/fbdev/
Dw100fb.c1067 static int w100_pll_adjust(struct w100_pll_info *pll) in w100_pll_adjust() argument
1091 if (tf80 >= (pll->tfgoal)) { in w100_pll_adjust()
1097 if (tf20 <= (pll->tfgoal)) in w100_pll_adjust()
1125 static int w100_pll_calibration(struct w100_pll_info *pll) in w100_pll_calibration() argument
1129 status = w100_pll_adjust(pll); in w100_pll_calibration()
1154 static int w100_pll_set_clk(struct w100_pll_info *pll) in w100_pll_set_clk() argument
1169 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; in w100_pll_set_clk()
1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int; in w100_pll_set_clk()
1171 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac; in w100_pll_set_clk()
1172 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time; in w100_pll_set_clk()
[all …]
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
Dconfig_defs.h92 unsigned int pll : 1; member
100 unsigned int pll : 1; member
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dconfig_defs.h92 unsigned int pll : 1; member
100 unsigned int pll : 1; member
/linux-4.1.27/drivers/clk/socfpga/
DMakefile3 obj-y += clk-pll.o
/linux-4.1.27/Documentation/video4linux/bttv/
DREADME.WINVIEW26 To use the driver I use the following options, the tuner and pll settings might
32 insmod bttv pll=1 radio=1 card=17
/linux-4.1.27/include/asm-generic/
Drtc.h209 static inline int get_rtc_pll(struct rtc_pll_info *pll) in get_rtc_pll() argument
213 static inline int set_rtc_pll(struct rtc_pll_info *pll) in set_rtc_pll() argument
/linux-4.1.27/drivers/bcma/
Ddriver_chipcommon_pmu.c447 u32 pll; in bcma_pmu_get_cpu_clock() local
454 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
458 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
461 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; in bcma_pmu_get_cpu_clock()
465 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); in bcma_pmu_get_cpu_clock()
/linux-4.1.27/drivers/mfd/
Dtwl6040.c319 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; in twl6040_power()
373 if (pll_id != twl6040->pll) { in twl6040_set_pll()
402 if (twl6040->pll == pll_id) in twl6040_set_pll()
490 twl6040->pll = pll_id; in twl6040_set_pll()
501 return twl6040->pll; in twl6040_get_pll()
/linux-4.1.27/arch/m68k/coldfire/
Dm5407.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5206.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5307.c32 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm523x.c26 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm525x.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm528x.c28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5249.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5272.c34 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm54xx.c32 DEFINE_CLK(pll, "pll.0", MCF_CLK);
/linux-4.1.27/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt71 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
79 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
99 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
103 - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
107 - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
/linux-4.1.27/drivers/media/pci/cx18/
Dcx18-av-core.c461 int fsc, pll; in cx18_av_std_setup() local
464 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; in cx18_av_std_setup()
465 pll /= pll_post; in cx18_av_std_setup()
467 pll / 1000000, pll % 1000000); in cx18_av_std_setup()
469 pll / 8000000, (pll / 8) % 1000000); in cx18_av_std_setup()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c148 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_single() local
152 if (oldpll == pll) in setPLL_single()
176 nv_wr32(devinit, reg, pll); in setPLL_single()
/linux-4.1.27/drivers/media/tuners/
Dtda18271-common.c268 enum tda18271_pll pll, int force, in __tda18271_charge_pump_source() argument
274 int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4; in __tda18271_charge_pump_source()
283 enum tda18271_pll pll, int force) in tda18271_charge_pump_source() argument
285 return __tda18271_charge_pump_source(fe, pll, force, true); in tda18271_charge_pump_source()

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