1Exynos MIPI DSI Master
2
3Required properties:
4  - compatible: value should be one of the following
5		"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6		"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7		"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
8		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
9  - reg: physical base address and length of the registers set for the device
10  - interrupts: should contain DSI interrupt
11  - clocks: list of clock specifiers, must contain an entry for each required
12    entry in clock-names
13  - clock-names: should include "bus_clk"and "pll_clk" entries
14  - phys: list of phy specifiers, must contain an entry for each required
15    entry in phy-names
16  - phy-names: should include "dsim" entry
17  - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
18  - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
19  - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
20  - #address-cells, #size-cells: should be set respectively to <1> and <0>
21    according to DSI host bindings (see MIPI DSI bindings [1])
22
23Optional properties:
24  - power-domains: a phandle to DSIM power domain node
25
26Child nodes:
27  Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
28
29Video interfaces:
30  Device node can contain video interface port nodes according to [2].
31  The following are properties specific to those nodes:
32
33  port node:
34    - reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port;
35
36  endpoint node of DSI port (reg = 1):
37    - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
38      mode
39    - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
40
41[1]: Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
42[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
43
44Example:
45
46	dsi@11C80000 {
47		compatible = "samsung,exynos4210-mipi-dsi";
48		reg = <0x11C80000 0x10000>;
49		interrupts = <0 79 0>;
50		clocks = <&clock 286>, <&clock 143>;
51		clock-names = "bus_clk", "pll_clk";
52		phys = <&mipi_phy 1>;
53		phy-names = "dsim";
54		vddcore-supply = <&vusb_reg>;
55		vddio-supply = <&vmipi_reg>;
56		power-domains = <&pd_lcd0>;
57		#address-cells = <1>;
58		#size-cells = <0>;
59		samsung,pll-clock-frequency = <24000000>;
60
61		panel@1 {
62			reg = <0>;
63			...
64			port {
65				panel_ep: endpoint {
66					remote-endpoint = <&dsi_ep>;
67				};
68			};
69		};
70
71		ports {
72			#address-cells = <1>;
73			#size-cells = <0>;
74
75			port@1 {
76				dsi_ep: endpoint {
77					reg = <0>;
78					samsung,burst-clock-frequency = <500000000>;
79					samsung,esc-clock-frequency = <20000000>;
80					remote-endpoint = <&panel_ep>;
81				};
82			};
83		};
84	};
85