Lines Matching refs:pll
928 void radeon_compute_pll_avivo(struct radeon_pll *pll, in radeon_compute_pll_avivo() argument
936 unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? in radeon_compute_pll_avivo()
946 fb_div_min = pll->min_feedback_div; in radeon_compute_pll_avivo()
947 fb_div_max = pll->max_feedback_div; in radeon_compute_pll_avivo()
949 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
955 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
956 ref_div_min = pll->reference_div; in radeon_compute_pll_avivo()
958 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo()
960 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && in radeon_compute_pll_avivo()
961 pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_avivo()
962 ref_div_max = pll->reference_div; in radeon_compute_pll_avivo()
963 else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
965 ref_div_max = min(pll->max_ref_div, 7u); in radeon_compute_pll_avivo()
967 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo()
970 if (pll->flags & RADEON_PLL_USE_POST_DIV) { in radeon_compute_pll_avivo()
971 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
972 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
976 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_avivo()
977 vco_min = pll->lcd_pll_out_min; in radeon_compute_pll_avivo()
978 vco_max = pll->lcd_pll_out_max; in radeon_compute_pll_avivo()
980 vco_min = pll->pll_out_min; in radeon_compute_pll_avivo()
981 vco_max = pll->pll_out_max; in radeon_compute_pll_avivo()
984 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
992 if (post_div_min < pll->min_post_div) in radeon_compute_pll_avivo()
993 post_div_min = pll->min_post_div; in radeon_compute_pll_avivo()
998 if (post_div_max > pll->max_post_div) in radeon_compute_pll_avivo()
999 post_div_max = pll->max_post_div; in radeon_compute_pll_avivo()
1004 den = pll->reference_freq; in radeon_compute_pll_avivo()
1010 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) in radeon_compute_pll_avivo()
1020 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1024 !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) { in radeon_compute_pll_avivo()
1041 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { in radeon_compute_pll_avivo()
1051 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_avivo()
1059 *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + in radeon_compute_pll_avivo()
1060 (pll->reference_freq * *frac_fb_div_p)) / in radeon_compute_pll_avivo()
1081 void radeon_compute_pll_legacy(struct radeon_pll *pll, in radeon_compute_pll_legacy() argument
1089 uint32_t min_ref_div = pll->min_ref_div; in radeon_compute_pll_legacy()
1090 uint32_t max_ref_div = pll->max_ref_div; in radeon_compute_pll_legacy()
1091 uint32_t min_post_div = pll->min_post_div; in radeon_compute_pll_legacy()
1092 uint32_t max_post_div = pll->max_post_div; in radeon_compute_pll_legacy()
1095 uint32_t best_vco = pll->best_vco; in radeon_compute_pll_legacy()
1106 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy()
1109 if (pll->flags & RADEON_PLL_IS_LCD) { in radeon_compute_pll_legacy()
1110 pll_out_min = pll->lcd_pll_out_min; in radeon_compute_pll_legacy()
1111 pll_out_max = pll->lcd_pll_out_max; in radeon_compute_pll_legacy()
1113 pll_out_min = pll->pll_out_min; in radeon_compute_pll_legacy()
1114 pll_out_max = pll->pll_out_max; in radeon_compute_pll_legacy()
1120 if (pll->flags & RADEON_PLL_USE_REF_DIV) in radeon_compute_pll_legacy()
1121 min_ref_div = max_ref_div = pll->reference_div; in radeon_compute_pll_legacy()
1125 uint32_t pll_in = pll->reference_freq / mid; in radeon_compute_pll_legacy()
1126 if (pll_in < pll->pll_in_min) in radeon_compute_pll_legacy()
1128 else if (pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1135 if (pll->flags & RADEON_PLL_USE_POST_DIV) in radeon_compute_pll_legacy()
1136 min_post_div = max_post_div = pll->post_div; in radeon_compute_pll_legacy()
1138 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) { in radeon_compute_pll_legacy()
1139 min_fractional_feed_div = pll->min_frac_feedback_div; in radeon_compute_pll_legacy()
1140 max_fractional_feed_div = pll->max_frac_feedback_div; in radeon_compute_pll_legacy()
1146 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) in radeon_compute_pll_legacy()
1150 if (pll->flags & RADEON_PLL_LEGACY) { in radeon_compute_pll_legacy()
1164 uint32_t pll_in = pll->reference_freq / ref_div; in radeon_compute_pll_legacy()
1165 uint32_t min_feed_div = pll->min_feedback_div; in radeon_compute_pll_legacy()
1166 uint32_t max_feed_div = pll->max_feedback_div + 1; in radeon_compute_pll_legacy()
1168 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max) in radeon_compute_pll_legacy()
1180 tmp = (uint64_t)pll->reference_freq * feedback_div; in radeon_compute_pll_legacy()
1193 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div; in radeon_compute_pll_legacy()
1194 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; in radeon_compute_pll_legacy()
1197 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { in radeon_compute_pll_legacy()
1226 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || in radeon_compute_pll_legacy()
1227 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || in radeon_compute_pll_legacy()
1228 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || in radeon_compute_pll_legacy()
1229 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || in radeon_compute_pll_legacy()
1230 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || in radeon_compute_pll_legacy()
1231 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { in radeon_compute_pll_legacy()