Home
last modified time | relevance | path

Searched refs:lane (Results 1 – 75 of 75) sorted by relevance

/linux-4.1.27/drivers/phy/
Dphy-xgene.c669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
675 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
689 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
700 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
702 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
710 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
712 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
[all …]
/linux-4.1.27/drivers/gpu/drm/exynos/
Dexynos_dp_core.c270 int pre_emphasis, int lane) in exynos_dp_set_lane_lane_pre_emphasis() argument
272 switch (lane) { in exynos_dp_set_lane_lane_pre_emphasis()
293 int lane, lane_count, pll_tries, retval; in exynos_dp_link_start() local
300 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
301 dp->link_train.cr_loop[lane] = 0; in exynos_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
318 PRE_EMPHASIS_LEVEL_0, lane); in exynos_dp_link_start()
342 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
343 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | in exynos_dp_link_start()
352 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) in exynos_dp_get_lane_status() argument
[all …]
/linux-4.1.27/drivers/gpu/drm/
Ddrm_dp_helper.c49 int lane) in dp_get_lane_status() argument
51 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
52 int s = (lane & 1) * 4; in dp_get_lane_status()
62 int lane; in drm_dp_channel_eq_ok() local
68 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
69 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
80 int lane; in drm_dp_clock_recovery_ok() local
83 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
84 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
93 int lane) in drm_dp_get_adjust_request_voltage() argument
[all …]
/linux-4.1.27/arch/x86/crypto/sha-mb/
Dsha1_mb_mgr_submit_avx2.S89 lane = %rbp define
118 mov unused_lanes, lane
119 and $0xF, lane
121 imul $_LANE_DATA_size, lane, lane_data
129 or lane, len
131 movl DWORD_len, _lens(state , lane, 4)
136 vmovd %xmm0, _args_digest(state, lane, 4)
137 vpextrd $1, %xmm0, _args_digest+1*32(state , lane, 4)
138 vpextrd $2, %xmm0, _args_digest+2*32(state , lane, 4)
139 vpextrd $3, %xmm0, _args_digest+3*32(state , lane, 4)
[all …]
Dsha1_mb_mgr_flush_avx2.S132 # find a lane with a non-null job
/linux-4.1.27/arch/mips/cavium-octeon/executive/
Dcvmx-helper-errata.c51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
/linux-4.1.27/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c155 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
163 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
169 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
173 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
189 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable() argument
192 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); in netcp_xgbe_serdes_lane_enable()
290 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr() argument
296 serdes_regs, lane + 1, 5); in netcp_xgbe_serdes_reset_cdr()
305 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + in netcp_xgbe_serdes_reset_cdr()
437 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2() argument
[all …]
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-tegra-xusb.c294 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
298 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
300 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_pinmux_set()
301 if (lane->funcs[i] == function) in tegra_xusb_padctl_pinmux_set()
304 if (i >= lane->num_funcs) in tegra_xusb_padctl_pinmux_set()
307 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
308 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
309 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
310 padctl_writel(padctl, value, lane->offset); in tegra_xusb_padctl_pinmux_set()
327 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_get() local
[all …]
/linux-4.1.27/drivers/ata/
Dsata_highbank.c273 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
277 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in highbank_cphy_disable_overrides()
279 combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); in highbank_cphy_disable_overrides()
284 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
290 tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_override_tx_attenuation()
292 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
295 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
298 combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_override_tx_attenuation()
303 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
305 tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_override_rx_mode()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dvideo-interfaces.txt93 - data-lanes: an array of physical data lane indexes. Position of an entry
94 determines the logical lane number, while the value of an entry indicates
95 physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
96 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
98 - clock-lanes: an array of physical clock lane indexes. Position of an entry
99 determines the logical lane number, while the value of an entry indicates
100 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
101 which places the clock lane on hardware lane 0. This property is valid for
108 lane value. An array of 64-bit unsigned integers.
109 - lane-polarities: an array of polarities of the lanes starting from the clock
[all …]
Dti,omap3isp.txt48 lane-polarities : lane polarity (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
Dsamsung-s5c73m3.txt49 video-interfaces.txt. This sensor doesn't support data lane remapping
50 and physical lane indexes in subsequent elements of the array should
Dsamsung-s5k6a3.txt33 video-interfaces.txt. The sensor supports only one data lane.
Dsamsung-s5k5baf.txt36 supports only one data lane without re-mapping.
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddport.c128 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; in dp_link_train_commit() local
130 u8 lpre = (lane & 0x0c) >> 2; in dp_link_train_commit()
131 u8 lvsw = (lane & 0x03) >> 0; in dp_link_train_commit()
209 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in dp_link_train_cr() local
210 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { in dp_link_train_cr()
247 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in dp_link_train_eq() local
248 if (!(lane & DPCD_LS02_LANE0_CR_DONE)) in dp_link_train_eq()
250 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || in dp_link_train_eq()
251 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) in dp_link_train_eq()
Doutpdp.c66 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; in nvkm_output_dp_train() local
67 if (!(lane & DPCD_LS02_LANE0_CR_DONE) || in nvkm_output_dp_train()
68 !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || in nvkm_output_dp_train()
69 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) { in nvkm_output_dp_train()
70 DBG("lane %d not equalised\n", lane); in nvkm_output_dp_train()
Dsorg94.c43 g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in g94_sor_dp_lane_map() argument
48 return mcp89[lane]; in g94_sor_dp_lane_map()
49 return g94[lane]; in g94_sor_dp_lane_map()
Dsorgf110.c40 gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in gf110_sor_dp_lane_map() argument
43 return gf110[lane]; in gf110_sor_dp_lane_map()
Dsorgm204.c54 gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in gm204_sor_dp_lane_map() argument
56 return lane * 0x08; in gm204_sor_dp_lane_map()
/linux-4.1.27/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
143 marvell,pcie-lane = <0>;
164 marvell,pcie-lane = <1>;
181 marvell,pcie-lane = <2>;
198 marvell,pcie-lane = <3>;
215 marvell,pcie-lane = <0>;
232 marvell,pcie-lane = <1>;
249 marvell,pcie-lane = <2>;
266 marvell,pcie-lane = <3>;
283 marvell,pcie-lane = <0>;
[all …]
/linux-4.1.27/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c1250 int lane) in cdv_intel_get_adjust_request_voltage() argument
1252 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in cdv_intel_get_adjust_request_voltage()
1253 int s = ((lane & 1) ? in cdv_intel_get_adjust_request_voltage()
1263 int lane) in cdv_intel_get_adjust_request_pre_emphasis() argument
1265 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); in cdv_intel_get_adjust_request_pre_emphasis()
1266 int s = ((lane & 1) ? in cdv_intel_get_adjust_request_pre_emphasis()
1311 int lane; in cdv_intel_get_adjust_train() local
1313 for (lane = 0; lane < intel_dp->lane_count; lane++) { in cdv_intel_get_adjust_train()
1314 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane); in cdv_intel_get_adjust_train()
1315 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); in cdv_intel_get_adjust_train()
[all …]
/linux-4.1.27/arch/arm/mach-mv78xx0/
Dpcie.c21 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
22 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
23 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
24 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
/linux-4.1.27/drivers/net/ethernet/sfc/
Dtxc43128_phy.c211 int lane; in txc_bist_one() local
245 for (lane = 0; lane < 4; lane++) { in txc_bist_one()
246 int count = efx_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane); in txc_bist_one()
249 "Lane %d had %d errs\n", lane, count); in txc_bist_one()
252 count = efx_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane); in txc_bist_one()
255 "Lane %d got 0 frames\n", lane); in txc_bist_one()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Dhdmi_phy.c47 u8 lane, pol; in hdmi_phy_parse_lanes() local
69 lane = dx / 2; in hdmi_phy_parse_lanes()
71 phy->lane_function[lane] = i / 2; in hdmi_phy_parse_lanes()
72 phy->lane_polarity[lane] = pol; in hdmi_phy_parse_lanes()
Ddsi.c3789 u8 lane, pol; in dsi_configure_pins() local
3811 lane = dx / 2; in dsi_configure_pins()
3813 lanes[lane].function = functions[i / 2]; in dsi_configure_pins()
3814 lanes[lane].polarity = pol; in dsi_configure_pins()
/linux-4.1.27/drivers/media/v4l2-core/
Dv4l2-of.c33 const __be32 *lane = NULL; in v4l2_of_parse_csi_bus() local
37 lane = of_prop_next_u32(prop, lane, &v); in v4l2_of_parse_csi_bus()
38 if (!lane) in v4l2_of_parse_csi_bus()
/linux-4.1.27/arch/arm/boot/dts/
Darmada-xp-mv78460.dtsi165 marvell,pcie-lane = <0>;
182 marvell,pcie-lane = <1>;
199 marvell,pcie-lane = <2>;
216 marvell,pcie-lane = <3>;
233 marvell,pcie-lane = <0>;
250 marvell,pcie-lane = <1>;
267 marvell,pcie-lane = <2>;
284 marvell,pcie-lane = <3>;
301 marvell,pcie-lane = <0>;
318 marvell,pcie-lane = <0>;
Darmada-xp-mv78260.dtsi144 marvell,pcie-lane = <0>;
161 marvell,pcie-lane = <1>;
178 marvell,pcie-lane = <2>;
195 marvell,pcie-lane = <3>;
212 marvell,pcie-lane = <0>;
229 marvell,pcie-lane = <1>;
246 marvell,pcie-lane = <2>;
263 marvell,pcie-lane = <3>;
280 marvell,pcie-lane = <0>;
Darmada-xp-mv78230.dtsi129 marvell,pcie-lane = <0>;
146 marvell,pcie-lane = <1>;
163 marvell,pcie-lane = <2>;
180 marvell,pcie-lane = <3>;
197 marvell,pcie-lane = <0>;
Darmada-385.dtsi121 marvell,pcie-lane = <0>;
139 marvell,pcie-lane = <0>;
157 marvell,pcie-lane = <0>;
178 marvell,pcie-lane = <0>;
Darmada-380.dtsi110 marvell,pcie-lane = <0>;
128 marvell,pcie-lane = <0>;
146 marvell,pcie-lane = <0>;
Dkirkwood-6282.dtsi34 marvell,pcie-lane = <0>;
51 marvell,pcie-lane = <0>;
Dkirkwood-98dx4122.dtsi30 marvell,pcie-lane = <0>;
Domap3-n9.dts51 lane-polarities = <1 1 1>;
Domap3-n950.dts51 lane-polarities = <1 1 1>;
Darmada-39x.dtsi436 marvell,pcie-lane = <0>;
454 marvell,pcie-lane = <0>;
472 marvell,pcie-lane = <0>;
493 marvell,pcie-lane = <0>;
Dkirkwood-6281.dtsi30 marvell,pcie-lane = <0>;
Dkirkwood-6192.dtsi30 marvell,pcie-lane = <0>;
Darmada-370.dtsi104 marvell,pcie-lane = <0>;
121 marvell,pcie-lane = <0>;
Darmada-375.dtsi593 marvell,pcie-lane = <0>;
610 marvell,pcie-lane = <1>;
Dexynos5250-smdk5250.dts83 samsung,lane-count = <4>;
Dexynos5420-smdk5420.dts112 samsung,lane-count = <4>;
Dexynos5420-peach-pit.dts155 samsung,lane-count = <2>;
623 lane-count = <2>;
Dexynos5250-arndale.dts127 samsung,lane-count = <4>;
Dexynos5250-spring.dts77 samsung,lane-count = <1>;
Dexynos5250-snow.dts271 samsung,lane-count = <2>;
Dexynos5800-peach-pi.dts149 samsung,lane-count = <2>;
/linux-4.1.27/drivers/gpu/drm/radeon/
Datombios_dp.c263 int lane; in dp_get_adjust_train() local
265 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
266 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in dp_get_adjust_train()
267 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in dp_get_adjust_train()
270 lane, in dp_get_adjust_train()
290 for (lane = 0; lane < 4; lane++) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
/linux-4.1.27/Documentation/devicetree/bindings/video/bridge/
Dps8622.txt10 - lane-count: number of DP lanes to use
23 lane-count = <1>;
/linux-4.1.27/drivers/video/fbdev/
Dsh_mipi_dsi.c221 if (!pdata->lane) in sh_mipi_setup()
267 bitmap_fill((unsigned long *)&tmp, pdata->lane); in sh_mipi_setup()
313 bottom = (pdata->lane * mode->hsync_len) - 10; in sh_mipi_setup()
334 top = ((pdata->lane * top / div) - 10) << 16; in sh_mipi_setup()
338 bottom = (pdata->lane * bottom / div) - 12; in sh_mipi_setup()
342 if ((pdata->lane / div) > bpp) { in sh_mipi_setup()
345 delay = (pdata->lane * tmp); in sh_mipi_setup()
/linux-4.1.27/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c433 u8 lane; in edp_fill_link_cfg() local
451 for (lane = 1; lane <= max_lane; lane <<= 1) { in edp_fill_link_cfg()
457 ctrl->lane_cnt = lane; in edp_fill_link_cfg()
725 u8 rate, lane, max_lane; in edp_link_rate_down_shift() local
729 lane = ctrl->lane_cnt; in edp_link_rate_down_shift()
743 if (lane >= 1 && lane < max_lane) in edp_link_rate_down_shift()
744 lane <<= 1; /* increase lane */ in edp_link_rate_down_shift()
749 lrate *= lane; in edp_link_rate_down_shift()
752 lrate, prate, rate, lane, in edp_link_rate_down_shift()
758 ctrl->lane_cnt = lane; in edp_link_rate_down_shift()
[all …]
/linux-4.1.27/Documentation/devicetree/bindings/ata/
Dsata_highbank.txt15 - calxeda,port-phys : phandle-combophy and lane assignment, which maps each
16 SATA port to a combophy and a lane within that
/linux-4.1.27/drivers/edac/
Dppc4xx_edac.h159 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) argument
Dppc4xx_edac.c441 unsigned int lane, lanes; in ppc4xx_edac_generate_lane_message() local
454 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
455 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { in ppc4xx_edac_generate_lane_message()
458 (lanes++ ? ", " : ""), lane); in ppc4xx_edac_generate_lane_message()
/linux-4.1.27/drivers/pci/host/
Dpci-mvebu.c115 u32 lane; member
1004 &port->lane)) in mvebu_pcie_probe()
1005 port->lane = 0; in mvebu_pcie_probe()
1008 port->port, port->lane); in mvebu_pcie_probe()
1018 port->port, port->lane); in mvebu_pcie_probe()
1037 "pcie%d.%d-reset", port->port, port->lane); in mvebu_pcie_probe()
1057 port->port, port->lane); in mvebu_pcie_probe()
1068 port->port, port->lane); in mvebu_pcie_probe()
Dpci-tegra.c1598 unsigned int lane = 0; in tegra_pcie_parse_dt() local
1708 lane += value; in tegra_pcie_parse_dt()
1712 mask |= ((1 << value) - 1) << lane; in tegra_pcie_parse_dt()
1713 lane += value; in tegra_pcie_parse_dt()
Dpcie-rcar.c421 unsigned int lane, unsigned int data) in phy_write_reg() argument
427 ((lane & 0xf) << LANE_POS) | in phy_write_reg()
/linux-4.1.27/include/video/
Dsh_mipi_dsi.h49 int lane; member
/linux-4.1.27/drivers/gpu/drm/tegra/
Dsor.c137 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
140 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
158 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
161 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
173 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
176 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
1154 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_encoder_mode_set() local
1157 value = (value << 8) | lane; in tegra_sor_encoder_mode_set()
1240 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_encoder_mode_set() local
1243 value = (value << 8) | lane; in tegra_sor_encoder_mode_set()
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dexynos_dp.txt49 -samsung,lane-count:
96 samsung,lane-count = <4>;
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_reg.h1104 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ argument
1105 (lane) * 0x200 + (offset))
1107 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) argument
1108 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) argument
1109 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) argument
1110 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) argument
1111 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) argument
1112 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) argument
1113 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) argument
1114 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) argument
[all …]
Dintel_dp.c3248 int lane; in intel_get_adjust_train() local
3252 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
3253 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); in intel_get_adjust_train()
3254 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); in intel_get_adjust_train()
3270 for (lane = 0; lane < 4; lane++) in intel_get_adjust_train()
3271 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()
Dintel_display.c5766 int lane, link_bw, fdi_dotclock; in ironlake_fdi_compute_config() local
5781 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, in ironlake_fdi_compute_config()
5784 pipe_config->fdi_lanes = lane; in ironlake_fdi_compute_config()
5786 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_link.c3228 u8 lane = 0; in bnx2x_get_warpcore_lane() local
3259 lane = (port<<1) + path; in bnx2x_get_warpcore_lane()
3274 lane = path << 1 ; in bnx2x_get_warpcore_lane()
3276 return lane; in bnx2x_get_warpcore_lane()
3532 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_ext_phy_update_adv_fc() local
3539 lane; in bnx2x_ext_phy_update_adv_fc()
3704 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_restart_AN_KR() local
3706 MDIO_AER_BLOCK_AER_REG, lane); in bnx2x_warpcore_restart_AN_KR()
3717 u16 lane, i, cl72_ctrl, an_adv = 0, val; in bnx2x_warpcore_enable_AN_KR() local
3770 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_enable_AN_KR()
[all …]
/linux-4.1.27/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_lowlevel.c253 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, in exynos_mipi_dsi_enable_lane() argument
261 reg |= DSIM_LANE_ENx(lane); in exynos_mipi_dsi_enable_lane()
263 reg &= ~DSIM_LANE_ENx(lane); in exynos_mipi_dsi_enable_lane()
Dexynos_mipi_dsi_lowlevel.h49 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-xusb-padctl.txt48 - nvidia,lanes: An array of strings. Each string is the name of a lane.
54 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
/linux-4.1.27/include/drm/
Ddrm_dp_helper.h577 int lane);
579 int lane);
/linux-4.1.27/drivers/media/platform/marvell-ccic/
Dmmp-driver.c371 mcam->lane = pdata->lane; in mmpcam_probe()
Dmcam-core.h128 int lane; /* lane number */ member
Dmcam-core.c311 if (mcam->lane > 4 || mcam->lane <= 0) { in mcam_enable_mipi()
313 mcam->lane = 1; /* set the default value */ in mcam_enable_mipi()
322 CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane)); in mcam_enable_mipi()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Di2c.h53 int (*drv_ctl)(struct nvkm_i2c_port *, int lane, int sw, int pe);
/linux-4.1.27/arch/sh/drivers/pci/
Dpcie-sh7786.c182 unsigned int lane, unsigned int data) in phy_write_reg() argument
186 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + in phy_write_reg()
/linux-4.1.27/Documentation/devicetree/bindings/phy/
Dti-phy.txt83 differentiate between each instance "id" can be used (e.g., multi-lane PCIe
/linux-4.1.27/arch/x86/crypto/
Dsha512-avx2-asm.S302 # Calculate sigma1 for w[18] and w[19] for upper 128 bit lane