3228 	u8 lane = 0;  in bnx2x_get_warpcore_lane()  local
3259 		lane = (port<<1) + path;  in bnx2x_get_warpcore_lane()
3274 		lane = path << 1 ;  in bnx2x_get_warpcore_lane()
3276 	return lane;  in bnx2x_get_warpcore_lane()
3532 		u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_ext_phy_update_adv_fc()  local
3539 			lane;  in bnx2x_ext_phy_update_adv_fc()
3704 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_restart_AN_KR()  local
3706 			  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_warpcore_restart_AN_KR()
3717 	u16 lane, i, cl72_ctrl, an_adv = 0, val;  in bnx2x_warpcore_enable_AN_KR()  local
3770 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_enable_AN_KR()
3772 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_enable_AN_KR()
3777 				 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),  in bnx2x_warpcore_enable_AN_KR()
3822 				  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_warpcore_enable_AN_KR()
3825 					 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),  in bnx2x_warpcore_enable_AN_KR()
3841 				MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);  in bnx2x_warpcore_enable_AN_KR()
3851 		    (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))  in bnx2x_warpcore_enable_AN_KR()
3856 				 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),  in bnx2x_warpcore_enable_AN_KR()
3871 	u16 val16, i, lane;  in bnx2x_warpcore_set_10G_KR()  local
3889 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_KR()
3896 	val16 &= ~(0x0011 << lane);  in bnx2x_warpcore_set_10G_KR()
3902 	val16 |= (0x0303 << (lane << 1));  in bnx2x_warpcore_set_10G_KR()
3939 	u16 misc1_val, tap_val, tx_driver_val, lane, val;  in bnx2x_warpcore_set_10G_XFI()  local
4039 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_XFI()
4044 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_set_10G_XFI()
4125 					 u16 lane)  in bnx2x_warpcore_set_20G_DXGXS()  argument
4173 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in bnx2x_warpcore_set_20G_DXGXS()
4279 				      u16 lane)  in bnx2x_warpcore_clear_regs()  argument
4307 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_clear_regs()
4309 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);  in bnx2x_warpcore_clear_regs()
4373 	u16 gp2_status_reg0, lane;  in bnx2x_warpcore_get_sigdet()  local
4376 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_get_sigdet()
4381 	return (gp2_status_reg0 >> (8+lane)) & 0x1;  in bnx2x_warpcore_get_sigdet()
4398 		u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_runtime()  local
4409 			lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */  in bnx2x_warpcore_config_runtime()
4411 			lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;  in bnx2x_warpcore_config_runtime()
4440 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_sfi()  local
4442 	bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_sfi()
4482 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_init()  local
4499 		bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4514 			bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4557 			bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);  in bnx2x_warpcore_config_init()
4587 	u16 val16, lane;  in bnx2x_warpcore_link_reset()  local
4612 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_link_reset()
4616 	val16 |= (0x11 << lane);  in bnx2x_warpcore_link_reset()
4618 		val16 |= (0x22 << lane);  in bnx2x_warpcore_link_reset()
4624 	val16 &= ~(0x0303 << (lane << 1));  in bnx2x_warpcore_link_reset()
4625 	val16 |= (0x0101 << (lane << 1));  in bnx2x_warpcore_link_reset()
4627 		val16 &= ~(0x0c0c << (lane << 1));  in bnx2x_warpcore_link_reset()
4628 		val16 |= (0x0404 << (lane << 1));  in bnx2x_warpcore_link_reset()
4643 	u32 lane;  in bnx2x_set_warpcore_loopback()  local
4659 		lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_set_warpcore_loopback()
4662 		val16 |= (1<<lane);  in bnx2x_set_warpcore_loopback()
4664 			val16 |= (2<<lane);  in bnx2x_set_warpcore_loopback()
5682 	u8 lane;  in bnx2x_warpcore_read_status()  local
5685 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_read_status()
5715 			(1 << lane);  in bnx2x_warpcore_read_status()
5731 				if (gp_status4 & ((1<<12)<<lane))  in bnx2x_warpcore_read_status()
5776 	if (lane < 2) {  in bnx2x_warpcore_read_status()
5783 	DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);  in bnx2x_warpcore_read_status()
5785 	if ((lane & 1) == 0)  in bnx2x_warpcore_read_status()
6459 			u8 lane = bnx2x_get_warpcore_lane(int_phy, params);  in bnx2x_test_link()  local
6465 			link_up = gp_status & (1 << lane);  in bnx2x_test_link()
8625 	u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_limiting_mode()  local
8629 	val &= ~(0xf << (lane << 2));  in bnx2x_warpcore_set_limiting_mode()
8644 	val |= (mode << (lane << 2));  in bnx2x_warpcore_set_limiting_mode()
13556 	u16 base_page, next_page, not_kr2_device, lane;  in bnx2x_check_kr2_wa()  local
13578 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_check_kr2_wa()
13580 			  MDIO_AER_BLOCK_AER_REG, lane);  in bnx2x_check_kr2_wa()