1/* 2 * Marvell camera core structures. 3 * 4 * Copyright 2011 Jonathan Corbet corbet@lwn.net 5 */ 6#ifndef _MCAM_CORE_H 7#define _MCAM_CORE_H 8 9#include <linux/list.h> 10#include <media/v4l2-common.h> 11#include <media/v4l2-ctrls.h> 12#include <media/v4l2-dev.h> 13#include <media/videobuf2-core.h> 14 15/* 16 * Create our own symbols for the supported buffer modes, but, for now, 17 * base them entirely on which videobuf2 options have been selected. 18 */ 19#if IS_ENABLED(CONFIG_VIDEOBUF2_VMALLOC) 20#define MCAM_MODE_VMALLOC 1 21#endif 22 23#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_CONTIG) 24#define MCAM_MODE_DMA_CONTIG 1 25#endif 26 27#if IS_ENABLED(CONFIG_VIDEOBUF2_DMA_SG) 28#define MCAM_MODE_DMA_SG 1 29#endif 30 31#if !defined(MCAM_MODE_VMALLOC) && !defined(MCAM_MODE_DMA_CONTIG) && \ 32 !defined(MCAM_MODE_DMA_SG) 33#error One of the videobuf buffer modes must be selected in the config 34#endif 35 36 37enum mcam_state { 38 S_NOTREADY, /* Not yet initialized */ 39 S_IDLE, /* Just hanging around */ 40 S_FLAKED, /* Some sort of problem */ 41 S_STREAMING, /* Streaming data */ 42 S_BUFWAIT /* streaming requested but no buffers yet */ 43}; 44#define MAX_DMA_BUFS 3 45 46/* 47 * Different platforms work best with different buffer modes, so we 48 * let the platform pick. 49 */ 50enum mcam_buffer_mode { 51 B_vmalloc = 0, 52 B_DMA_contig = 1, 53 B_DMA_sg = 2 54}; 55 56enum mcam_chip_id { 57 MCAM_CAFE, 58 MCAM_ARMADA610, 59}; 60 61/* 62 * Is a given buffer mode supported by the current kernel configuration? 63 */ 64static inline int mcam_buffer_mode_supported(enum mcam_buffer_mode mode) 65{ 66 switch (mode) { 67#ifdef MCAM_MODE_VMALLOC 68 case B_vmalloc: 69#endif 70#ifdef MCAM_MODE_DMA_CONTIG 71 case B_DMA_contig: 72#endif 73#ifdef MCAM_MODE_DMA_SG 74 case B_DMA_sg: 75#endif 76 return 1; 77 default: 78 return 0; 79 } 80} 81 82/* 83 * Basic frame states 84 */ 85struct mcam_frame_state { 86 unsigned int frames; 87 unsigned int singles; 88 unsigned int delivered; 89}; 90 91#define NR_MCAM_CLK 3 92 93/* 94 * A description of one of our devices. 95 * Locking: controlled by s_mutex. Certain fields, however, require 96 * the dev_lock spinlock; they are marked as such by comments. 97 * dev_lock is also required for access to device registers. 98 */ 99struct mcam_camera { 100 /* 101 * These fields should be set by the platform code prior to 102 * calling mcam_register(). 103 */ 104 struct i2c_adapter *i2c_adapter; 105 unsigned char __iomem *regs; 106 unsigned regs_size; /* size in bytes of the register space */ 107 spinlock_t dev_lock; 108 struct device *dev; /* For messages, dma alloc */ 109 enum mcam_chip_id chip_id; 110 short int clock_speed; /* Sensor clock speed, default 30 */ 111 short int use_smbus; /* SMBUS or straight I2c? */ 112 enum mcam_buffer_mode buffer_mode; 113 114 int mclk_min; /* The minimal value of mclk */ 115 int mclk_src; /* which clock source the mclk derives from */ 116 int mclk_div; /* Clock Divider Value for MCLK */ 117 118 int ccic_id; 119 enum v4l2_mbus_type bus_type; 120 /* MIPI support */ 121 /* The dphy config value, allocated in board file 122 * dphy[0]: DPHY3 123 * dphy[1]: DPHY5 124 * dphy[2]: DPHY6 125 */ 126 int *dphy; 127 bool mipi_enabled; /* flag whether mipi is enabled already */ 128 int lane; /* lane number */ 129 130 /* clock tree support */ 131 struct clk *clk[NR_MCAM_CLK]; 132 133 /* 134 * Callbacks from the core to the platform code. 135 */ 136 int (*plat_power_up) (struct mcam_camera *cam); 137 void (*plat_power_down) (struct mcam_camera *cam); 138 void (*calc_dphy) (struct mcam_camera *cam); 139 void (*ctlr_reset) (struct mcam_camera *cam); 140 141 /* 142 * Everything below here is private to the mcam core and 143 * should not be touched by the platform code. 144 */ 145 struct v4l2_device v4l2_dev; 146 struct v4l2_ctrl_handler ctrl_handler; 147 enum mcam_state state; 148 unsigned long flags; /* Buffer status, mainly (dev_lock) */ 149 int users; /* How many open FDs */ 150 151 struct mcam_frame_state frame_state; /* Frame state counter */ 152 /* 153 * Subsystem structures. 154 */ 155 struct video_device vdev; 156 struct v4l2_subdev *sensor; 157 unsigned short sensor_addr; 158 159 /* Videobuf2 stuff */ 160 struct vb2_queue vb_queue; 161 struct list_head buffers; /* Available frames */ 162 163 unsigned int nbufs; /* How many are alloc'd */ 164 int next_buf; /* Next to consume (dev_lock) */ 165 166 /* DMA buffers - vmalloc mode */ 167#ifdef MCAM_MODE_VMALLOC 168 unsigned int dma_buf_size; /* allocated size */ 169 void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */ 170 dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */ 171 struct tasklet_struct s_tasklet; 172#endif 173 unsigned int sequence; /* Frame sequence number */ 174 unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual bufs */ 175 176 /* DMA buffers - DMA modes */ 177 struct mcam_vb_buffer *vb_bufs[MAX_DMA_BUFS]; 178 struct vb2_alloc_ctx *vb_alloc_ctx; 179 struct vb2_alloc_ctx *vb_alloc_ctx_sg; 180 181 /* Mode-specific ops, set at open time */ 182 void (*dma_setup)(struct mcam_camera *cam); 183 void (*frame_complete)(struct mcam_camera *cam, int frame); 184 185 /* Current operating parameters */ 186 struct v4l2_pix_format pix_format; 187 u32 mbus_code; 188 189 /* Locks */ 190 struct mutex s_mutex; /* Access to this structure */ 191}; 192 193 194/* 195 * Register I/O functions. These are here because the platform code 196 * may legitimately need to mess with the register space. 197 */ 198/* 199 * Device register I/O 200 */ 201static inline void mcam_reg_write(struct mcam_camera *cam, unsigned int reg, 202 unsigned int val) 203{ 204 iowrite32(val, cam->regs + reg); 205} 206 207static inline unsigned int mcam_reg_read(struct mcam_camera *cam, 208 unsigned int reg) 209{ 210 return ioread32(cam->regs + reg); 211} 212 213 214static inline void mcam_reg_write_mask(struct mcam_camera *cam, unsigned int reg, 215 unsigned int val, unsigned int mask) 216{ 217 unsigned int v = mcam_reg_read(cam, reg); 218 219 v = (v & ~mask) | (val & mask); 220 mcam_reg_write(cam, reg, v); 221} 222 223static inline void mcam_reg_clear_bit(struct mcam_camera *cam, 224 unsigned int reg, unsigned int val) 225{ 226 mcam_reg_write_mask(cam, reg, 0, val); 227} 228 229static inline void mcam_reg_set_bit(struct mcam_camera *cam, 230 unsigned int reg, unsigned int val) 231{ 232 mcam_reg_write_mask(cam, reg, val, val); 233} 234 235/* 236 * Functions for use by platform code. 237 */ 238int mccic_register(struct mcam_camera *cam); 239int mccic_irq(struct mcam_camera *cam, unsigned int irqs); 240void mccic_shutdown(struct mcam_camera *cam); 241#ifdef CONFIG_PM 242void mccic_suspend(struct mcam_camera *cam); 243int mccic_resume(struct mcam_camera *cam); 244#endif 245 246/* 247 * Register definitions for the m88alp01 camera interface. Offsets in bytes 248 * as given in the spec. 249 */ 250#define REG_Y0BAR 0x00 251#define REG_Y1BAR 0x04 252#define REG_Y2BAR 0x08 253#define REG_U0BAR 0x0c 254#define REG_U1BAR 0x10 255#define REG_U2BAR 0x14 256#define REG_V0BAR 0x18 257#define REG_V1BAR 0x1C 258#define REG_V2BAR 0x20 259 260/* 261 * register definitions for MIPI support 262 */ 263#define REG_CSI2_CTRL0 0x100 264#define CSI2_C0_MIPI_EN (0x1 << 0) 265#define CSI2_C0_ACT_LANE(n) ((n-1) << 1) 266#define REG_CSI2_DPHY3 0x12c 267#define REG_CSI2_DPHY5 0x134 268#define REG_CSI2_DPHY6 0x138 269 270/* ... */ 271 272#define REG_IMGPITCH 0x24 /* Image pitch register */ 273#define IMGP_YP_SHFT 2 /* Y pitch params */ 274#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */ 275#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */ 276#define IMGP_UVP_MASK 0x3ffc0000 277#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */ 278#define IRQ_EOF0 0x00000001 /* End of frame 0 */ 279#define IRQ_EOF1 0x00000002 /* End of frame 1 */ 280#define IRQ_EOF2 0x00000004 /* End of frame 2 */ 281#define IRQ_SOF0 0x00000008 /* Start of frame 0 */ 282#define IRQ_SOF1 0x00000010 /* Start of frame 1 */ 283#define IRQ_SOF2 0x00000020 /* Start of frame 2 */ 284#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */ 285#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */ 286#define IRQ_TWSIR 0x00020000 /* TWSI read */ 287#define IRQ_TWSIE 0x00040000 /* TWSI error */ 288#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE) 289#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2) 290#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW) 291#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */ 292#define REG_IRQSTAT 0x30 /* IRQ status / clear */ 293 294#define REG_IMGSIZE 0x34 /* Image size */ 295#define IMGSZ_V_MASK 0x1fff0000 296#define IMGSZ_V_SHIFT 16 297#define IMGSZ_H_MASK 0x00003fff 298#define REG_IMGOFFSET 0x38 /* IMage offset */ 299 300#define REG_CTRL0 0x3c /* Control 0 */ 301#define C0_ENABLE 0x00000001 /* Makes the whole thing go */ 302 303/* Mask for all the format bits */ 304#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */ 305 306/* RGB ordering */ 307#define C0_RGB4_RGBX 0x00000000 308#define C0_RGB4_XRGB 0x00000004 309#define C0_RGB4_BGRX 0x00000008 310#define C0_RGB4_XBGR 0x0000000c 311#define C0_RGB5_RGGB 0x00000000 312#define C0_RGB5_GRBG 0x00000004 313#define C0_RGB5_GBRG 0x00000008 314#define C0_RGB5_BGGR 0x0000000c 315 316/* Spec has two fields for DIN and DOUT, but they must match, so 317 combine them here. */ 318#define C0_DF_YUV 0x00000000 /* Data is YUV */ 319#define C0_DF_RGB 0x000000a0 /* ... RGB */ 320#define C0_DF_BAYER 0x00000140 /* ... Bayer */ 321/* 8-8-8 must be missing from the below - ask */ 322#define C0_RGBF_565 0x00000000 323#define C0_RGBF_444 0x00000800 324#define C0_RGB_BGR 0x00001000 /* Blue comes first */ 325#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */ 326#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */ 327#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */ 328/* Think that 420 packed must be 111 - ask */ 329#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */ 330#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */ 331#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */ 332#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */ 333#define C0_YUVE_NOSWAP 0x00000000 /* no bytes swapping */ 334#define C0_YUVE_SWAP13 0x00010000 /* swap byte 1 and 3 */ 335#define C0_YUVE_SWAP24 0x00020000 /* swap byte 2 and 4 */ 336#define C0_YUVE_SWAP1324 0x00030000 /* swap bytes 1&3 and 2&4 */ 337/* Bayer bits 18,19 if needed */ 338#define C0_EOF_VSYNC 0x00400000 /* Generate EOF by VSYNC */ 339#define C0_VEDGE_CTRL 0x00800000 /* Detect falling edge of VSYNC */ 340#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */ 341#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */ 342#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */ 343#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */ 344/* SIFMODE */ 345#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */ 346#define C0_SOF_NOSYNC 0x40000000 /* Use inband active signaling */ 347#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */ 348 349/* Bits below C1_444ALPHA are not present in Cafe */ 350#define REG_CTRL1 0x40 /* Control 1 */ 351#define C1_CLKGATE 0x00000001 /* Sensor clock gate */ 352#define C1_DESC_ENA 0x00000100 /* DMA descriptor enable */ 353#define C1_DESC_3WORD 0x00000200 /* Three-word descriptors used */ 354#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */ 355#define C1_ALPHA_SHFT 20 356#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */ 357#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */ 358#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */ 359#define C1_DMAB_MASK 0x06000000 360#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */ 361#define C1_PWRDWN 0x10000000 /* Power down */ 362 363#define REG_CLKCTRL 0x88 /* Clock control */ 364#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */ 365 366/* This appears to be a Cafe-only register */ 367#define REG_UBAR 0xc4 /* Upper base address register */ 368 369/* Armada 610 DMA descriptor registers */ 370#define REG_DMA_DESC_Y 0x200 371#define REG_DMA_DESC_U 0x204 372#define REG_DMA_DESC_V 0x208 373#define REG_DESC_LEN_Y 0x20c /* Lengths are in bytes */ 374#define REG_DESC_LEN_U 0x210 375#define REG_DESC_LEN_V 0x214 376 377/* 378 * Useful stuff that probably belongs somewhere global. 379 */ 380#define VGA_WIDTH 640 381#define VGA_HEIGHT 480 382 383#endif /* _MCAM_CORE_H */ 384