Lines Matching refs:lane
669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
675 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
689 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
700 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
702 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
710 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
712 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
955 int lane; in xgene_phy_sata_cfg_lanes() local
957 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
958 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
961 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
965 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
968 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
971 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
972 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
973 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
977 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
981 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
984 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
986 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
989 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
992 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
996 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
998 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
999 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
1002 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1004 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
1005 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1006 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
1009 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
1011 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1012 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1017 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1020 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1023 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1026 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1032 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1035 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1037 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1040 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1044 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1047 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1050 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1052 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1055 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1058 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1062 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1064 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1066 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1071 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1075 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1081 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1085 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1091 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1095 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1098 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1100 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1102 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1104 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1106 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1107 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1109 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1110 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1112 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1114 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1116 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1118 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1120 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1122 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1132 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1140 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1354 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal() argument
1382 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1389 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1398 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1405 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1409 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1410 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1411 serdes_clrbits(ctx, lane, RXTX_REG4, in xgene_phy_force_lat_summer_cal()
1413 serdes_clrbits(ctx, lane, RXTX_REG7, in xgene_phy_force_lat_summer_cal()
1416 serdes_wr(ctx, lane, serdes_reg[i].reg, in xgene_phy_force_lat_summer_cal()
1420 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd() argument
1423 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1426 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1434 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val() argument
1449 lane); in xgene_phy_gen_avg_val()
1452 serdes_setbits(ctx, lane, RXTX_REG12, in xgene_phy_gen_avg_val()
1455 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1457 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1468 xgene_phy_force_lat_summer_cal(ctx, lane); in xgene_phy_gen_avg_val()
1470 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1475 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1480 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1484 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1488 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1518 xgene_phy_reset_rxd(ctx, lane); in xgene_phy_gen_avg_val()
1522 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1527 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1529 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1534 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1536 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1541 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1543 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1548 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1551 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1554 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1570 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1572 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1575 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1578 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1581 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1583 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()
1585 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1587 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()