Searched refs:OP (Results 1 - 129 of 129) sorted by relevance

/linux-4.1.27/drivers/infiniband/hw/qib/
H A Dqib_uc.c38 #define OP(x) IB_OPCODE_UC_##x macro
109 qp->s_state = OP(SEND_FIRST); qib_make_uc_req()
114 qp->s_state = OP(SEND_ONLY); qib_make_uc_req()
117 OP(SEND_ONLY_WITH_IMMEDIATE); qib_make_uc_req()
138 qp->s_state = OP(RDMA_WRITE_FIRST); qib_make_uc_req()
143 qp->s_state = OP(RDMA_WRITE_ONLY); qib_make_uc_req()
146 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); qib_make_uc_req()
163 case OP(SEND_FIRST): qib_make_uc_req()
164 qp->s_state = OP(SEND_MIDDLE); qib_make_uc_req()
166 case OP(SEND_MIDDLE): qib_make_uc_req()
173 qp->s_state = OP(SEND_LAST); qib_make_uc_req()
175 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE); qib_make_uc_req()
187 case OP(RDMA_WRITE_FIRST): qib_make_uc_req()
188 qp->s_state = OP(RDMA_WRITE_MIDDLE); qib_make_uc_req()
190 case OP(RDMA_WRITE_MIDDLE): qib_make_uc_req()
197 qp->s_state = OP(RDMA_WRITE_LAST); qib_make_uc_req()
200 OP(RDMA_WRITE_LAST_WITH_IMMEDIATE); qib_make_uc_req()
279 if (qp->r_state == OP(SEND_FIRST) || qib_uc_rcv()
280 qp->r_state == OP(SEND_MIDDLE)) { qib_uc_rcv()
285 qp->r_state = OP(SEND_LAST); qib_uc_rcv()
287 case OP(SEND_FIRST): qib_uc_rcv()
288 case OP(SEND_ONLY): qib_uc_rcv()
289 case OP(SEND_ONLY_WITH_IMMEDIATE): qib_uc_rcv()
292 case OP(RDMA_WRITE_FIRST): qib_uc_rcv()
293 case OP(RDMA_WRITE_ONLY): qib_uc_rcv()
294 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): qib_uc_rcv()
304 case OP(SEND_FIRST): qib_uc_rcv()
305 case OP(SEND_MIDDLE): qib_uc_rcv()
306 if (opcode == OP(SEND_MIDDLE) || qib_uc_rcv()
307 opcode == OP(SEND_LAST) || qib_uc_rcv()
308 opcode == OP(SEND_LAST_WITH_IMMEDIATE)) qib_uc_rcv()
312 case OP(RDMA_WRITE_FIRST): qib_uc_rcv()
313 case OP(RDMA_WRITE_MIDDLE): qib_uc_rcv()
314 if (opcode == OP(RDMA_WRITE_MIDDLE) || qib_uc_rcv()
315 opcode == OP(RDMA_WRITE_LAST) || qib_uc_rcv()
316 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) qib_uc_rcv()
321 if (opcode == OP(SEND_FIRST) || qib_uc_rcv()
322 opcode == OP(SEND_ONLY) || qib_uc_rcv()
323 opcode == OP(SEND_ONLY_WITH_IMMEDIATE) || qib_uc_rcv()
324 opcode == OP(RDMA_WRITE_FIRST) || qib_uc_rcv()
325 opcode == OP(RDMA_WRITE_ONLY) || qib_uc_rcv()
326 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) qib_uc_rcv()
345 case OP(SEND_FIRST): qib_uc_rcv()
346 case OP(SEND_ONLY): qib_uc_rcv()
347 case OP(SEND_ONLY_WITH_IMMEDIATE): qib_uc_rcv()
364 if (opcode == OP(SEND_ONLY)) qib_uc_rcv()
366 else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE)) qib_uc_rcv()
369 case OP(SEND_MIDDLE): qib_uc_rcv()
379 case OP(SEND_LAST_WITH_IMMEDIATE): qib_uc_rcv()
385 case OP(SEND_LAST): qib_uc_rcv()
422 case OP(RDMA_WRITE_FIRST): OP() function
423 case OP(RDMA_WRITE_ONLY): OP()
424 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): /* consume RWQE */ OP()
453 if (opcode == OP(RDMA_WRITE_ONLY))
455 else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
460 case OP(RDMA_WRITE_MIDDLE):
470 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
501 case OP(RDMA_WRITE_LAST):
H A Dqib_rc.c39 #define OP(x) IB_OPCODE_RC_##x macro
94 case OP(RDMA_READ_RESPONSE_LAST): qib_make_rc_ack()
95 case OP(RDMA_READ_RESPONSE_ONLY): qib_make_rc_ack()
102 case OP(ATOMIC_ACKNOWLEDGE): qib_make_rc_ack()
111 case OP(SEND_ONLY): OP() function
112 case OP(ACKNOWLEDGE): OP()
121 if (e->opcode == OP(RDMA_READ_REQUEST)) {
142 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
144 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
155 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
168 case OP(RDMA_READ_RESPONSE_FIRST):
169 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
171 case OP(RDMA_READ_RESPONSE_MIDDLE):
182 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
198 qp->s_ack_state = OP(SEND_ONLY);
210 bth0 = OP(ACKNOWLEDGE) << 24;
220 qp->s_ack_state = OP(ACKNOWLEDGE);
346 qp->s_state = OP(SEND_FIRST); qib_make_rc_req()
351 qp->s_state = OP(SEND_ONLY); qib_make_rc_req()
353 qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE); qib_make_rc_req()
385 qp->s_state = OP(RDMA_WRITE_FIRST); qib_make_rc_req()
390 qp->s_state = OP(RDMA_WRITE_ONLY); qib_make_rc_req()
393 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); qib_make_rc_req()
432 qp->s_state = OP(RDMA_READ_REQUEST); qib_make_rc_req()
459 qp->s_state = OP(COMPARE_SWAP); qib_make_rc_req()
465 qp->s_state = OP(FETCH_ADD); qib_make_rc_req()
506 case OP(RDMA_READ_RESPONSE_FIRST): qib_make_rc_req()
518 case OP(SEND_FIRST): qib_make_rc_req()
519 qp->s_state = OP(SEND_MIDDLE); qib_make_rc_req()
521 case OP(SEND_MIDDLE): qib_make_rc_req()
532 qp->s_state = OP(SEND_LAST); qib_make_rc_req()
534 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE); qib_make_rc_req()
547 case OP(RDMA_READ_RESPONSE_LAST): qib_make_rc_req()
559 case OP(RDMA_WRITE_FIRST): qib_make_rc_req()
560 qp->s_state = OP(RDMA_WRITE_MIDDLE); qib_make_rc_req()
562 case OP(RDMA_WRITE_MIDDLE): qib_make_rc_req()
573 qp->s_state = OP(RDMA_WRITE_LAST); qib_make_rc_req()
575 qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE); qib_make_rc_req()
588 case OP(RDMA_READ_RESPONSE_MIDDLE): qib_make_rc_req()
604 qp->s_state = OP(RDMA_READ_REQUEST); qib_make_rc_req()
685 bth0 = qib_get_pkey(ibp, qp->s_pkey_index) | (OP(ACKNOWLEDGE) << 24); qib_send_rc_ack()
796 qp->s_state = OP(SEND_LAST); reset_psn()
819 qp->s_state = OP(SEND_LAST); reset_psn()
833 qp->s_state = OP(RDMA_READ_RESPONSE_FIRST); reset_psn()
838 qp->s_state = OP(RDMA_READ_RESPONSE_LAST); reset_psn()
842 qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE); reset_psn()
850 qp->s_state = OP(SEND_LAST); reset_psn()
988 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) && qib_rc_send_complete()
989 opcode <= OP(ATOMIC_ACKNOWLEDGE)) { qib_rc_send_complete()
1103 qp->s_state = OP(SEND_LAST); do_rc_completion()
1167 opcode == OP(RDMA_READ_RESPONSE_ONLY) && do_rc_ack()
1182 (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) || do_rc_ack()
1185 (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0))) { do_rc_ack()
1246 qp->s_state = OP(SEND_LAST); do_rc_ack()
1414 if (opcode != OP(RDMA_READ_RESPONSE_MIDDLE)) { qib_rc_rcv_resp()
1449 if (diff == 0 && opcode == OP(ACKNOWLEDGE)) { qib_rc_rcv_resp()
1473 case OP(ACKNOWLEDGE): qib_rc_rcv_resp()
1474 case OP(ATOMIC_ACKNOWLEDGE): qib_rc_rcv_resp()
1475 case OP(RDMA_READ_RESPONSE_FIRST): qib_rc_rcv_resp()
1477 if (opcode == OP(ATOMIC_ACKNOWLEDGE)) { qib_rc_rcv_resp()
1485 opcode != OP(RDMA_READ_RESPONSE_FIRST)) qib_rc_rcv_resp()
1500 case OP(RDMA_READ_RESPONSE_MIDDLE): qib_rc_rcv_resp()
1523 if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE)) qib_rc_rcv_resp()
1536 case OP(RDMA_READ_RESPONSE_ONLY): qib_rc_rcv_resp()
1559 case OP(RDMA_READ_RESPONSE_LAST): qib_rc_rcv_resp()
1582 OP(RDMA_READ_RESPONSE_LAST), 0, rcd); qib_rc_rcv_resp()
1707 case OP(RDMA_READ_REQUEST): { OP() function
1716 if (!e || e->opcode != OP(RDMA_READ_REQUEST)) OP()
1757 case OP(COMPARE_SWAP): OP() function
1758 case OP(FETCH_ADD): { OP()
1805 qp->s_ack_state = OP(ACKNOWLEDGE);
1846 qp->s_ack_state = OP(ACKNOWLEDGE); qib_update_ack_queue()
1900 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) && qib_rc_rcv()
1901 opcode <= OP(ATOMIC_ACKNOWLEDGE)) { qib_rc_rcv()
1917 case OP(SEND_FIRST): qib_rc_rcv()
1918 case OP(SEND_MIDDLE): qib_rc_rcv()
1919 if (opcode == OP(SEND_MIDDLE) || qib_rc_rcv()
1920 opcode == OP(SEND_LAST) || qib_rc_rcv()
1921 opcode == OP(SEND_LAST_WITH_IMMEDIATE)) qib_rc_rcv()
1925 case OP(RDMA_WRITE_FIRST): qib_rc_rcv()
1926 case OP(RDMA_WRITE_MIDDLE): qib_rc_rcv()
1927 if (opcode == OP(RDMA_WRITE_MIDDLE) || qib_rc_rcv()
1928 opcode == OP(RDMA_WRITE_LAST) || qib_rc_rcv()
1929 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) qib_rc_rcv()
1934 if (opcode == OP(SEND_MIDDLE) || qib_rc_rcv()
1935 opcode == OP(SEND_LAST) || qib_rc_rcv()
1936 opcode == OP(SEND_LAST_WITH_IMMEDIATE) || qib_rc_rcv()
1937 opcode == OP(RDMA_WRITE_MIDDLE) || qib_rc_rcv()
1938 opcode == OP(RDMA_WRITE_LAST) || qib_rc_rcv()
1939 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) qib_rc_rcv()
1963 case OP(SEND_FIRST): qib_rc_rcv()
1971 case OP(SEND_MIDDLE): qib_rc_rcv()
1972 case OP(RDMA_WRITE_MIDDLE): qib_rc_rcv()
1983 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE): qib_rc_rcv()
1992 case OP(SEND_ONLY): qib_rc_rcv()
1993 case OP(SEND_ONLY_WITH_IMMEDIATE): qib_rc_rcv()
2000 if (opcode == OP(SEND_ONLY)) qib_rc_rcv()
2003 case OP(SEND_LAST_WITH_IMMEDIATE): qib_rc_rcv()
2009 case OP(SEND_LAST): qib_rc_rcv()
2010 case OP(RDMA_WRITE_LAST): qib_rc_rcv()
2033 if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) || qib_rc_rcv()
2034 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) qib_rc_rcv()
2053 case OP(RDMA_WRITE_FIRST): qib_rc_rcv()
2054 case OP(RDMA_WRITE_ONLY): qib_rc_rcv()
2055 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): qib_rc_rcv()
2082 if (opcode == OP(RDMA_WRITE_FIRST)) qib_rc_rcv()
2084 else if (opcode == OP(RDMA_WRITE_ONLY)) qib_rc_rcv()
2096 case OP(RDMA_READ_REQUEST): { OP() function
2114 if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) { OP()
2164 case OP(COMPARE_SWAP): OP() function
2165 case OP(FETCH_ADD): { OP()
2186 if (e->opcode == OP(RDMA_READ_REQUEST) && e->rdma_sge.mr) { OP()
2201 /* Perform atomic OP and save result. */ OP()
2204 e->atomic_data = (opcode == OP(FETCH_ADD)) ? OP()
H A Dqib_ruc.c496 /* Perform atomic OP and save result. */ qib_ruc_loopback()
/linux-4.1.27/drivers/infiniband/hw/ipath/
H A Dipath_uc.c38 #define OP(x) IB_OPCODE_UC_##x macro
106 qp->s_state = OP(SEND_FIRST); ipath_make_uc_req()
111 qp->s_state = OP(SEND_ONLY); ipath_make_uc_req()
114 OP(SEND_ONLY_WITH_IMMEDIATE); ipath_make_uc_req()
135 qp->s_state = OP(RDMA_WRITE_FIRST); ipath_make_uc_req()
140 qp->s_state = OP(RDMA_WRITE_ONLY); ipath_make_uc_req()
143 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); ipath_make_uc_req()
160 case OP(SEND_FIRST): ipath_make_uc_req()
161 qp->s_state = OP(SEND_MIDDLE); ipath_make_uc_req()
163 case OP(SEND_MIDDLE): ipath_make_uc_req()
170 qp->s_state = OP(SEND_LAST); ipath_make_uc_req()
172 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE); ipath_make_uc_req()
184 case OP(RDMA_WRITE_FIRST): ipath_make_uc_req()
185 qp->s_state = OP(RDMA_WRITE_MIDDLE); ipath_make_uc_req()
187 case OP(RDMA_WRITE_MIDDLE): ipath_make_uc_req()
194 qp->s_state = OP(RDMA_WRITE_LAST); ipath_make_uc_req()
197 OP(RDMA_WRITE_LAST_WITH_IMMEDIATE); ipath_make_uc_req()
295 qp->r_state = OP(SEND_LAST); ipath_uc_rcv()
297 case OP(SEND_FIRST): ipath_uc_rcv()
298 case OP(SEND_ONLY): ipath_uc_rcv()
299 case OP(SEND_ONLY_WITH_IMMEDIATE): ipath_uc_rcv()
302 case OP(RDMA_WRITE_FIRST): ipath_uc_rcv()
303 case OP(RDMA_WRITE_ONLY): ipath_uc_rcv()
304 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): ipath_uc_rcv()
315 case OP(SEND_FIRST): ipath_uc_rcv()
316 case OP(SEND_MIDDLE): ipath_uc_rcv()
317 if (opcode == OP(SEND_MIDDLE) || ipath_uc_rcv()
318 opcode == OP(SEND_LAST) || ipath_uc_rcv()
319 opcode == OP(SEND_LAST_WITH_IMMEDIATE)) ipath_uc_rcv()
323 case OP(RDMA_WRITE_FIRST): ipath_uc_rcv()
324 case OP(RDMA_WRITE_MIDDLE): ipath_uc_rcv()
325 if (opcode == OP(RDMA_WRITE_MIDDLE) || ipath_uc_rcv()
326 opcode == OP(RDMA_WRITE_LAST) || ipath_uc_rcv()
327 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) ipath_uc_rcv()
332 if (opcode == OP(SEND_FIRST) || ipath_uc_rcv()
333 opcode == OP(SEND_ONLY) || ipath_uc_rcv()
334 opcode == OP(SEND_ONLY_WITH_IMMEDIATE) || ipath_uc_rcv()
335 opcode == OP(RDMA_WRITE_FIRST) || ipath_uc_rcv()
336 opcode == OP(RDMA_WRITE_ONLY) || ipath_uc_rcv()
337 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) ipath_uc_rcv()
344 case OP(SEND_FIRST): OP() function
345 case OP(SEND_ONLY): OP()
346 case OP(SEND_ONLY_WITH_IMMEDIATE): OP()
358 if (opcode == OP(SEND_ONLY))
360 else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))
363 case OP(SEND_MIDDLE): OP() function
379 case OP(SEND_LAST_WITH_IMMEDIATE): OP() function
391 case OP(SEND_LAST):
425 case OP(RDMA_WRITE_FIRST):
426 case OP(RDMA_WRITE_ONLY):
427 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): /* consume RWQE */
464 if (opcode == OP(RDMA_WRITE_ONLY))
466 else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
469 case OP(RDMA_WRITE_MIDDLE): OP() function
483 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE): OP() function
519 case OP(RDMA_WRITE_LAST):
H A Dipath_rc.c40 #define OP(x) IB_OPCODE_RC_##x macro
103 case OP(RDMA_READ_RESPONSE_LAST): ipath_make_rc_ack()
104 case OP(RDMA_READ_RESPONSE_ONLY): ipath_make_rc_ack()
105 case OP(ATOMIC_ACKNOWLEDGE): ipath_make_rc_ack()
114 case OP(SEND_ONLY): OP() function
115 case OP(ACKNOWLEDGE): OP()
120 qp->s_ack_state = OP(ACKNOWLEDGE); OP()
125 if (e->opcode == OP(RDMA_READ_REQUEST)) {
132 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
134 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
145 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
158 case OP(RDMA_READ_RESPONSE_FIRST):
159 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
161 case OP(RDMA_READ_RESPONSE_MIDDLE):
168 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
183 qp->s_ack_state = OP(SEND_ONLY);
195 bth0 = OP(ACKNOWLEDGE) << 24;
241 qp->s_ack_state != OP(ACKNOWLEDGE)) && ipath_make_rc_req()
322 qp->s_state = OP(SEND_FIRST); ipath_make_rc_req()
327 qp->s_state = OP(SEND_ONLY); ipath_make_rc_req()
329 qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE); ipath_make_rc_req()
361 qp->s_state = OP(RDMA_WRITE_FIRST); ipath_make_rc_req()
366 qp->s_state = OP(RDMA_WRITE_ONLY); ipath_make_rc_req()
369 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE); ipath_make_rc_req()
408 qp->s_state = OP(RDMA_READ_REQUEST); ipath_make_rc_req()
434 qp->s_state = OP(COMPARE_SWAP); ipath_make_rc_req()
440 qp->s_state = OP(FETCH_ADD); ipath_make_rc_req()
490 case OP(RDMA_READ_RESPONSE_FIRST): ipath_make_rc_req()
497 case OP(SEND_FIRST): ipath_make_rc_req()
498 qp->s_state = OP(SEND_MIDDLE); ipath_make_rc_req()
500 case OP(SEND_MIDDLE): ipath_make_rc_req()
511 qp->s_state = OP(SEND_LAST); ipath_make_rc_req()
513 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE); ipath_make_rc_req()
526 case OP(RDMA_READ_RESPONSE_LAST): ipath_make_rc_req()
533 case OP(RDMA_WRITE_FIRST): ipath_make_rc_req()
534 qp->s_state = OP(RDMA_WRITE_MIDDLE); ipath_make_rc_req()
536 case OP(RDMA_WRITE_MIDDLE): ipath_make_rc_req()
547 qp->s_state = OP(RDMA_WRITE_LAST); ipath_make_rc_req()
549 qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE); ipath_make_rc_req()
562 case OP(RDMA_READ_RESPONSE_MIDDLE): ipath_make_rc_req()
574 qp->s_state = OP(RDMA_READ_REQUEST); ipath_make_rc_req()
629 qp->s_ack_state != OP(ACKNOWLEDGE)) send_rc_ack()
666 (OP(ACKNOWLEDGE) << 24) | (1 << 22); send_rc_ack()
737 qp->s_state = OP(SEND_LAST); reset_psn()
760 qp->s_state = OP(SEND_LAST); reset_psn()
774 qp->s_state = OP(RDMA_READ_RESPONSE_FIRST); reset_psn()
779 qp->s_state = OP(RDMA_READ_RESPONSE_LAST); reset_psn()
783 qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE); reset_psn()
791 qp->s_state = OP(SEND_LAST); reset_psn()
902 opcode == OP(RDMA_READ_RESPONSE_ONLY) && do_rc_ack()
917 (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) || do_rc_ack()
920 (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0))) { do_rc_ack()
975 qp->s_state = OP(SEND_LAST); do_rc_ack()
1008 qp->s_state = OP(SEND_LAST); do_rc_ack()
1147 if (diff == 0 && opcode == OP(ACKNOWLEDGE)) { ipath_rc_rcv_resp()
1166 case OP(ACKNOWLEDGE): ipath_rc_rcv_resp()
1167 case OP(ATOMIC_ACKNOWLEDGE): ipath_rc_rcv_resp()
1168 case OP(RDMA_READ_RESPONSE_FIRST): ipath_rc_rcv_resp()
1175 if (opcode == OP(ATOMIC_ACKNOWLEDGE)) { ipath_rc_rcv_resp()
1186 opcode != OP(RDMA_READ_RESPONSE_FIRST)) ipath_rc_rcv_resp()
1202 case OP(RDMA_READ_RESPONSE_MIDDLE): OP() function
1227 if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
1240 case OP(RDMA_READ_RESPONSE_ONLY):
1266 case OP(RDMA_READ_RESPONSE_LAST): OP() function
1299 OP(RDMA_READ_RESPONSE_LAST), 0);
1410 case OP(RDMA_READ_REQUEST): { OP() function
1420 if (!e || e->opcode != OP(RDMA_READ_REQUEST) || old_req) OP()
1460 qp->s_ack_state = OP(ACKNOWLEDGE); OP()
1465 case OP(COMPARE_SWAP): OP() function
1466 case OP(FETCH_ADD): { OP()
1474 qp->s_ack_state = OP(ACKNOWLEDGE); OP()
1499 qp->s_ack_state == OP(ACKNOWLEDGE)) {
1509 qp->s_ack_state = OP(ACKNOWLEDGE);
1553 qp->s_ack_state = OP(ACKNOWLEDGE); ipath_update_ack_queue()
1618 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) && ipath_rc_rcv()
1619 opcode <= OP(ATOMIC_ACKNOWLEDGE)) { ipath_rc_rcv()
1636 case OP(SEND_FIRST): ipath_rc_rcv()
1637 case OP(SEND_MIDDLE): ipath_rc_rcv()
1638 if (opcode == OP(SEND_MIDDLE) || ipath_rc_rcv()
1639 opcode == OP(SEND_LAST) || ipath_rc_rcv()
1640 opcode == OP(SEND_LAST_WITH_IMMEDIATE)) ipath_rc_rcv()
1644 case OP(RDMA_WRITE_FIRST): ipath_rc_rcv()
1645 case OP(RDMA_WRITE_MIDDLE): ipath_rc_rcv()
1646 if (opcode == OP(RDMA_WRITE_MIDDLE) || ipath_rc_rcv()
1647 opcode == OP(RDMA_WRITE_LAST) || ipath_rc_rcv()
1648 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) ipath_rc_rcv()
1653 if (opcode == OP(SEND_MIDDLE) || ipath_rc_rcv()
1654 opcode == OP(SEND_LAST) || ipath_rc_rcv()
1655 opcode == OP(SEND_LAST_WITH_IMMEDIATE) || ipath_rc_rcv()
1656 opcode == OP(RDMA_WRITE_MIDDLE) || ipath_rc_rcv()
1657 opcode == OP(RDMA_WRITE_LAST) || ipath_rc_rcv()
1658 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE)) ipath_rc_rcv()
1672 case OP(SEND_FIRST): ipath_rc_rcv()
1677 case OP(SEND_MIDDLE): ipath_rc_rcv()
1678 case OP(RDMA_WRITE_MIDDLE): ipath_rc_rcv()
1689 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE): ipath_rc_rcv()
1695 case OP(SEND_ONLY): ipath_rc_rcv()
1696 case OP(SEND_ONLY_WITH_IMMEDIATE): ipath_rc_rcv()
1700 if (opcode == OP(SEND_ONLY)) ipath_rc_rcv()
1703 case OP(SEND_LAST_WITH_IMMEDIATE): OP() function
1715 case OP(SEND_LAST):
1716 case OP(RDMA_WRITE_LAST):
1735 if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
1736 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
1750 case OP(RDMA_WRITE_FIRST):
1751 case OP(RDMA_WRITE_ONLY):
1752 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
1785 if (opcode == OP(RDMA_WRITE_FIRST))
1787 else if (opcode == OP(RDMA_WRITE_ONLY))
1793 case OP(RDMA_READ_REQUEST): { OP() function
1866 case OP(COMPARE_SWAP): OP() function
1867 case OP(FETCH_ADD): { OP()
1905 /* Perform atomic OP and save result. */ OP()
1909 e->atomic_data = (opcode == OP(FETCH_ADD)) ? OP()
H A Dipath_ruc.c384 /* Perform atomic OP and save result. */ ipath_ruc_loopback()
/linux-4.1.27/drivers/cpufreq/
H A Dspeedstep-centrino.c83 #define OP(mhz, mv) \ macro
99 OP(600, 844),
100 OP(800, 988),
101 OP(900, 1004),
108 OP(600, 844),
109 OP(800, 972),
110 OP(900, 988),
111 OP(1000, 1004),
118 OP( 600, 956),
119 OP( 800, 1020),
120 OP( 900, 1100),
121 OP(1000, 1164),
122 OP(1100, 1180),
130 OP( 600, 956),
131 OP( 800, 1004),
132 OP( 900, 1020),
133 OP(1000, 1100),
134 OP(1100, 1164),
135 OP(1200, 1180),
142 OP( 600, 956),
143 OP( 800, 1260),
144 OP(1000, 1292),
145 OP(1200, 1356),
146 OP(1300, 1388),
153 OP( 600, 956),
154 OP( 800, 1180),
155 OP(1000, 1308),
156 OP(1200, 1436),
157 OP(1400, 1484),
164 OP( 600, 956),
165 OP( 800, 1116),
166 OP(1000, 1228),
167 OP(1200, 1356),
168 OP(1400, 1452),
169 OP(1500, 1484),
176 OP( 600, 956),
177 OP( 800, 1036),
178 OP(1000, 1164),
179 OP(1200, 1276),
180 OP(1400, 1420),
181 OP(1600, 1484),
188 OP( 600, 956),
189 OP( 800, 1004),
190 OP(1000, 1116),
191 OP(1200, 1228),
192 OP(1400, 1308),
193 OP(1700, 1484),
196 #undef OP macro
H A Dpxa3xx-cpufreq.c55 #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ macro
71 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
72 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
73 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
74 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
79 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
80 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
81 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
82 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
83 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
/linux-4.1.27/sound/oss/
H A Dopl3_hw.h16 * a bit mask defining which voices are used as 4 OP voices.
22 * A 4 OP voice can be created by setting the corresponding
26 * first voice on the right side to the 4 OP mode. The fourth
29 * If a voice is set to the 2 OP mode, it works like 2 OP modes
32 * even be left unconnected. This works with 4 OP voices also.
35 * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
99 #define TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */
141 * to the stereo channels. For 4 OP voices this bit is
145 * For 4 OP voices the connection bit is used in the
149 #define FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */
152 * In the 4 OP mode there is four possible configurations how the
153 * operators can be connected together (in 2 OP modes there is just
154 * AM or FM). The 4 OP connection mode is defined by the rightmost
195 unsigned char voice_mode; /* 0=unavailable, 2=2 OP, 4=4 OP */
201 * There is 18 possible 2 OP voices
203 * The first OP is the modulator and 2nd is the carrier.
206 * with another voice to a 4 OP voice. For example voice 0
208 * used as operators 3 and 4 of the new 4 OP voice.
209 * In this case the 2 OP voice number 0 is the 'first half' and
H A Dopl3.c94 devc->cmask = 0x3f; /* Connect all possible 4 OP voice operators */ enter_4op_mode()
409 * 4 OP voice set_voice_volume()
419 * The connection method for 4 OP devc->voc is defined by the rightmost set_voice_volume()
532 * Just 2 OP patch opl3_start_note()
599 * If the voice is a 4 OP one, initialize the operators 3 and 4 also opl3_start_note()
723 * The original 2-OP synth requires a quite long delay after writing to a opl3_command()
799 * Just 2 OP mode opl3_open()
1012 devc->nr_voice != 12) /* Not in 4 OP mode */ opl3_alloc_voice()
1014 else if (devc->nr_voice == 12) /* 4 OP mode */ opl3_alloc_voice()
1026 if (devc->nr_voice == 12) /* 4 OP mode. Use the '2 OP only' operators first */ opl3_alloc_voice()
/linux-4.1.27/samples/bpf/
H A Dlibbpf.h23 #define BPF_ALU64_REG(OP, DST, SRC) \
25 .code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \
31 #define BPF_ALU32_REG(OP, DST, SRC) \
33 .code = BPF_ALU | BPF_OP(OP) | BPF_X, \
41 #define BPF_ALU64_IMM(OP, DST, IMM) \
43 .code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
49 #define BPF_ALU32_IMM(OP, DST, IMM) \
51 .code = BPF_ALU | BPF_OP(OP) | BPF_K, \
146 #define BPF_JMP_REG(OP, DST, SRC, OFF) \
148 .code = BPF_JMP | BPF_OP(OP) | BPF_X, \
156 #define BPF_JMP_IMM(OP, DST, IMM, OFF) \
158 .code = BPF_JMP | BPF_OP(OP) | BPF_K, \
/linux-4.1.27/crypto/
H A Dseed.c315 #define OP(X1, X2, X3, X4, rbase) \ macro
381 OP(x1, x2, x3, x4, 0); seed_encrypt()
382 OP(x3, x4, x1, x2, 2); seed_encrypt()
383 OP(x1, x2, x3, x4, 4); seed_encrypt()
384 OP(x3, x4, x1, x2, 6); seed_encrypt()
385 OP(x1, x2, x3, x4, 8); seed_encrypt()
386 OP(x3, x4, x1, x2, 10); seed_encrypt()
387 OP(x1, x2, x3, x4, 12); seed_encrypt()
388 OP(x3, x4, x1, x2, 14); seed_encrypt()
389 OP(x1, x2, x3, x4, 16); seed_encrypt()
390 OP(x3, x4, x1, x2, 18); seed_encrypt()
391 OP(x1, x2, x3, x4, 20); seed_encrypt()
392 OP(x3, x4, x1, x2, 22); seed_encrypt()
393 OP(x1, x2, x3, x4, 24); seed_encrypt()
394 OP(x3, x4, x1, x2, 26); seed_encrypt()
395 OP(x1, x2, x3, x4, 28); seed_encrypt()
396 OP(x3, x4, x1, x2, 30); seed_encrypt()
419 OP(x1, x2, x3, x4, 30); seed_decrypt()
420 OP(x3, x4, x1, x2, 28); seed_decrypt()
421 OP(x1, x2, x3, x4, 26); seed_decrypt()
422 OP(x3, x4, x1, x2, 24); seed_decrypt()
423 OP(x1, x2, x3, x4, 22); seed_decrypt()
424 OP(x3, x4, x1, x2, 20); seed_decrypt()
425 OP(x1, x2, x3, x4, 18); seed_decrypt()
426 OP(x3, x4, x1, x2, 16); seed_decrypt()
427 OP(x1, x2, x3, x4, 14); seed_decrypt()
428 OP(x3, x4, x1, x2, 12); seed_decrypt()
429 OP(x1, x2, x3, x4, 10); seed_decrypt()
430 OP(x3, x4, x1, x2, 8); seed_decrypt()
431 OP(x1, x2, x3, x4, 6); seed_decrypt()
432 OP(x3, x4, x1, x2, 4); seed_decrypt()
433 OP(x1, x2, x3, x4, 2); seed_decrypt()
434 OP(x3, x4, x1, x2, 0); seed_decrypt()
/linux-4.1.27/sound/pci/emu10k1/
H A Demufx.c508 #define OP(icode, ptr, op, r, a, x, y) \ macro
1768 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); _volume()
1769 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); _volume()
1770 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001); _volume()
1771 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); _volume()
1775 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); _volume_add()
1776 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); _volume_add()
1777 OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001); _volume_add()
1778 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); _volume_add()
1779 OP(icode, ptr, iMAC0, dst, dst, src, vol); _volume_add()
1783 OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff); _volume_out()
1784 OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); _volume_out()
1785 OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000); _volume_out()
1786 OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001); _volume_out()
1787 OP(icode, ptr, iMAC0, dst, C_00000000, src, vol); _volume_out()
1801 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1807 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1872 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004); _snd_emu10k1_init_efx()
1873 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004); _snd_emu10k1_init_efx()
1874 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004); _snd_emu10k1_init_efx()
1875 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004); _snd_emu10k1_init_efx()
1876 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004); _snd_emu10k1_init_efx()
1877 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004); _snd_emu10k1_init_efx()
1878 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004); _snd_emu10k1_init_efx()
1879 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004); _snd_emu10k1_init_efx()
1880 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ _snd_emu10k1_init_efx()
1881 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ _snd_emu10k1_init_efx()
1882 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004); _snd_emu10k1_init_efx()
1883 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004); _snd_emu10k1_init_efx()
1914 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); _snd_emu10k1_init_efx()
1915 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); _snd_emu10k1_init_efx()
1917 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); _snd_emu10k1_init_efx()
1918 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); _snd_emu10k1_init_efx()
1920 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); _snd_emu10k1_init_efx()
1921 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); _snd_emu10k1_init_efx()
1922 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); _snd_emu10k1_init_efx()
1923 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); _snd_emu10k1_init_efx()
1925 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); _snd_emu10k1_init_efx()
1926 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); _snd_emu10k1_init_efx()
1927 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); _snd_emu10k1_init_efx()
1928 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); _snd_emu10k1_init_efx()
1930 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); _snd_emu10k1_init_efx()
1931 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); _snd_emu10k1_init_efx()
1932 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); _snd_emu10k1_init_efx()
1933 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); _snd_emu10k1_init_efx()
1934 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); _snd_emu10k1_init_efx()
1936 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); _snd_emu10k1_init_efx()
1937 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); _snd_emu10k1_init_efx()
1938 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); _snd_emu10k1_init_efx()
1939 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); _snd_emu10k1_init_efx()
1940 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); _snd_emu10k1_init_efx()
1942 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); _snd_emu10k1_init_efx()
1943 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); _snd_emu10k1_init_efx()
1944 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); _snd_emu10k1_init_efx()
1945 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); _snd_emu10k1_init_efx()
1946 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); _snd_emu10k1_init_efx()
1948 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); _snd_emu10k1_init_efx()
1949 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); _snd_emu10k1_init_efx()
1950 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); _snd_emu10k1_init_efx()
1951 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); _snd_emu10k1_init_efx()
1952 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); _snd_emu10k1_init_efx()
1954 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); _snd_emu10k1_init_efx()
1955 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); _snd_emu10k1_init_efx()
1957 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); _snd_emu10k1_init_efx()
1958 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); _snd_emu10k1_init_efx()
1976 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); _snd_emu10k1_init_efx()
1977 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002); _snd_emu10k1_init_efx()
2168 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */ _snd_emu10k1_init_efx()
2169 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */ _snd_emu10k1_init_efx()
2170 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */ _snd_emu10k1_init_efx()
2171 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */ _snd_emu10k1_init_efx()
2172 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */ _snd_emu10k1_init_efx()
2173 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */ _snd_emu10k1_init_efx()
2213 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); _snd_emu10k1_init_efx()
2214 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); _snd_emu10k1_init_efx()
2215 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); _snd_emu10k1_init_efx()
2216 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); _snd_emu10k1_init_efx()
2217 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); _snd_emu10k1_init_efx()
2218 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); _snd_emu10k1_init_efx()
2220 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); _snd_emu10k1_init_efx()
2221 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); _snd_emu10k1_init_efx()
2222 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); _snd_emu10k1_init_efx()
2223 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); _snd_emu10k1_init_efx()
2224 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); _snd_emu10k1_init_efx()
2225 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); _snd_emu10k1_init_efx()
2227 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2242 OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); _snd_emu10k1_init_efx()
2254 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2264 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); _snd_emu10k1_init_efx()
2266 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); _snd_emu10k1_init_efx()
2281 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); _snd_emu10k1_init_efx()
2297 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2301 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2305 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2306 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2308 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2309 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2315 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2316 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2318 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2319 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2325 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2329 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); _snd_emu10k1_init_efx()
2342 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0)); _snd_emu10k1_init_efx()
2343 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1)); _snd_emu10k1_init_efx()
2344 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2)); _snd_emu10k1_init_efx()
2345 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3)); _snd_emu10k1_init_efx()
2347 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); _snd_emu10k1_init_efx()
2350 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); _snd_emu10k1_init_efx()
2367 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); _snd_emu10k1_init_efx()
H A Demuproc.c306 snd_iprintf(buffer, " OP(0x%02x, 0x%03x, 0x%03x, 0x%03x, 0x%03x) /* 0x%04x: 0x%08x%08x */\n", snd_emu10k1_proc_acode_read()
315 snd_iprintf(buffer, " OP(0x%02x, 0x%03x, 0x%03x, 0x%03x, 0x%03x) /* 0x%04x: 0x%08x%08x */\n", snd_emu10k1_proc_acode_read()
/linux-4.1.27/include/sound/
H A Dopl3.h15 * a bit mask defining which voices are used as 4 OP voices.
21 * A 4 OP voice can be created by setting the corresponding
25 * first voice on the right side to the 4 OP mode. The fourth
28 * If a voice is set to the 2 OP mode, it works like 2 OP modes
31 * even be left unconnected. This works with 4 OP voices also.
34 * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
125 #define OPL3_TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */
168 * to the stereo channels. For 4 OP voices this bit is
172 * For 4 OP voices the connection bit is used in the
176 #define OPL3_FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */
179 * In the 4 OP mode there is four possible configurations how the
180 * operators can be connected together (in 2 OP modes there is just
181 * AM or FM). The 4 OP connection mode is defined by the rightmost
/linux-4.1.27/arch/ia64/lib/
H A Didiv32.S20 # define OP mod
22 # define OP div
39 #define NAME PASTE(PASTE(__,SGN),PASTE(OP,si3))
H A Didiv64.S20 # define OP mod
22 # define OP div
37 #define NAME PASTE(PASTE(__,SGN),PASTE(OP,di3))
/linux-4.1.27/include/linux/
H A Dfilter.h50 #define BPF_ALU64_REG(OP, DST, SRC) \
52 .code = BPF_ALU64 | BPF_OP(OP) | BPF_X, \
58 #define BPF_ALU32_REG(OP, DST, SRC) \
60 .code = BPF_ALU | BPF_OP(OP) | BPF_X, \
68 #define BPF_ALU64_IMM(OP, DST, IMM) \
70 .code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
76 #define BPF_ALU32_IMM(OP, DST, IMM) \
78 .code = BPF_ALU | BPF_OP(OP) | BPF_K, \
222 #define BPF_JMP_REG(OP, DST, SRC, OFF) \
224 .code = BPF_JMP | BPF_OP(OP) | BPF_X, \
232 #define BPF_JMP_IMM(OP, DST, IMM, OFF) \
234 .code = BPF_JMP | BPF_OP(OP) | BPF_K, \
H A Dcapability.h101 #define CAP_BOP_ALL(c, a, b, OP) \
105 c.cap[__capi] = a.cap[__capi] OP b.cap[__capi]; \
109 #define CAP_UOP_ALL(c, a, OP) \
113 c.cap[__capi] = OP a.cap[__capi]; \
H A Dperf_event.h701 #define PERF_MEM_NA (PERF_MEM_S(OP, NA) |\
/linux-4.1.27/fs/cachefiles/
H A Dinternal.h325 #define ASSERTCMP(X, OP, Y) \
327 if (unlikely(!((X) OP (Y)))) { \
330 pr_err("%lx " #OP " %lx is false\n", \
345 #define ASSERTIFCMP(C, X, OP, Y) \
347 if (unlikely((C) && !((X) OP (Y)))) { \
350 pr_err("%lx " #OP " %lx is false\n", \
359 #define ASSERTCMP(X, OP, Y) do {} while (0)
361 #define ASSERTIFCMP(C, X, OP, Y) do {} while (0)
/linux-4.1.27/fs/fscache/
H A Dinternal.h426 #define ASSERTCMP(X, OP, Y) \
428 if (unlikely(!((X) OP (Y)))) { \
431 pr_err("%lx " #OP " %lx is false\n", \
446 #define ASSERTIFCMP(C, X, OP, Y) \
448 if (unlikely((C) && !((X) OP (Y)))) { \
451 pr_err("%lx " #OP " %lx is false\n", \
460 #define ASSERTCMP(X, OP, Y) do {} while (0)
462 #define ASSERTIFCMP(C, X, OP, Y) do {} while (0)
H A Doperation.c33 _enter("{OBJ%x OP%x,%u}", fscache_enqueue_operation()
88 _enter("{OBJ%x OP%x},", object->debug_id, op->debug_id); fscache_submit_exclusive_op()
156 kdebug("unexpected submission OP%x [OBJ%x %s]", fscache_report_unexpected_submission()
192 _enter("{OBJ%x OP%x},{%u}", fscache_submit_op()
301 _enter("OBJ%x OP%x}", op->object->debug_id, op->debug_id); fscache_cancel_op()
403 _enter("{OBJ%x OP%x,%d}", fscache_put_operation()
411 _debug("PUT OP"); fscache_put_operation()
486 _debug("GC DEFERRED REL OBJ%x OP%x", fscache_operation_gc()
519 _enter("{OBJ%x OP%x,%d}", fscache_op_work_func()
H A Dhistogram.c34 seq_puts(m, "JIFS SECS OBJ INST OP RUNS OBJ RUNS RETRV DLY RETRIEVLS\n"); fscache_histogram_show()
H A Dpage.c178 _enter("{OBJ%x OP%x}", object->debug_id, op->debug_id); fscache_attr_changed_op()
259 _enter("{OP%x}", op->op.debug_id); fscache_release_retrieval_op()
760 _enter("{OP%x}", _op->debug_id); fscache_release_write_op()
777 _enter("{OP%x,%d}", op->op.debug_id, atomic_read(&op->op.usage)); fscache_write_op()
/linux-4.1.27/arch/arc/kernel/
H A Ddisasm.c244 case 0: /* OP a,b,c */ disasm_instr()
248 case 1: /* OP a,b,u6 */ disasm_instr()
250 case 2: /* OP b,b,s12 */ disasm_instr()
252 case 3: /* OP.cc b,b,c/u6 */ disasm_instr()
265 case 0: /* OP a,b,c */ disasm_instr()
270 case 1: /* OP a,b,u6 */ disasm_instr()
272 case 2: /* OP b,b,s12 */ disasm_instr()
274 case 3: /* OP.cc b,b,c/u6 */ disasm_instr()
/linux-4.1.27/arch/arm64/net/
H A Dbpf_jit.h89 /* Rd = Rn OP imm12 */
133 /* Rd = Rn OP Rm */
151 /* Rd = Rn OP Rm */
170 /* Rd = Rn OP Rm */
H A Dbpf_jit_comp.c245 /* dst = dst OP src */ build_insn()
361 /* dst = dst OP imm */ build_insn()
/linux-4.1.27/arch/powerpc/xmon/
H A Dppc-opc.c1526 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1527 #define OP_MASK OP (0x3f)
1532 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1538 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1542 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1558 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1590 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1594 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1601 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1605 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1609 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1613 #define M(op, rc) (OP (op) | ((rc) & 1))
1626 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1636 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1643 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1647 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1653 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1659 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1665 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1668 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1738 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1742 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1746 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1786 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1793 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1821 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1955 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1985 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1986 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
2513 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2514 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2516 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2517 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2519 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2528 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2529 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2533 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2534 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2536 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2537 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2538 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2540 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2541 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2542 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2544 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2545 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2546 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2547 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2548 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2549 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2551 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2552 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2553 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2554 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2555 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3281 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3282 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3283 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3285 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3286 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3288 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3289 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3291 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3292 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3294 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3295 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3297 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3298 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
4546 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4547 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4549 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4550 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4552 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4554 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4556 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4557 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4559 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4560 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4562 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4564 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4566 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4568 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4570 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4572 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4574 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4576 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4578 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4579 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4581 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4582 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4584 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4586 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4588 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4590 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4592 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4594 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4596 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4598 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4600 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4602 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4604 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4606 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4729 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4731 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4733 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
1523 #define OP global() macro
/linux-4.1.27/arch/tile/include/asm/
H A Dfutex.h41 #define __futex_asm(OP) \
42 asm("1: {" #OP " %1, %3, %4; movei %0, 0 }\n" \
H A Duaccess.h136 #define __get_user_asm(OP, x, ptr, ret) \
137 asm volatile("1: {" #OP " %1, %2; movei %0, 0 }\n" \
228 #define __put_user_asm(OP, x, ptr, ret) \
229 asm volatile("1: {" #OP " %1, %2; movei %0, 0 }\n" \
/linux-4.1.27/include/uapi/sound/
H A Dasound_fm.h122 #define FM_KEY_2OP "2OP\032"
123 #define FM_KEY_4OP "4OP\032"
/linux-4.1.27/arch/sparc/include/asm/
H A Dsfp-machine_64.h59 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
H A Dsfp-machine_32.h61 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
/linux-4.1.27/arch/sh/include/asm/
H A Dsfp-machine.h57 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
/linux-4.1.27/arch/alpha/include/asm/
H A Dsfp-machine.h55 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
/linux-4.1.27/drivers/media/i2c/
H A Dsmiapp-pll.c126 * If there are no OP clocks, the VT clocks are contained in check_all_bounds()
127 * the OP clock struct. check_all_bounds()
264 /* No OP clocks --- VT clocks are used instead. */ __smiapp_pll_calculate()
409 * If there's no OP PLL at all, use the VT values smiapp_pll_calculate()
410 * instead. The OP values are ignored for the rest of smiapp_pll_calculate()
/linux-4.1.27/sound/drivers/opl3/
H A Dopl3_synth.c32 * There is 18 possible 2 OP voices
34 * The first OP is the modulator and 2nd is the carrier.
37 * with another voice to a 4 OP voice. For example voice 0
39 * used as operators 3 and 4 of the new 4 OP voice.
40 * In this case the 2 OP voice number 0 is the 'first half' and
H A Dopl3_lib.c47 * The original 2-OP synth requires a quite long delay snd_opl2_command()
/linux-4.1.27/arch/sparc/net/
H A Dbpf_jit_comp.c47 #define OP(X) ((X) << 30) macro
51 #define F1(X) OP(X)
52 #define F2(X, Y) (OP(X) | OP2(Y))
53 #define F3(X, Y) (OP(X) | OP3(Y))
163 * OP r_A, r_X, r_A
173 * OP r_A, K, r_A
179 * OP r_A, r_TMP, r_A
/linux-4.1.27/arch/nios2/kernel/
H A Dinsnemu.S89 * The instruction's OP and OPX fields identify the operation to be
93 * an OP field of 0x24.
98 * The remaining emulated instructions are R-type and have an OP field
105 * Opcode Encoding. muli is identified by its OP value. Then OPX & 0x02
109 * Instruction OP OPX OPX & 0x02
178 * r2 = OP
211 * r2 = OP
/linux-4.1.27/fs/afs/
H A Dinternal.h817 #define ASSERTCMP(X, OP, Y) \
819 if (unlikely(!((X) OP (Y)))) { \
822 printk(KERN_ERR "%lu " #OP " %lu is false\n", \
824 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
854 #define ASSERTIFCMP(C, X, OP, Y) \
856 if (unlikely((C) && !((X) OP (Y)))) { \
859 printk(KERN_ERR "%lu " #OP " %lu is false\n", \
861 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
873 #define ASSERTCMP(X, OP, Y) \
885 #define ASSERTIFCMP(C, X, OP, Y) \
H A Dcmservice.c103 _enter("{CB.OP %u}", operation_id); afs_cm_incoming_call()
/linux-4.1.27/net/rxrpc/
H A Dar-internal.h699 #define ASSERTCMP(X, OP, Y) \
701 if (unlikely(!((X) OP (Y)))) { \
704 printk(KERN_ERR "%lu " #OP " %lu is false\n", \
706 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
721 #define ASSERTIFCMP(C, X, OP, Y) \
723 if (unlikely((C) && !((X) OP (Y)))) { \
726 printk(KERN_ERR "%lu " #OP " %lu is false\n", \
728 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
740 #define ASSERTCMP(X, OP, Y) \
748 #define ASSERTIFCMP(C, X, OP, Y) \
/linux-4.1.27/arch/sh/math-emu/
H A Dmath.c76 #define CMP(OP) ({ int r; BOTH_PRmn(OP##_X,r); r; })
99 #define ARITH_X(SZ,OP,M,N) do{ \
102 FP_##OP##_##SZ(Fr, Fn, Fm); \
/linux-4.1.27/drivers/block/paride/
H A Dfit2.c34 So, we map ALT_STATUS to STATUS and NO-OP writes to the device
H A Dfit3.c14 registers. So, we map ALT_STATUS to STATUS and NO-OP writes
/linux-4.1.27/arch/s390/include/asm/
H A Dsfp-machine.h58 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
/linux-4.1.27/tools/perf/util/
H A Dstrfilter.c91 case '&': /* Exchg last OP->r with AND */ strfilter_node__new()
H A Devent.h197 (PERF_MEM_S(OP, NA) |\
H A Ddwarf-aux.c320 pr_debug("Unable to get offset:Unexpected OP %x (%zd)\n", die_get_data_member_location()
/linux-4.1.27/kernel/bpf/
H A Dcore.c306 #define ALU(OPCODE, OP) \ __bpf_prog_run()
308 DST = DST OP SRC; \ __bpf_prog_run()
311 DST = (u32) DST OP (u32) SRC; \ __bpf_prog_run()
314 DST = DST OP IMM; \ __bpf_prog_run()
317 DST = (u32) DST OP (u32) IMM; \ __bpf_prog_run()
/linux-4.1.27/drivers/scsi/
H A Daha1740.h141 #define AHA1740CMD_NOP 0x00 /* No OP */
H A Dscsi_devinfo.c177 {"HITACHI", "OP-C-", "*", BLIST_SPARSELUN | BLIST_LARGELUN},
192 {"HP", "OP-C-", "*", BLIST_SPARSELUN | BLIST_LARGELUN},
H A Dips.h145 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
H A Dinitio.c286 | SB OP | OP A5 A4
H A Dwd7000.c365 #define NO_OP 0 /* NO-OP toggles CMD_RDY bit in ASC_STAT */
H A Ddc395x.c3963 /* program SB + OP code */ trms1040_write_cmd()
/linux-4.1.27/arch/tile/kernel/
H A Dbacktrace.c126 /* Does this bundle contain any 'info OP' or 'infol OP'
127 * instruction, and if so, what are their OP? Note that OP is interpreted
/linux-4.1.27/include/uapi/linux/
H A Dfutex.h144 *(int *)UADDR2 = oldval OP OPARG;
/linux-4.1.27/arch/arc/include/asm/
H A Ddma-mapping.h76 pr_err("Invalid DMA dir [%d] for OP @ %lx\n", dir, paddr); __inline_dma_cache_sync()
/linux-4.1.27/drivers/scsi/bfa/
H A Dbfa_ioc_cb.c332 * can not be in OP state when this function is called. bfa_ioc_cb_sync_complete()
334 * However, this IOC could still be in OP state when bfa_ioc_cb_sync_complete()
/linux-4.1.27/drivers/scsi/aic7xxx/
H A Daic7xxx_93cx6.c37 * Start OP *
60 * OP code, Address, and Data (if needed). For the READ instruction, the
H A Daic79xx_core.c4427 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); ahd_setup_initiator_msgout()
/linux-4.1.27/drivers/infiniband/hw/usnic/
H A Dusnic_ib_qp_grp.c399 /* NO-OP */ usnic_ib_qp_grp_modify()
470 /* NO-OP FOR NOW */ usnic_ib_qp_grp_modify()
/linux-4.1.27/drivers/mtd/
H A Dbcm47xxpart.c40 #define POT_MAGIC2 0x504f /* OP */
/linux-4.1.27/include/uapi/linux/netfilter_arp/
H A Darp_tables.h85 #define ARPT_INV_ARPOP 0x0040 /* Invert the sense of ARP OP. */
/linux-4.1.27/include/uapi/linux/netfilter_ipv4/
H A Dip_tables.h96 #define IPT_INV_DSTIP 0x10 /* Invert the sense of DST OP. */
/linux-4.1.27/include/uapi/linux/netfilter_ipv6/
H A Dip6_tables.h100 #define IP6T_INV_DSTIP 0x10 /* Invert the sense of DST OP. */
/linux-4.1.27/include/video/
H A Dexynos7_decon.h328 /* LINECNT OP THRSHOLD*/
/linux-4.1.27/net/sunrpc/
H A Dstats.c145 * @op_metrics: stat structure for OP that will accumulate stats from @task
/linux-4.1.27/include/math-emu/
H A Dop-common.h229 #define _FP_ADD_INTERNAL(fs, wc, R, X, Y, OP) \
306 _FP_CHOOSENAN(fs, wc, R, X, Y, OP); \
/linux-4.1.27/arch/arm/mach-tegra/
H A Dsleep-tegra30.S497 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
507 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
/linux-4.1.27/tools/lib/traceevent/
H A Devent-parse.h400 _PE(REPARENT_NOT_OP, "cannot reparent other than OP"), \
401 _PE(REPARENT_FAILED, "failed to reparent filter OP"), \
H A Dparse-filter.c772 show_error(error_str, "can not reparent other than OP"); reparent_op_arg()
H A Devent-parse.c1453 * If the next token is not an OP, then it is of event_read_fields()
/linux-4.1.27/drivers/net/ethernet/dlink/
H A Ddl2k.c1346 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ mii_read()
1347 /* ST,OP = 0110'b for read operation */ mii_read()
1372 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ mii_write()
1373 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ mii_write()
/linux-4.1.27/drivers/media/i2c/m5mols/
H A Dm5mols_reg.h74 #define REG_SAMSUNG_OPTICS "OP" /* Samsung Fiber-Optics */
/linux-4.1.27/arch/sparc/kernel/
H A Dfpu_traps.S223 cmp %g1, 2 ! Unfinished FP-OP
/linux-4.1.27/arch/powerpc/include/asm/
H A Dsfp-machine.h144 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
H A Dcpm2.h75 #define mk_cr_cmd(PG, SBC, MCN, OP) \
76 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
/linux-4.1.27/arch/x86/kernel/cpu/
H A Dperf_event_intel_ds.c51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); precise_store_data()
/linux-4.1.27/arch/mn10300/mm/
H A Dmisalignment.c818 #define ASSERTCMP(X, OP, Y) \
820 if (unlikely(!((X) OP (Y)))) { \
824 printk(KERN_ERR "0x%lx " #OP " 0x%lx is false\n", \
/linux-4.1.27/drivers/net/ethernet/
H A Dfealnx.c306 /* ST+OP+PHYAD+REGAD+TA */
307 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
308 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
730 /* calculate ST+OP+PHYAD+REGAD+TA */ m80x_send_cmd_to_phy()
/linux-4.1.27/drivers/net/ethernet/icplus/
H A Dipg.c241 { GMII_READ, 2 }, /* OP */ mdio_read()
254 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */ mdio_read()
332 { GMII_WRITE, 2 }, /* OP */ mdio_write()
345 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */ mdio_write()
/linux-4.1.27/arch/microblaze/kernel/cpu/
H A Dcache.c140 /* It is used only first parameter for OP - for wic, wdc */
/linux-4.1.27/include/linux/mfd/wm8350/
H A Daudio.h575 /* OP clock dividers */
/linux-4.1.27/drivers/media/platform/vivid/
H A Dvivid-vid-cap.c1794 #define FRACT_CMP(a, OP, b) \
1795 ((u64)(a).numerator * (b).denominator OP (u64)(b).numerator * (a).denominator)
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c735 /* Write the PHY address, register number and set the OP bit in the xemaclite_mdio_read()
781 /* Write the PHY address, register number and clear the OP bit in the xemaclite_mdio_write()
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type.h1151 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
1152 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
1153 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
1154 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
1155 #define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (read) */
1156 #define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (read, auto inc)*/
/linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c3618 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F); t4_wol_pat_enable()
3619 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ t4_wol_pat_enable()
3620 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) t4_wol_pat_enable()
3625 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F); t4_wol_pat_enable()
3626 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ t4_wol_pat_enable()
3627 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F) t4_wol_pat_enable()
/linux-4.1.27/drivers/isdn/hardware/mISDN/
H A Dw6692.c1037 pr_info("%s: unknown CTRL OP %x\n", card->name, cq->op); channel_ctrl()
H A DmISDNipac.c1535 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op); channel_ctrl()
/linux-4.1.27/drivers/mtd/nand/
H A Dfsl_elbc_nand.c204 /* Setup the FMR[OP] to execute without write protection */ fsl_elbc_run_command()
/linux-4.1.27/drivers/net/ethernet/natsemi/
H A Dnatsemi.c1082 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ miiport_read()
1083 /* ST,OP = 0110'b for read operation */ miiport_read()
1105 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ miiport_write()
1106 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ miiport_write()
/linux-4.1.27/drivers/net/wireless/ath/ath10k/
H A Dcore.c935 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", ath10k_core_init_firmware_features()
/linux-4.1.27/drivers/scsi/fnic/
H A Dfnic_fcs.c404 "Received VLAN response... OP 0x%x SUB_OP 0x%x\n", fnic_fcoe_process_vlan_resp()
/linux-4.1.27/drivers/s390/char/
H A Dtape_core.c926 DBF_EVENT(3, "DEVICE: %08x OP\t: %s\n", device->cdev_id, op); tape_dump_sense_dbf()
/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr8192U.h865 /* The simple tx command OP code. */
/linux-4.1.27/drivers/input/mouse/
H A Dcyapa.c162 * On smbus systems in OP mode, the i2c_reg_read will fail with cyapa_get_state()
/linux-4.1.27/arch/powerpc/kernel/
H A Dhead_8xx.S523 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
/linux-4.1.27/arch/alpha/kernel/
H A Dperf_event.c677 * that we can just use it, hence a NO-OP here. __hw_perf_event_init()
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A D3945.c931 D_INFO("SKU OP mode is mrc\n"); il3945_nic_config()
935 D_INFO("SKU OP mode is basic\n"); il3945_nic_config()
/linux-4.1.27/fs/proc/
H A Dbase.c116 #define NOD(NAME, MODE, IOP, FOP, OP) { \
122 .op = OP, \
/linux-4.1.27/drivers/isdn/hisax/
H A Delsa.c116 {NULL,0,2,{0xa1,0x3f,0,0,0,0,0,0,0,0}}; /* Normal OP */
/linux-4.1.27/drivers/net/cris/
H A Deth_v10.c941 /* Start of frame, OP Code, Physical Address, Register Address */ e100_get_mdio_reg()
/linux-4.1.27/drivers/net/ethernet/freescale/
H A Dgianfar.h606 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
/linux-4.1.27/drivers/net/wireless/libertas/
H A Dcfg.c1581 * I think can keep this a NO-OP, because: lbs_cfg_del_key()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Dhal_btc.c781 "[BTCoex], set to ignore wlanAct for BT OP!!\n"); rtl8723e_dm_bt_set_bt_dm()
/linux-4.1.27/drivers/net/wireless/cw1200/
H A Dwsm.h1127 /* TX OP Limit (in microseconds) for the access class. */
/linux-4.1.27/drivers/crypto/caam/
H A Ddesc.h412 /* Operation type selectors - OP TYPE */
/linux-4.1.27/drivers/net/wireless/iwlwifi/pcie/
H A Dtrans.c877 IWL_ERR(trans, "FW debug - unknown OP %d\n", iwl_pcie_apply_destination()
/linux-4.1.27/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_hw.c190 0x3570, /* DRV OP MODE */
/linux-4.1.27/drivers/media/i2c/smiapp/
H A Dsmiapp-core.c2701 /* Profile 0 sensors have no separate OP clock branch. */ smiapp_init()
/linux-4.1.27/drivers/rapidio/devices/
H A Dtsi721.c162 dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n", tsi721_maint_dma()
/linux-4.1.27/drivers/net/ethernet/atheros/atlx/
H A Datl1.c825 /* Init OP table */ atl1_init_flash_opcode()
H A Datl2.c2418 /* Init OP table */ atl2_init_flash_opcode()
/linux-4.1.27/arch/mips/kvm/
H A Demulate.c1710 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n", kvm_mips_emulate_cache()
/linux-4.1.27/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h4623 /* MC_CMD_FILTER_OP_IN/OP */
4654 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
/linux-4.1.27/drivers/net/ethernet/agere/
H A Det131x.c222 * 29: asw_unsupported_op unsupported OP code
/linux-4.1.27/drivers/scsi/qla2xxx/
H A Dqla_mbx.c3758 /* NOTE: we only update OP firmware. */ qla84xx_verify_chip()
/linux-4.1.27/drivers/usb/host/
H A Dxhci-ring.c1374 /* Is this an aborted command turned to NO-OP? */ handle_cmd_completion()
/linux-4.1.27/scripts/
H A Dcheckpatch.pl1563 print "OP($1)\n" if ($dbg_values > 1);
/linux-4.1.27/sound/pci/hda/
H A Dpatch_realtek.c2998 alc5505_coef_set(codec, 0x6230, 0xfc0d4011); /* Disable Input OP */ alc5505_dsp_halt()
/linux-4.1.27/drivers/message/fusion/
H A Dmptbase.c2985 * BIOS or previous driver load left IOC in OP state. MakeIocReady()
/linux-4.1.27/kernel/events/
H A Dcore.c8161 * By installing siblings first we NO-OP because they're not SYSCALL_DEFINE5()
/linux-4.1.27/arch/m68k/ifpsp060/src/
H A Dfplsp.S539 # TRANSCENDENTAL "LAST-OP" FLAGS #
H A Dpfpsp.S558 # TRANSCENDENTAL "LAST-OP" FLAGS #
H A Dfpsp.S559 # TRANSCENDENTAL "LAST-OP" FLAGS #

Completed in 6207 milliseconds