1/* 2 * drivers/net/ethernet/freescale/gianfar.h 3 * 4 * Gianfar Ethernet Driver 5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560 6 * Based on 8260_io/fcc_enet.c 7 * 8 * Author: Andy Fleming 9 * Maintainer: Kumar Gala 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 11 * 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 * 19 * Still left to do: 20 * -Add support for module parameters 21 * -Add patch for ethtool phys id 22 */ 23#ifndef __GIANFAR_H 24#define __GIANFAR_H 25 26#include <linux/kernel.h> 27#include <linux/sched.h> 28#include <linux/string.h> 29#include <linux/errno.h> 30#include <linux/slab.h> 31#include <linux/interrupt.h> 32#include <linux/delay.h> 33#include <linux/netdevice.h> 34#include <linux/etherdevice.h> 35#include <linux/skbuff.h> 36#include <linux/spinlock.h> 37#include <linux/mm.h> 38#include <linux/mii.h> 39#include <linux/phy.h> 40 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/uaccess.h> 44#include <linux/module.h> 45#include <linux/crc32.h> 46#include <linux/workqueue.h> 47#include <linux/ethtool.h> 48 49struct ethtool_flow_spec_container { 50 struct ethtool_rx_flow_spec fs; 51 struct list_head list; 52}; 53 54struct ethtool_rx_list { 55 struct list_head list; 56 unsigned int count; 57}; 58 59/* The maximum number of packets to be handled in one call of gfar_poll */ 60#define GFAR_DEV_WEIGHT 64 61 62/* Length for FCB */ 63#define GMAC_FCB_LEN 8 64 65/* Length for TxPAL */ 66#define GMAC_TXPAL_LEN 16 67 68/* Default padding amount */ 69#define DEFAULT_PADDING 2 70 71/* Number of bytes to align the rx bufs to */ 72#define RXBUF_ALIGNMENT 64 73 74/* The number of bytes which composes a unit for the purpose of 75 * allocating data buffers. ie-for any given MTU, the data buffer 76 * will be the next highest multiple of 512 bytes. */ 77#define INCREMENTAL_BUFFER_SIZE 512 78 79#define PHY_INIT_TIMEOUT 100000 80 81#define DRV_NAME "gfar-enet" 82extern const char gfar_driver_version[]; 83 84/* MAXIMUM NUMBER OF QUEUES SUPPORTED */ 85#define MAX_TX_QS 0x8 86#define MAX_RX_QS 0x8 87 88/* MAXIMUM NUMBER OF GROUPS SUPPORTED */ 89#define MAXGROUPS 0x2 90 91/* These need to be powers of 2 for this driver */ 92#define DEFAULT_TX_RING_SIZE 256 93#define DEFAULT_RX_RING_SIZE 256 94 95#define GFAR_RX_MAX_RING_SIZE 256 96#define GFAR_TX_MAX_RING_SIZE 256 97 98#define GFAR_MAX_FIFO_THRESHOLD 511 99#define GFAR_MAX_FIFO_STARVE 511 100#define GFAR_MAX_FIFO_STARVE_OFF 511 101 102#define FBTHR_SHIFT 24 103#define DEFAULT_RX_LFC_THR 16 104#define DEFAULT_LFC_PTVVAL 4 105 106#define DEFAULT_RX_BUFFER_SIZE 1536 107#define TX_RING_MOD_MASK(size) (size-1) 108#define RX_RING_MOD_MASK(size) (size-1) 109#define JUMBO_BUFFER_SIZE 9728 110#define JUMBO_FRAME_SIZE 9600 111 112#define DEFAULT_FIFO_TX_THR 0x100 113#define DEFAULT_FIFO_TX_STARVE 0x40 114#define DEFAULT_FIFO_TX_STARVE_OFF 0x80 115#define DEFAULT_BD_STASH 1 116#define DEFAULT_STASH_LENGTH 96 117#define DEFAULT_STASH_INDEX 0 118 119/* The number of Exact Match registers */ 120#define GFAR_EM_NUM 15 121 122/* Latency of interface clock in nanoseconds */ 123/* Interface clock latency , in this case, means the 124 * time described by a value of 1 in the interrupt 125 * coalescing registers' time fields. Since those fields 126 * refer to the time it takes for 64 clocks to pass, the 127 * latencies are as such: 128 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick 129 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick 130 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick 131 */ 132#define GFAR_GBIT_TIME 512 133#define GFAR_100_TIME 2560 134#define GFAR_10_TIME 25600 135 136#define DEFAULT_TX_COALESCE 1 137#define DEFAULT_TXCOUNT 16 138#define DEFAULT_TXTIME 21 139 140#define DEFAULT_RXTIME 21 141 142#define DEFAULT_RX_COALESCE 0 143#define DEFAULT_RXCOUNT 0 144 145#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \ 146 | SUPPORTED_10baseT_Full \ 147 | SUPPORTED_100baseT_Half \ 148 | SUPPORTED_100baseT_Full \ 149 | SUPPORTED_Autoneg \ 150 | SUPPORTED_MII) 151 152#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full 153 154/* TBI register addresses */ 155#define MII_TBICON 0x11 156 157/* TBICON register bit fields */ 158#define TBICON_CLK_SELECT 0x0020 159 160/* MAC register bits */ 161#define MACCFG1_SOFT_RESET 0x80000000 162#define MACCFG1_RESET_RX_MC 0x00080000 163#define MACCFG1_RESET_TX_MC 0x00040000 164#define MACCFG1_RESET_RX_FUN 0x00020000 165#define MACCFG1_RESET_TX_FUN 0x00010000 166#define MACCFG1_LOOPBACK 0x00000100 167#define MACCFG1_RX_FLOW 0x00000020 168#define MACCFG1_TX_FLOW 0x00000010 169#define MACCFG1_SYNCD_RX_EN 0x00000008 170#define MACCFG1_RX_EN 0x00000004 171#define MACCFG1_SYNCD_TX_EN 0x00000002 172#define MACCFG1_TX_EN 0x00000001 173 174#define MACCFG2_INIT_SETTINGS 0x00007205 175#define MACCFG2_FULL_DUPLEX 0x00000001 176#define MACCFG2_IF 0x00000300 177#define MACCFG2_MII 0x00000100 178#define MACCFG2_GMII 0x00000200 179#define MACCFG2_HUGEFRAME 0x00000020 180#define MACCFG2_LENGTHCHECK 0x00000010 181#define MACCFG2_MPEN 0x00000008 182 183#define ECNTRL_FIFM 0x00008000 184#define ECNTRL_INIT_SETTINGS 0x00001000 185#define ECNTRL_TBI_MODE 0x00000020 186#define ECNTRL_REDUCED_MODE 0x00000010 187#define ECNTRL_R100 0x00000008 188#define ECNTRL_REDUCED_MII_MODE 0x00000004 189#define ECNTRL_SGMII_MODE 0x00000002 190 191#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE 192 193#define MINFLR_INIT_SETTINGS 0x00000040 194 195/* Tqueue control */ 196#define TQUEUE_EN0 0x00008000 197#define TQUEUE_EN1 0x00004000 198#define TQUEUE_EN2 0x00002000 199#define TQUEUE_EN3 0x00001000 200#define TQUEUE_EN4 0x00000800 201#define TQUEUE_EN5 0x00000400 202#define TQUEUE_EN6 0x00000200 203#define TQUEUE_EN7 0x00000100 204#define TQUEUE_EN_ALL 0x0000FF00 205 206#define TR03WT_WT0_MASK 0xFF000000 207#define TR03WT_WT1_MASK 0x00FF0000 208#define TR03WT_WT2_MASK 0x0000FF00 209#define TR03WT_WT3_MASK 0x000000FF 210 211#define TR47WT_WT4_MASK 0xFF000000 212#define TR47WT_WT5_MASK 0x00FF0000 213#define TR47WT_WT6_MASK 0x0000FF00 214#define TR47WT_WT7_MASK 0x000000FF 215 216/* Rqueue control */ 217#define RQUEUE_EX0 0x00800000 218#define RQUEUE_EX1 0x00400000 219#define RQUEUE_EX2 0x00200000 220#define RQUEUE_EX3 0x00100000 221#define RQUEUE_EX4 0x00080000 222#define RQUEUE_EX5 0x00040000 223#define RQUEUE_EX6 0x00020000 224#define RQUEUE_EX7 0x00010000 225#define RQUEUE_EX_ALL 0x00FF0000 226 227#define RQUEUE_EN0 0x00000080 228#define RQUEUE_EN1 0x00000040 229#define RQUEUE_EN2 0x00000020 230#define RQUEUE_EN3 0x00000010 231#define RQUEUE_EN4 0x00000008 232#define RQUEUE_EN5 0x00000004 233#define RQUEUE_EN6 0x00000002 234#define RQUEUE_EN7 0x00000001 235#define RQUEUE_EN_ALL 0x000000FF 236 237/* Init to do tx snooping for buffers and descriptors */ 238#define DMACTRL_INIT_SETTINGS 0x000000c3 239#define DMACTRL_GRS 0x00000010 240#define DMACTRL_GTS 0x00000008 241 242#define TSTAT_CLEAR_THALT_ALL 0xFF000000 243#define TSTAT_CLEAR_THALT 0x80000000 244#define TSTAT_CLEAR_THALT0 0x80000000 245#define TSTAT_CLEAR_THALT1 0x40000000 246#define TSTAT_CLEAR_THALT2 0x20000000 247#define TSTAT_CLEAR_THALT3 0x10000000 248#define TSTAT_CLEAR_THALT4 0x08000000 249#define TSTAT_CLEAR_THALT5 0x04000000 250#define TSTAT_CLEAR_THALT6 0x02000000 251#define TSTAT_CLEAR_THALT7 0x01000000 252 253/* Interrupt coalescing macros */ 254#define IC_ICEN 0x80000000 255#define IC_ICFT_MASK 0x1fe00000 256#define IC_ICFT_SHIFT 21 257#define mk_ic_icft(x) \ 258 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK) 259#define IC_ICTT_MASK 0x0000ffff 260#define mk_ic_ictt(x) (x&IC_ICTT_MASK) 261 262#define mk_ic_value(count, time) (IC_ICEN | \ 263 mk_ic_icft(count) | \ 264 mk_ic_ictt(time)) 265#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \ 266 IC_ICFT_SHIFT) 267#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK) 268 269#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME) 270#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME) 271 272#define skip_bd(bdp, stride, base, ring_size) ({ \ 273 typeof(bdp) new_bd = (bdp) + (stride); \ 274 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; }) 275 276#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size) 277 278#define RCTRL_TS_ENABLE 0x01000000 279#define RCTRL_PAL_MASK 0x001f0000 280#define RCTRL_LFC 0x00004000 281#define RCTRL_VLEX 0x00002000 282#define RCTRL_FILREN 0x00001000 283#define RCTRL_GHTX 0x00000400 284#define RCTRL_IPCSEN 0x00000200 285#define RCTRL_TUCSEN 0x00000100 286#define RCTRL_PRSDEP_MASK 0x000000c0 287#define RCTRL_PRSDEP_INIT 0x000000c0 288#define RCTRL_PRSFM 0x00000020 289#define RCTRL_PROM 0x00000008 290#define RCTRL_EMEN 0x00000002 291#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \ 292 RCTRL_TUCSEN | RCTRL_FILREN) 293#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \ 294 RCTRL_PRSDEP_INIT) 295#define RCTRL_EXTHASH (RCTRL_GHTX) 296#define RCTRL_VLAN (RCTRL_PRSDEP_INIT) 297#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK) 298 299 300#define RSTAT_CLEAR_RHALT 0x00800000 301#define RSTAT_CLEAR_RXF0 0x00000080 302#define RSTAT_RXF_MASK 0x000000ff 303 304#define TCTRL_IPCSEN 0x00004000 305#define TCTRL_TUCSEN 0x00002000 306#define TCTRL_VLINS 0x00001000 307#define TCTRL_THDF 0x00000800 308#define TCTRL_RFCPAUSE 0x00000010 309#define TCTRL_TFCPAUSE 0x00000008 310#define TCTRL_TXSCHED_MASK 0x00000006 311#define TCTRL_TXSCHED_INIT 0x00000000 312/* priority scheduling */ 313#define TCTRL_TXSCHED_PRIO 0x00000002 314/* weighted round-robin scheduling (WRRS) */ 315#define TCTRL_TXSCHED_WRRS 0x00000004 316/* default WRRS weight and policy setting, 317 * tailored to the tr03wt and tr47wt registers: 318 * equal weight for all Tx Qs, measured in 64byte units 319 */ 320#define DEFAULT_WRRS_WEIGHT 0x18181818 321 322#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN) 323 324#define IEVENT_INIT_CLEAR 0xffffffff 325#define IEVENT_BABR 0x80000000 326#define IEVENT_RXC 0x40000000 327#define IEVENT_BSY 0x20000000 328#define IEVENT_EBERR 0x10000000 329#define IEVENT_MSRO 0x04000000 330#define IEVENT_GTSC 0x02000000 331#define IEVENT_BABT 0x01000000 332#define IEVENT_TXC 0x00800000 333#define IEVENT_TXE 0x00400000 334#define IEVENT_TXB 0x00200000 335#define IEVENT_TXF 0x00100000 336#define IEVENT_LC 0x00040000 337#define IEVENT_CRL 0x00020000 338#define IEVENT_XFUN 0x00010000 339#define IEVENT_RXB0 0x00008000 340#define IEVENT_MAG 0x00000800 341#define IEVENT_GRSC 0x00000100 342#define IEVENT_RXF0 0x00000080 343#define IEVENT_FIR 0x00000008 344#define IEVENT_FIQ 0x00000004 345#define IEVENT_DPE 0x00000002 346#define IEVENT_PERR 0x00000001 347#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY) 348#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF) 349#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK) 350#define IEVENT_ERR_MASK \ 351(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \ 352 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \ 353 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \ 354 | IEVENT_MAG | IEVENT_BABR) 355 356#define IMASK_INIT_CLEAR 0x00000000 357#define IMASK_BABR 0x80000000 358#define IMASK_RXC 0x40000000 359#define IMASK_BSY 0x20000000 360#define IMASK_EBERR 0x10000000 361#define IMASK_MSRO 0x04000000 362#define IMASK_GTSC 0x02000000 363#define IMASK_BABT 0x01000000 364#define IMASK_TXC 0x00800000 365#define IMASK_TXEEN 0x00400000 366#define IMASK_TXBEN 0x00200000 367#define IMASK_TXFEN 0x00100000 368#define IMASK_LC 0x00040000 369#define IMASK_CRL 0x00020000 370#define IMASK_XFUN 0x00010000 371#define IMASK_RXB0 0x00008000 372#define IMASK_MAG 0x00000800 373#define IMASK_GRSC 0x00000100 374#define IMASK_RXFEN0 0x00000080 375#define IMASK_FIR 0x00000008 376#define IMASK_FIQ 0x00000004 377#define IMASK_DPE 0x00000002 378#define IMASK_PERR 0x00000001 379#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \ 380 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \ 381 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \ 382 | IMASK_PERR) 383#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY) 384#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN) 385 386#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT) 387#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT) 388 389/* Fifo management */ 390#define FIFO_TX_THR_MASK 0x01ff 391#define FIFO_TX_STARVE_MASK 0x01ff 392#define FIFO_TX_STARVE_OFF_MASK 0x01ff 393 394/* Attribute fields */ 395 396/* This enables rx snooping for buffers and descriptors */ 397#define ATTR_BDSTASH 0x00000800 398 399#define ATTR_BUFSTASH 0x00004000 400 401#define ATTR_SNOOPING 0x000000c0 402#define ATTR_INIT_SETTINGS ATTR_SNOOPING 403 404#define ATTRELI_INIT_SETTINGS 0x0 405#define ATTRELI_EL_MASK 0x3fff0000 406#define ATTRELI_EL(x) (x << 16) 407#define ATTRELI_EI_MASK 0x00003fff 408#define ATTRELI_EI(x) (x) 409 410#define BD_LFLAG(flags) ((flags) << 16) 411#define BD_LENGTH_MASK 0x0000ffff 412 413#define FPR_FILER_MASK 0xFFFFFFFF 414#define MAX_FILER_IDX 0xFF 415 416/* This default RIR value directly corresponds 417 * to the 3-bit hash value generated */ 418#define DEFAULT_8RXQ_RIR0 0x05397700 419/* Map even hash values to Q0, and odd ones to Q1 */ 420#define DEFAULT_2RXQ_RIR0 0x04104100 421 422/* RQFCR register bits */ 423#define RQFCR_GPI 0x80000000 424#define RQFCR_HASHTBL_Q 0x00000000 425#define RQFCR_HASHTBL_0 0x00020000 426#define RQFCR_HASHTBL_1 0x00040000 427#define RQFCR_HASHTBL_2 0x00060000 428#define RQFCR_HASHTBL_3 0x00080000 429#define RQFCR_HASH 0x00010000 430#define RQFCR_QUEUE 0x0000FC00 431#define RQFCR_CLE 0x00000200 432#define RQFCR_RJE 0x00000100 433#define RQFCR_AND 0x00000080 434#define RQFCR_CMP_EXACT 0x00000000 435#define RQFCR_CMP_MATCH 0x00000020 436#define RQFCR_CMP_NOEXACT 0x00000040 437#define RQFCR_CMP_NOMATCH 0x00000060 438 439/* RQFCR PID values */ 440#define RQFCR_PID_MASK 0x00000000 441#define RQFCR_PID_PARSE 0x00000001 442#define RQFCR_PID_ARB 0x00000002 443#define RQFCR_PID_DAH 0x00000003 444#define RQFCR_PID_DAL 0x00000004 445#define RQFCR_PID_SAH 0x00000005 446#define RQFCR_PID_SAL 0x00000006 447#define RQFCR_PID_ETY 0x00000007 448#define RQFCR_PID_VID 0x00000008 449#define RQFCR_PID_PRI 0x00000009 450#define RQFCR_PID_TOS 0x0000000A 451#define RQFCR_PID_L4P 0x0000000B 452#define RQFCR_PID_DIA 0x0000000C 453#define RQFCR_PID_SIA 0x0000000D 454#define RQFCR_PID_DPT 0x0000000E 455#define RQFCR_PID_SPT 0x0000000F 456 457/* RQFPR when PID is 0x0001 */ 458#define RQFPR_HDR_GE_512 0x00200000 459#define RQFPR_LERR 0x00100000 460#define RQFPR_RAR 0x00080000 461#define RQFPR_RARQ 0x00040000 462#define RQFPR_AR 0x00020000 463#define RQFPR_ARQ 0x00010000 464#define RQFPR_EBC 0x00008000 465#define RQFPR_VLN 0x00004000 466#define RQFPR_CFI 0x00002000 467#define RQFPR_JUM 0x00001000 468#define RQFPR_IPF 0x00000800 469#define RQFPR_FIF 0x00000400 470#define RQFPR_IPV4 0x00000200 471#define RQFPR_IPV6 0x00000100 472#define RQFPR_ICC 0x00000080 473#define RQFPR_ICV 0x00000040 474#define RQFPR_TCP 0x00000020 475#define RQFPR_UDP 0x00000010 476#define RQFPR_TUC 0x00000008 477#define RQFPR_TUV 0x00000004 478#define RQFPR_PER 0x00000002 479#define RQFPR_EER 0x00000001 480 481/* TxBD status field bits */ 482#define TXBD_READY 0x8000 483#define TXBD_PADCRC 0x4000 484#define TXBD_WRAP 0x2000 485#define TXBD_INTERRUPT 0x1000 486#define TXBD_LAST 0x0800 487#define TXBD_CRC 0x0400 488#define TXBD_DEF 0x0200 489#define TXBD_HUGEFRAME 0x0080 490#define TXBD_LATECOLLISION 0x0080 491#define TXBD_RETRYLIMIT 0x0040 492#define TXBD_RETRYCOUNTMASK 0x003c 493#define TXBD_UNDERRUN 0x0002 494#define TXBD_TOE 0x0002 495 496/* Tx FCB param bits */ 497#define TXFCB_VLN 0x80 498#define TXFCB_IP 0x40 499#define TXFCB_IP6 0x20 500#define TXFCB_TUP 0x10 501#define TXFCB_UDP 0x08 502#define TXFCB_CIP 0x04 503#define TXFCB_CTU 0x02 504#define TXFCB_NPH 0x01 505#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH) 506 507/* RxBD status field bits */ 508#define RXBD_EMPTY 0x8000 509#define RXBD_RO1 0x4000 510#define RXBD_WRAP 0x2000 511#define RXBD_INTERRUPT 0x1000 512#define RXBD_LAST 0x0800 513#define RXBD_FIRST 0x0400 514#define RXBD_MISS 0x0100 515#define RXBD_BROADCAST 0x0080 516#define RXBD_MULTICAST 0x0040 517#define RXBD_LARGE 0x0020 518#define RXBD_NONOCTET 0x0010 519#define RXBD_SHORT 0x0008 520#define RXBD_CRCERR 0x0004 521#define RXBD_OVERRUN 0x0002 522#define RXBD_TRUNCATED 0x0001 523#define RXBD_STATS 0x01ff 524#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \ 525 | RXBD_CRCERR | RXBD_OVERRUN \ 526 | RXBD_TRUNCATED) 527 528/* Rx FCB status field bits */ 529#define RXFCB_VLN 0x8000 530#define RXFCB_IP 0x4000 531#define RXFCB_IP6 0x2000 532#define RXFCB_TUP 0x1000 533#define RXFCB_CIP 0x0800 534#define RXFCB_CTU 0x0400 535#define RXFCB_EIP 0x0200 536#define RXFCB_ETU 0x0100 537#define RXFCB_CSUM_MASK 0x0f00 538#define RXFCB_PERR_MASK 0x000c 539#define RXFCB_PERR_BADL3 0x0008 540 541#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */ 542 543struct txbd8 544{ 545 union { 546 struct { 547 __be16 status; /* Status Fields */ 548 __be16 length; /* Buffer length */ 549 }; 550 __be32 lstatus; 551 }; 552 __be32 bufPtr; /* Buffer Pointer */ 553}; 554 555struct txfcb { 556 u8 flags; 557 u8 ptp; /* Flag to enable tx timestamping */ 558 u8 l4os; /* Level 4 Header Offset */ 559 u8 l3os; /* Level 3 Header Offset */ 560 __be16 phcs; /* Pseudo-header Checksum */ 561 __be16 vlctl; /* VLAN control word */ 562}; 563 564struct rxbd8 565{ 566 union { 567 struct { 568 __be16 status; /* Status Fields */ 569 __be16 length; /* Buffer Length */ 570 }; 571 __be32 lstatus; 572 }; 573 __be32 bufPtr; /* Buffer Pointer */ 574}; 575 576struct rxfcb { 577 __be16 flags; 578 u8 rq; /* Receive Queue index */ 579 u8 pro; /* Layer 4 Protocol */ 580 u16 reserved; 581 __be16 vlctl; /* VLAN control word */ 582}; 583 584struct gianfar_skb_cb { 585 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */ 586}; 587 588#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb)) 589 590struct rmon_mib 591{ 592 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */ 593 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */ 594 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */ 595 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */ 596 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */ 597 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */ 598 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 599 u32 rbyt; /* 0x.69c - Receive Byte Counter */ 600 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */ 601 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */ 602 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */ 603 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */ 604 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */ 605 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */ 606 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */ 607 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */ 608 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */ 609 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */ 610 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */ 611 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */ 612 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */ 613 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */ 614 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */ 615 u32 rdrp; /* 0x.6dc - Receive Drop Counter */ 616 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */ 617 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */ 618 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */ 619 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */ 620 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */ 621 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */ 622 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */ 623 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */ 624 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */ 625 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */ 626 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */ 627 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */ 628 u8 res1[4]; 629 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */ 630 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */ 631 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */ 632 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */ 633 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */ 634 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */ 635 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */ 636 u32 car1; /* 0x.730 - Carry Register One */ 637 u32 car2; /* 0x.734 - Carry Register Two */ 638 u32 cam1; /* 0x.738 - Carry Mask Register One */ 639 u32 cam2; /* 0x.73c - Carry Mask Register Two */ 640}; 641 642struct gfar_extra_stats { 643 atomic64_t rx_large; 644 atomic64_t rx_short; 645 atomic64_t rx_nonoctet; 646 atomic64_t rx_crcerr; 647 atomic64_t rx_overrun; 648 atomic64_t rx_bsy; 649 atomic64_t rx_babr; 650 atomic64_t rx_trunc; 651 atomic64_t eberr; 652 atomic64_t tx_babt; 653 atomic64_t tx_underrun; 654 atomic64_t rx_skbmissing; 655 atomic64_t tx_timeout; 656}; 657 658#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32)) 659#define GFAR_EXTRA_STATS_LEN \ 660 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t)) 661 662/* Number of stats exported via ethtool */ 663#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN) 664 665struct gfar { 666 u32 tsec_id; /* 0x.000 - Controller ID register */ 667 u32 tsec_id2; /* 0x.004 - Controller ID2 register */ 668 u8 res1[8]; 669 u32 ievent; /* 0x.010 - Interrupt Event Register */ 670 u32 imask; /* 0x.014 - Interrupt Mask Register */ 671 u32 edis; /* 0x.018 - Error Disabled Register */ 672 u32 emapg; /* 0x.01c - Group Error mapping register */ 673 u32 ecntrl; /* 0x.020 - Ethernet Control Register */ 674 u32 minflr; /* 0x.024 - Minimum Frame Length Register */ 675 u32 ptv; /* 0x.028 - Pause Time Value Register */ 676 u32 dmactrl; /* 0x.02c - DMA Control Register */ 677 u32 tbipa; /* 0x.030 - TBI PHY Address Register */ 678 u8 res2[28]; 679 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold 680 register */ 681 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff 682 register */ 683 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold 684 register */ 685 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve 686 shutoff register */ 687 u8 res3[44]; 688 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */ 689 u8 res4[8]; 690 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */ 691 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */ 692 u8 res5[96]; 693 u32 tctrl; /* 0x.100 - Transmit Control Register */ 694 u32 tstat; /* 0x.104 - Transmit Status Register */ 695 u32 dfvlan; /* 0x.108 - Default VLAN Control word */ 696 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */ 697 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */ 698 u32 tqueue; /* 0x.114 - Transmit queue control register */ 699 u8 res7[40]; 700 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */ 701 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */ 702 u8 res8[52]; 703 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */ 704 u8 res9a[4]; 705 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */ 706 u8 res9b[4]; 707 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */ 708 u8 res9c[4]; 709 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */ 710 u8 res9d[4]; 711 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */ 712 u8 res9e[4]; 713 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */ 714 u8 res9f[4]; 715 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */ 716 u8 res9g[4]; 717 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */ 718 u8 res9h[4]; 719 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */ 720 u8 res9[64]; 721 u32 tbaseh; /* 0x.200 - TxBD base address high */ 722 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */ 723 u8 res10a[4]; 724 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */ 725 u8 res10b[4]; 726 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */ 727 u8 res10c[4]; 728 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */ 729 u8 res10d[4]; 730 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */ 731 u8 res10e[4]; 732 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */ 733 u8 res10f[4]; 734 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */ 735 u8 res10g[4]; 736 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */ 737 u8 res10[192]; 738 u32 rctrl; /* 0x.300 - Receive Control Register */ 739 u32 rstat; /* 0x.304 - Receive Status Register */ 740 u8 res12[8]; 741 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */ 742 u32 rqueue; /* 0x.314 - Receive queue control register */ 743 u32 rir0; /* 0x.318 - Ring mapping register 0 */ 744 u32 rir1; /* 0x.31c - Ring mapping register 1 */ 745 u32 rir2; /* 0x.320 - Ring mapping register 2 */ 746 u32 rir3; /* 0x.324 - Ring mapping register 3 */ 747 u8 res13[8]; 748 u32 rbifx; /* 0x.330 - Receive bit field extract control register */ 749 u32 rqfar; /* 0x.334 - Receive queue filing table address register */ 750 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */ 751 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */ 752 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */ 753 u8 res14[56]; 754 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */ 755 u8 res15a[4]; 756 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */ 757 u8 res15b[4]; 758 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */ 759 u8 res15c[4]; 760 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */ 761 u8 res15d[4]; 762 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */ 763 u8 res15e[4]; 764 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */ 765 u8 res15f[4]; 766 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */ 767 u8 res15g[4]; 768 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */ 769 u8 res15h[4]; 770 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */ 771 u8 res16[64]; 772 u32 rbaseh; /* 0x.400 - RxBD base address high */ 773 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */ 774 u8 res17a[4]; 775 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */ 776 u8 res17b[4]; 777 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */ 778 u8 res17c[4]; 779 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */ 780 u8 res17d[4]; 781 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */ 782 u8 res17e[4]; 783 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */ 784 u8 res17f[4]; 785 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */ 786 u8 res17g[4]; 787 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */ 788 u8 res17[192]; 789 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */ 790 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */ 791 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */ 792 u32 hafdup; /* 0x.50c - Half Duplex Register */ 793 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */ 794 u8 res18[12]; 795 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */ 796 u32 ifctrl; /* 0x.538 - Interface control register */ 797 u32 ifstat; /* 0x.53c - Interface Status Register */ 798 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */ 799 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */ 800 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */ 801 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */ 802 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */ 803 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */ 804 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */ 805 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */ 806 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */ 807 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */ 808 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */ 809 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */ 810 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */ 811 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */ 812 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */ 813 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */ 814 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */ 815 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */ 816 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */ 817 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */ 818 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/ 819 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/ 820 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/ 821 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/ 822 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/ 823 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/ 824 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/ 825 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/ 826 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/ 827 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/ 828 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/ 829 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/ 830 u8 res20[192]; 831 struct rmon_mib rmon; /* 0x.680-0x.73c */ 832 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */ 833 u8 res21[188]; 834 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/ 835 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/ 836 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/ 837 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/ 838 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/ 839 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/ 840 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/ 841 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/ 842 u8 res22[96]; 843 u32 gaddr0; /* 0x.880 - Group address register 0 */ 844 u32 gaddr1; /* 0x.884 - Group address register 1 */ 845 u32 gaddr2; /* 0x.888 - Group address register 2 */ 846 u32 gaddr3; /* 0x.88c - Group address register 3 */ 847 u32 gaddr4; /* 0x.890 - Group address register 4 */ 848 u32 gaddr5; /* 0x.894 - Group address register 5 */ 849 u32 gaddr6; /* 0x.898 - Group address register 6 */ 850 u32 gaddr7; /* 0x.89c - Group address register 7 */ 851 u8 res23a[352]; 852 u32 fifocfg; /* 0x.a00 - FIFO interface config register */ 853 u8 res23b[252]; 854 u8 res23c[248]; 855 u32 attr; /* 0x.bf8 - Attributes Register */ 856 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */ 857 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */ 858 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */ 859 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */ 860 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */ 861 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */ 862 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */ 863 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */ 864 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */ 865 u8 res24[36]; 866 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */ 867 u8 res24a[4]; 868 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */ 869 u8 res24b[4]; 870 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */ 871 u8 res24c[4]; 872 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */ 873 u8 res24d[4]; 874 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */ 875 u8 res24e[4]; 876 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */ 877 u8 res24f[4]; 878 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */ 879 u8 res24g[4]; 880 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */ 881 u8 res24h[4]; 882 u8 res24x[556]; 883 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */ 884 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */ 885 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */ 886 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */ 887 u8 res25[16]; 888 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */ 889 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */ 890 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */ 891 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */ 892 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */ 893 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */ 894 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */ 895 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */ 896 u8 res26[32]; 897 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */ 898 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */ 899 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */ 900 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */ 901 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */ 902 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */ 903 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */ 904 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */ 905 u8 res27[208]; 906}; 907 908/* Flags related to gianfar device features */ 909#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001 910#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002 911#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004 912#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008 913#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 914#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 915#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 916#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 917#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 918#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 919#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800 920 921#if (MAXGROUPS == 2) 922#define DEFAULT_MAPPING 0xAA 923#else 924#define DEFAULT_MAPPING 0xFF 925#endif 926 927#define ISRG_RR0 0x80000000 928#define ISRG_TR0 0x00800000 929 930/* The same driver can operate in two modes */ 931/* SQ_SG_MODE: Single Queue Single Group Mode 932 * (Backward compatible mode) 933 * MQ_MG_MODE: Multi Queue Multi Group mode 934 */ 935enum { 936 SQ_SG_MODE = 0, 937 MQ_MG_MODE 938}; 939 940/* GFAR_SQ_POLLING: Single Queue NAPI polling mode 941 * The driver supports a single pair of RX/Tx queues 942 * per interrupt group (Rx/Tx int line). MQ_MG mode 943 * devices have 2 interrupt groups, so the device will 944 * have a total of 2 Tx and 2 Rx queues in this case. 945 * GFAR_MQ_POLLING: Multi Queue NAPI polling mode 946 * The driver supports all the 8 Rx and Tx HW queues 947 * each queue mapped by the Device Tree to one of 948 * the 2 interrupt groups. This mode implies significant 949 * processing overhead (CPU and controller level). 950 */ 951enum gfar_poll_mode { 952 GFAR_SQ_POLLING = 0, 953 GFAR_MQ_POLLING 954}; 955 956/* 957 * Per TX queue stats 958 */ 959struct tx_q_stats { 960 unsigned long tx_packets; 961 unsigned long tx_bytes; 962}; 963 964/** 965 * struct gfar_priv_tx_q - per tx queue structure 966 * @txlock: per queue tx spin lock 967 * @tx_skbuff:skb pointers 968 * @skb_curtx: to be used skb pointer 969 * @skb_dirtytx:the last used skb pointer 970 * @stats: bytes/packets stats 971 * @qindex: index of this queue 972 * @dev: back pointer to the dev structure 973 * @grp: back pointer to the group to which this queue belongs 974 * @tx_bd_base: First tx buffer descriptor 975 * @cur_tx: Next free ring entry 976 * @dirty_tx: First buffer in line to be transmitted 977 * @tx_ring_size: Tx ring size 978 * @num_txbdfree: number of free TxBds 979 * @txcoalescing: enable/disable tx coalescing 980 * @txic: transmit interrupt coalescing value 981 * @txcount: coalescing value if based on tx frame count 982 * @txtime: coalescing value if based on time 983 */ 984struct gfar_priv_tx_q { 985 /* cacheline 1 */ 986 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES))); 987 struct txbd8 *tx_bd_base; 988 struct txbd8 *cur_tx; 989 unsigned int num_txbdfree; 990 unsigned short skb_curtx; 991 unsigned short tx_ring_size; 992 struct tx_q_stats stats; 993 struct gfar_priv_grp *grp; 994 /* cacheline 2 */ 995 struct net_device *dev; 996 struct sk_buff **tx_skbuff; 997 struct txbd8 *dirty_tx; 998 unsigned short skb_dirtytx; 999 unsigned short qindex; 1000 /* Configuration info for the coalescing features */ 1001 unsigned int txcoalescing; 1002 unsigned long txic; 1003 dma_addr_t tx_bd_dma_base; 1004}; 1005 1006/* 1007 * Per RX queue stats 1008 */ 1009struct rx_q_stats { 1010 unsigned long rx_packets; 1011 unsigned long rx_bytes; 1012 unsigned long rx_dropped; 1013}; 1014 1015/** 1016 * struct gfar_priv_rx_q - per rx queue structure 1017 * @rx_skbuff: skb pointers 1018 * @skb_currx: currently use skb pointer 1019 * @rx_bd_base: First rx buffer descriptor 1020 * @cur_rx: Next free rx ring entry 1021 * @qindex: index of this queue 1022 * @dev: back pointer to the dev structure 1023 * @rx_ring_size: Rx ring size 1024 * @rxcoalescing: enable/disable rx-coalescing 1025 * @rxic: receive interrupt coalescing vlaue 1026 */ 1027 1028struct gfar_priv_rx_q { 1029 struct sk_buff **rx_skbuff __aligned(SMP_CACHE_BYTES); 1030 dma_addr_t rx_bd_dma_base; 1031 struct rxbd8 *rx_bd_base; 1032 struct rxbd8 *cur_rx; 1033 struct net_device *dev; 1034 struct gfar_priv_grp *grp; 1035 struct rx_q_stats stats; 1036 u16 skb_currx; 1037 u16 qindex; 1038 unsigned int rx_ring_size; 1039 /* RX Coalescing values */ 1040 unsigned char rxcoalescing; 1041 unsigned long rxic; 1042 u32 __iomem *rfbptr; 1043}; 1044 1045enum gfar_irqinfo_id { 1046 GFAR_TX = 0, 1047 GFAR_RX = 1, 1048 GFAR_ER = 2, 1049 GFAR_NUM_IRQS = 3 1050}; 1051 1052struct gfar_irqinfo { 1053 unsigned int irq; 1054 char name[GFAR_INT_NAME_MAX]; 1055}; 1056 1057/** 1058 * struct gfar_priv_grp - per group structure 1059 * @napi: the napi poll function 1060 * @priv: back pointer to the priv structure 1061 * @regs: the ioremapped register space for this group 1062 * @irqinfo: TX/RX/ER irq data for this group 1063 */ 1064 1065struct gfar_priv_grp { 1066 spinlock_t grplock __aligned(SMP_CACHE_BYTES); 1067 struct napi_struct napi_rx; 1068 struct napi_struct napi_tx; 1069 struct gfar __iomem *regs; 1070 struct gfar_priv_tx_q *tx_queue; 1071 struct gfar_priv_rx_q *rx_queue; 1072 unsigned int tstat; 1073 unsigned int rstat; 1074 1075 struct gfar_private *priv; 1076 unsigned long num_tx_queues; 1077 unsigned long tx_bit_map; 1078 unsigned long num_rx_queues; 1079 unsigned long rx_bit_map; 1080 1081 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS]; 1082}; 1083 1084#define gfar_irq(grp, ID) \ 1085 ((grp)->irqinfo[GFAR_##ID]) 1086 1087enum gfar_errata { 1088 GFAR_ERRATA_74 = 0x01, 1089 GFAR_ERRATA_76 = 0x02, 1090 GFAR_ERRATA_A002 = 0x04, 1091 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */ 1092}; 1093 1094enum gfar_dev_state { 1095 GFAR_DOWN = 1, 1096 GFAR_RESETTING 1097}; 1098 1099/* Struct stolen almost completely (and shamelessly) from the FCC enet source 1100 * (Ok, that's not so true anymore, but there is a family resemblance) 1101 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base 1102 * and tx_bd_base always point to the currently available buffer. 1103 * The dirty_tx tracks the current buffer that is being sent by the 1104 * controller. The cur_tx and dirty_tx are equal under both completely 1105 * empty and completely full conditions. The empty/ready indicator in 1106 * the buffer descriptor determines the actual condition. 1107 */ 1108struct gfar_private { 1109 struct device *dev; 1110 struct net_device *ndev; 1111 enum gfar_errata errata; 1112 unsigned int rx_buffer_size; 1113 1114 u16 uses_rxfcb; 1115 u16 padding; 1116 u32 device_flags; 1117 1118 /* HW time stamping enabled flag */ 1119 int hwts_rx_en; 1120 int hwts_tx_en; 1121 1122 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS]; 1123 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS]; 1124 struct gfar_priv_grp gfargrp[MAXGROUPS]; 1125 1126 unsigned long state; 1127 1128 unsigned short mode; 1129 unsigned short poll_mode; 1130 unsigned int num_tx_queues; 1131 unsigned int num_rx_queues; 1132 unsigned int num_grps; 1133 int tx_actual_en; 1134 1135 /* Network Statistics */ 1136 struct gfar_extra_stats extra_stats; 1137 1138 /* PHY stuff */ 1139 phy_interface_t interface; 1140 struct device_node *phy_node; 1141 struct device_node *tbi_node; 1142 struct phy_device *phydev; 1143 struct mii_bus *mii_bus; 1144 int oldspeed; 1145 int oldduplex; 1146 int oldlink; 1147 1148 /* Bitfield update lock */ 1149 spinlock_t bflock; 1150 1151 uint32_t msg_enable; 1152 1153 struct work_struct reset_task; 1154 1155 struct platform_device *ofdev; 1156 unsigned char 1157 extended_hash:1, 1158 bd_stash_en:1, 1159 rx_filer_enable:1, 1160 /* Wake-on-LAN enabled */ 1161 wol_en:1, 1162 /* Enable priorty based Tx scheduling in Hw */ 1163 prio_sched_en:1, 1164 /* Flow control flags */ 1165 pause_aneg_en:1, 1166 tx_pause_en:1, 1167 rx_pause_en:1; 1168 1169 /* The total tx and rx ring size for the enabled queues */ 1170 unsigned int total_tx_ring_size; 1171 unsigned int total_rx_ring_size; 1172 1173 u32 rqueue; 1174 u32 tqueue; 1175 1176 /* RX per device parameters */ 1177 unsigned int rx_stash_size; 1178 unsigned int rx_stash_index; 1179 1180 u32 cur_filer_idx; 1181 1182 /* RX queue filer rule set*/ 1183 struct ethtool_rx_list rx_list; 1184 struct mutex rx_queue_access; 1185 1186 /* Hash registers and their width */ 1187 u32 __iomem *hash_regs[16]; 1188 int hash_width; 1189 1190 /*Filer table*/ 1191 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1192 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1193}; 1194 1195 1196static inline int gfar_has_errata(struct gfar_private *priv, 1197 enum gfar_errata err) 1198{ 1199 return priv->errata & err; 1200} 1201 1202static inline u32 gfar_read(unsigned __iomem *addr) 1203{ 1204 u32 val; 1205 val = ioread32be(addr); 1206 return val; 1207} 1208 1209static inline void gfar_write(unsigned __iomem *addr, u32 val) 1210{ 1211 iowrite32be(val, addr); 1212} 1213 1214static inline void gfar_write_filer(struct gfar_private *priv, 1215 unsigned int far, unsigned int fcr, unsigned int fpr) 1216{ 1217 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1218 1219 gfar_write(®s->rqfar, far); 1220 gfar_write(®s->rqfcr, fcr); 1221 gfar_write(®s->rqfpr, fpr); 1222} 1223 1224static inline void gfar_read_filer(struct gfar_private *priv, 1225 unsigned int far, unsigned int *fcr, unsigned int *fpr) 1226{ 1227 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1228 1229 gfar_write(®s->rqfar, far); 1230 *fcr = gfar_read(®s->rqfcr); 1231 *fpr = gfar_read(®s->rqfpr); 1232} 1233 1234static inline void gfar_write_isrg(struct gfar_private *priv) 1235{ 1236 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1237 u32 __iomem *baddr = ®s->isrg0; 1238 u32 isrg = 0; 1239 int grp_idx, i; 1240 1241 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1242 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx]; 1243 1244 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) { 1245 isrg |= (ISRG_RR0 >> i); 1246 } 1247 1248 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) { 1249 isrg |= (ISRG_TR0 >> i); 1250 } 1251 1252 gfar_write(baddr, isrg); 1253 1254 baddr++; 1255 isrg = 0; 1256 } 1257} 1258 1259static inline int gfar_is_dma_stopped(struct gfar_private *priv) 1260{ 1261 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1262 1263 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) == 1264 (IEVENT_GRSC | IEVENT_GTSC)); 1265} 1266 1267static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv) 1268{ 1269 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1270 1271 return gfar_read(®s->ievent) & IEVENT_GRSC; 1272} 1273 1274static inline void gfar_wmb(void) 1275{ 1276#if defined(CONFIG_PPC) 1277 /* The powerpc-specific eieio() is used, as wmb() has too strong 1278 * semantics (it requires synchronization between cacheable and 1279 * uncacheable mappings, which eieio() doesn't provide and which we 1280 * don't need), thus requiring a more expensive sync instruction. At 1281 * some point, the set of architecture-independent barrier functions 1282 * should be expanded to include weaker barriers. 1283 */ 1284 eieio(); 1285#else 1286 wmb(); /* order write acesses for BD (or FCB) fields */ 1287#endif 1288} 1289 1290static inline void gfar_clear_txbd_status(struct txbd8 *bdp) 1291{ 1292 u32 lstatus = be32_to_cpu(bdp->lstatus); 1293 1294 lstatus &= BD_LFLAG(TXBD_WRAP); 1295 bdp->lstatus = cpu_to_be32(lstatus); 1296} 1297 1298irqreturn_t gfar_receive(int irq, void *dev_id); 1299int startup_gfar(struct net_device *dev); 1300void stop_gfar(struct net_device *dev); 1301void reset_gfar(struct net_device *dev); 1302void gfar_mac_reset(struct gfar_private *priv); 1303void gfar_halt(struct gfar_private *priv); 1304void gfar_start(struct gfar_private *priv); 1305void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, 1306 u32 regnum, u32 read); 1307void gfar_configure_coalescing_all(struct gfar_private *priv); 1308int gfar_set_features(struct net_device *dev, netdev_features_t features); 1309 1310extern const struct ethtool_ops gfar_ethtool_ops; 1311 1312#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX)) 1313 1314#define RQFCR_PID_PRI_MASK 0xFFFFFFF8 1315#define RQFCR_PID_L4P_MASK 0xFFFFFF00 1316#define RQFCR_PID_VID_MASK 0xFFFFF000 1317#define RQFCR_PID_PORT_MASK 0xFFFF0000 1318#define RQFCR_PID_MAC_MASK 0xFF000000 1319 1320struct gfar_mask_entry { 1321 unsigned int mask; /* The mask value which is valid form start to end */ 1322 unsigned int start; 1323 unsigned int end; 1324 unsigned int block; /* Same block values indicate depended entries */ 1325}; 1326 1327/* Represents a receive filer table entry */ 1328struct gfar_filer_entry { 1329 u32 ctrl; 1330 u32 prop; 1331}; 1332 1333 1334/* The 20 additional entries are a shadow for one extra element */ 1335struct filer_table { 1336 u32 index; 1337 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20]; 1338}; 1339 1340/* The gianfar_ptp module will set this variable */ 1341extern int gfar_phc_index; 1342 1343#endif /* __GIANFAR_H */ 1344