Home
last modified time | relevance | path

Searched refs:MHz (Results 1 – 198 of 198) sorted by relevance

/linux-4.1.27/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
Ds3fb.txt39 lower pixclocks (maximum usually between 50-60 MHz, depending on specific
40 hardware, i get best results from plain S3 Trio32 card - about 75 MHz). This
Dmatroxfb.txt271 maxclk:X - maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
301 83 MHz on G200
302 66 MHz on Millennium I
303 60 MHz on Millennium II
308 + my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
309 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
310 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
340 faster, it is kernel-space only time on P-II/350 MHz, Millennium I in 33 MHz
Dvt8623fb.txt29 lower pixclocks (maximum about 100 MHz). This limitation is not enforced by
Darkfb.txt30 lower pixclocks (i got maximum about 70 MHz, it is dependent on specific
Dsstfb.txt101 gfxclk=x gfxclk:x Force graphic clock frequency (in MHz).
106 75MHz for Voodoo 2.
Dframebuffer.txt174 dotclock in the graphics board. For a dotclock of e.g. 28.37516 MHz (millions
274 xfree: in MHz
Duvesafb.txt137 maxclk:n Maximum pixel clock (in MHz).
/linux-4.1.27/arch/arm/boot/dts/
Dintegratorcp.dts22 /* The codec chrystal operates at 24.576 MHz */
38 /* This is a 25MHz chrystal on the base board */
45 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
60 /* 24 MHz chrystal on the core module */
69 * to drive video circuitry. Driven from the 24MHz clock.
77 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
86 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
102 /* TIMER0 runs directly on the 25MHz chrystal */
108 /* TIMER1 runs @ 1MHz */
114 /* TIMER2 runs @ 1MHz */
Ddove-cubox.dts51 /* 25MHz reference crystal */
88 /* connect xtal input to 25MHz reference */
Dste-nomadik-stn8815.dtsi171 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
181 * The 2.4 MHz TIMCLK reference clock is active at
182 * boot time, this is actually the MXTALCLK @19.2 MHz
194 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
217 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
527 clocks = <&clk48>; /* 48 MHz not ULPI */
617 /* Stated as "48 MHz not ULPI clock" */
Dintegratorap.dts22 /* 24 MHz chrystal on the core module */
37 /* The UART clock is 14.74 MHz divided by an ICS525 */
Dversatile-ab.dts43 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
Dexynos4210-trats.dts437 /* Corresponds to 800MHz at freq_table */
441 /* Corresponds to 200MHz at freq_table */
Dexynos4412-odroid-common.dtsi449 /* Corresponds to 800MHz at freq_table */
453 /* Corresponds to 200MHz at freq_table */
Dimx6qdl-microsom-ar8035.dtsi64 /* GPIO16 -> AR8035 25MHz */
Dsun4i-a10-olinuxino-lime.dts63 * when running at 1008 MHz
Dvexpress-v2p-ca9.dts77 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
Dstih407-clock.dtsi16 * Fixed 30MHz oscillator inputs to SoC
Dstih410-clock.dtsi18 * Fixed 30MHz oscillator inputs to SoC
Darmada-xp.dtsi254 /* 25 MHz reference crystal */
Dstih418-clock.dtsi18 * Fixed 30MHz oscillator inputs to SoC
Dexynos5250.dtsi268 /* Corresponds to 800MHz at freq_table */
272 /* Corresponds to 200MHz at freq_table */
Dvexpress-v2m-rs1.dtsi254 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
Dvexpress-v2m.dtsi253 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
Dimx6dl-riotboard.dts391 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
Dhisi-x5hd2.dtsi53 * The rate is fixed in 24MHz.
Dvexpress-v2p-ca15_a7.dts198 /* Reference 24MHz clock */
Dtegra30-apalis.dtsi548 /* 3.25 MHz ADC clock speed */
Dstih415-clock.dtsi18 * Fixed 30MHz oscillator input to SoC
Dexynos4412-trats2.dts935 /* Corresponds to 800MHz at freq_table */
939 /* Corresponds to 200MHz at freq_table */
Darmada-375.dtsi74 /* 25 MHz reference crystal */
Darmada-38x.dtsi591 /* 25 MHz reference crystal */
Dstih416-clock.dtsi19 * Fixed 30MHz oscillator inputs to SoC
Dsun6i-a31.dtsi605 * data lines in GMII mode run at 125MHz and
Dtegra124-nyan-blaze-emc.dtsi54 /* TODO: Add 528MHz frequency */
Dtegra124-nyan-big-emc.dtsi54 /* TODO: Add 528MHz frequency */
/linux-4.1.27/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
Daxp20x.txt17 (range: 750-1875). Default: 1.5MHz
/linux-4.1.27/Documentation/frv/
Dclock.txt42 Clock-In: 50.00 MHz
43 Clock-Core: 300.00 MHz
44 Clock-SDRAM: 100.00 MHz
45 Clock-CBus: 100.00 MHz
46 Clock-Res: 50.00 MHz
47 Clock-Ext: 50.00 MHz
48 Clock-DSU: 25.00 MHz
/linux-4.1.27/Documentation/devicetree/bindings/regulator/
Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
/linux-4.1.27/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/linux-4.1.27/drivers/staging/sm750fb/
Dddk750_chip.c91 return MHz(130); in getChipClock()
145 if (frequency > MHz(336)) in setMemoryClock()
146 frequency = MHz(336); in setMemoryClock()
193 if (frequency > MHz(190)) in setMasterClock()
194 frequency = MHz(190); in setMasterClock()
296 setChipClock(MHz((unsigned int)pInitParam->chipClock)); in ddk750_initHw()
299 setMemoryClock(MHz(pInitParam->memClock)); in ddk750_initHw()
302 setMasterClock(MHz(pInitParam->masterClock)); in ddk750_initHw()
Dsm750_help.h106 #define MHz(x) ((x) * 1000000) macro
/linux-4.1.27/arch/mips/jazz/
DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
19 This is a machine with a R4000 100 MHz CPU. To compile a Linux
30 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dmicrel.txt23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
Drockchip-dwmac.txt23 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
25 PHY provides the reference clock(50MHz), "output" means GMAC provides the
Dfsl-tsec-phy.txt102 TimerOsc = selected reference clock MHz
104 NominalFreq = 1000 / tclk_period MHz
107 OutputClock = NominalFreq / tmr_prsc MHz
Dqca-qca7000-spi.txt44 spi-max-frequency = <8000000>; /* freq: 8 MHz */
Dsti-dwmac.txt21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
/linux-4.1.27/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt14 - st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
/linux-4.1.27/arch/powerpc/boot/dts/
Dmedia5200.dts33 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
34 bus-frequency = <132000000>; // 132 MHz
35 clock-frequency = <396000000>; // 396 MHz
44 bus-frequency = <132000000>;// 132 MHz
Dgamecube.dts39 clock-frequency = <486000000>; /* 486MHz */
40 bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
41 timebase-frequency = <40500000>; /* 162MHz / 4 */
Dmpc5125twr.dts43 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
44 bus-frequency = <198000000>; // 198 MHz csb bus
45 clock-frequency = <396000000>; // 396 MHz ppc core
76 bus-frequency = <66000000>; // 66 MHz ips bus
Dwii.dts48 clock-frequency = <729000000>; /* 729MHz */
49 bus-frequency = <243000000>; /* 243MHz core-to-bus 3x */
50 timebase-frequency = <60750000>; /* 243MHz / 4 */
Dac14xx.dts30 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
31 bus-frequency = <160000000>; /* 160 MHz csb bus */
32 clock-frequency = <400000000>; /* 400 MHz ppc core */
149 bus-frequency = <80000000>; /* 80 MHz ips bus */
Dc2k.dts37 clock-frequency = <996000000>; /* 996 MHz */
38 bus-frequency = <166666667>; /* 166.6666 MHz */
39 timebase-frequency = <41666667>; /* 166.6666/4 MHz */
57 clock-frequency = <166666667>; /* 166.66... MHz */
Dtaishan.dts37 clock-frequency = <800000000>; // 800MHz
124 clock-frequency = <160000000>; // 160MHz
172 clock-frequency = <80000000>; // 80MHz
180 clock-frequency = <80000000>; // 80MHz
Dmpc5121.dtsi39 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
40 bus-frequency = <198000000>; /* 198 MHz csb bus */
41 clock-frequency = <396000000>; /* 396 MHz ppc core */
101 bus-frequency = <66000000>; /* 66 MHz ips bus */
Dmpc8540ads.dts42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // 166 MHz
44 clock-frequency = <0>; // 825 MHz, from uboot
Dmpc8555cds.dts42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // 166 MHz
44 clock-frequency = <0>; // 825 MHz, from uboot
Dstxssa8555.dts41 timebase-frequency = <0>; // 33 MHz, from uboot
42 bus-frequency = <0>; // 166 MHz
43 clock-frequency = <0>; // 825 MHz, from uboot
Dmpc8541cds.dts42 timebase-frequency = <0>; // 33 MHz, from uboot
43 bus-frequency = <0>; // 166 MHz
44 clock-frequency = <0>; // 825 MHz, from uboot
Dsbc8548-post.dtsi231 /* IDSEL 0x01 (PCI-X slot) @66MHz */
237 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
Damigaone.dts33 timebase-frequency = <0>; // 33.3 MHz, from U-boot
Dmpc7448hpc2.dts42 timebase-frequency = <0>; // 33 MHz, from uboot
Dmpc8641_hpcn_36b.dts42 timebase-frequency = <0>; // 33 MHz, from uboot
53 timebase-frequency = <0>; // 33 MHz, from uboot
Dksi8560.dts237 clock-frequency = <165000000>; /* 166MHz */
/linux-4.1.27/arch/arm/mach-pxa/
Dsleep.S66 @ with core operating above 91 MHz
103 @ about suspending with PXBus operating above 133MHz
123 orrne r7, r7, #1 @@ 99.53MHz
150 @ need 6 13-MHz cycles before changing PWRMODE
151 @ just set frequency to 91-MHz... 6*91/13 = 42
/linux-4.1.27/arch/powerpc/boot/
Dprpmc2800.c27 #define MHz (1000U*1000U) macro
28 #define GHz (1000U*MHz)
99 .core_speed = 733*MHz,
138 .core_speed = 733*MHz,
203 .core_speed = 733*MHz,
242 .core_speed = 733*MHz,
268 .core_speed = 733*MHz,
/linux-4.1.27/Documentation/arm/sunxi/
Dclocks.txt7 Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
10 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
17 24MHz 32kHz
/linux-4.1.27/Documentation/scsi/
Daic7xxx.txt21 aic7770 10 EISA/VL 10MHz 16Bit 4 1
22 aic7850 10 PCI/32 10MHz 8Bit 3
23 aic7855 10 PCI/32 10MHz 8Bit 3
24 aic7856 10 PCI/32 10MHz 8Bit 3
25 aic7859 10 PCI/32 20MHz 8Bit 3
26 aic7860 10 PCI/32 20MHz 8Bit 3
27 aic7870 10 PCI/32 10MHz 16Bit 16
28 aic7880 10 PCI/32 20MHz 16Bit 16
29 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
30 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
Daic79xx.txt24 AIC-7901A Single Channel 64-bit PCI-X 133MHz to
26 AIC-7901B Single Channel 64-bit PCI-X 133MHz to
28 AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to
30 AIC-7902B Dual Channel 64-bit PCI-X 133MHz to
35 Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B
38 Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B
41 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
44 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
48 Adaptec SCSI Card 29320 Single Channel 64-bit PCI-X 133MHz to 7901A
52 Adaptec SCSI Card 29320A Single Channel 64-bit PCI-X 133MHz to 7901B
[all …]
D53c700.txt54 53c700 - 25MHz
55 53c700-66 - 50MHz
99 Set to the clock speed of the chip in MHz.
Dtmscsim.txt104 One more warning: I used to overclock my PCI bus to 41.67 MHz. My Tekram
107 MHz PCI bus works for me, though, but I don't recommend using higher clocks
108 than the 33.33 MHz being in the PCI spec.
115 * Sync speed up to 10 MHz
174 (1 / 112 ns = 8.9 MHz). At least in theory. The driver is able to adjust the
177 10 MHz corresp. to a min. NegoPeriod of 100 ns.
225 10 MHz. It's useless to specify both NegoPeriod and SyncSpeed as
289 0..7 mean 10, 8.0, 6.7, 5.7, 5.0, 4.0, 3.1 and 2 MHz resp. Default is
290 0 (10.0 MHz).
330 would set the adapter ID to 6, max. speed to 6.7 MHz, enable all device
DChangeLog.sym53c8xx77 ULTRA3 -> 160 MHz, ULTRA2 -> 80 MHz otherwise 40 MHz.
238 that overclocked PCI BUS up to 48 MHz will not be refused.
344 result is greater than 37 MHz. Since the precision of the
Dsym53c8xx_2.txt84 33 MHz and 66MHz Ultra-3 controllers. The new driver is named `sym'.
149 * Chip supports 33MHz and 66MHz PCI bus clock.
421 This option allows you to specify the frequency in MHz the driver
Dncr53c8xx.txt176 * Chip supports 33MHz and 66MHz PCI buses.
580 This option allows you to specify the frequency in MHz the driver
1359 The first table corresponds to Ultra chips 53875 and 53C860 with 80 MHz
/linux-4.1.27/Documentation/cpu-freq/
Dcpufreq-nforce2.txt13 min_fsb defaults to FSB at boot time - 50 MHz.
17 booting with 200 MHz, 150 should always work.
Dpcc-cpufreq.txt133 pcc-cpufreq: (v1.00.00) driver loaded with frequency limits: 1600 MHz, 2933
134 MHz
137 between the limits (1600 MHz, and 2933 MHz) specified in the message.
184 In this example, the nominal frequency is 2933 MHz. The driver obtains the
187 54% of 2933 MHz = 1583 MHz
Dgovernors.txt173 when ondemand governor would have targeted 1000 MHz, it will target
174 1000 MHz - (10% of 1000 MHz) = 900 MHz instead. This is set to 0
/linux-4.1.27/Documentation/dvb/
Davermedia.txt168 ABC VHF 12 226.5 MHz
169 TEN VHF 11 219.5 MHz
170 NINE VHF 8 191.625 MHz
171 SEVEN VHF 6 177.5 MHz
172 SBS UHF 29 536.5 MHz
184 T 226500000 7MHz 2/3 NONE QAM64 8k 1/8 NONE
185 T 191625000 7MHz 2/3 NONE QAM64 8k 1/8 NONE
186 T 219500000 7MHz 2/3 NONE QAM64 8k 1/8 NONE
187 T 177500000 7MHz 2/3 NONE QAM64 8k 1/8 NONE
188 T 536500000 7MHz 2/3 NONE QAM64 8k 1/8 NONE
/linux-4.1.27/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.txt8 "core" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
Dusb-nop-xceiv.txt39 and expects that clock to be configured to 19.2MHz by the NOP PHY driver.
/linux-4.1.27/Documentation/devicetree/bindings/clock/st/
Dst,quadfs.txt5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
/linux-4.1.27/drivers/ata/
Dpata_hpt37x.c822 static const int MHz[4] = { 33, 40, 50, 66 }; in hpt37x_init_one() local
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1021 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
1036 chip_table->name, MHz[clock_slot]); in hpt37x_init_one()
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dsilabs,si5351.txt56 /* 25MHz reference crystal */
73 /* connect xtal input to 25MHz reference */
86 * - set initial clock frequency of 74.25MHz
Dpwm-clock.txt25 pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
Darm-integrator.txt5 This is a configurable clock fed from a 24 MHz chrystal,
Dsunxi.txt96 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
186 * The first clock must be fixed at 25MHz;
187 * the second clock must be fixed at 125MHz
Dvf610-clock.txt17 - fxosc (external crystal oscillator 24MHz, recommended)
Dst,nomadik.txt18 i.e. the driver output for the main (~19.2 MHz) chrystal,
Dzynq-7000.txt19 (usually 33 MHz oscillators are used for Zynq platforms)
Dat91-clock.txt229 e.g. output = <0 133000000>; <=> 0 to 133MHz.
290 e.g. input = <1 32000000>; <=> 1 to 32MHz.
/linux-4.1.27/Documentation/video4linux/
DREADME.saa713456 - 32.11 MHz -> .audio_clock=0x187de7
57 - 24.576MHz -> .audio_clock=0x200000
Dvivid.txt319 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
320 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
321 will be in color for the +/- 0.25 MHz around it, and in grayscale for
322 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
323 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
327 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
328 a valid channel frequency. When the frequency is within +/- 0.25 MHz of the
344 interlaced, for pixelclock frequencies between 25 and 600 MHz. The field
398 interlaced, for pixelclock frequencies between 25 and 600 MHz. The field
450 FM: 64 MHz - 108 MHz
[all …]
Dsi4713.txt54 Frequency: 1408000 (88.000000 MHz)
59 Frequency range : 76.0 MHz - 108.0 MHz
Dradiotrack.txt27 broadcast TV channels, situated just below and above the 87.0-109.0 MHz range.
39 more or less limited from 87.0 to 109.0 MHz (the commercial FM broadcast
DCARDLIST.bttv164 163 -> Bt848 Capture 14MHz
/linux-4.1.27/drivers/clk/pxa/
Dclk-pxa3xx.c27 #define MHz (1000 * 1000) macro
288 13 * MHz); in pxa3xx_register_plls()
294 120 * MHz); in pxa3xx_register_plls()
Dclk-pxa27x.c24 #define MHz (1000 * 1000) macro
212 13 * MHz); in pxa27x_register_plls()
Dclk-pxa25x.c27 #define MHz (1000 * 1000) macro
/linux-4.1.27/Documentation/devicetree/bindings/timer/
Dallwinner,sun4i-timer.txt8 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
Dmarvell,armada-370-xp-timer.txt23 "fixed" (Reference 25 MHz fixed-clock).
/linux-4.1.27/drivers/video/fbdev/
Dimsttfb.c438 setclkMHz(struct imstt_par *par, __u32 MHz) in setclkMHz() argument
454 if (x == MHz) in setclkMHz()
456 if (x > MHz) { in setclkMHz()
459 } else if (spilled && x < MHz) { in setclkMHz()
473 __u32 MHz, hes, heb, veb, htp, vtp; in compute_imstt_regvals_ibm() local
478 MHz = 30 /* .25 */ ; in compute_imstt_regvals_ibm()
482 MHz = 57 /* .27_ */ ; in compute_imstt_regvals_ibm()
486 MHz = 80; in compute_imstt_regvals_ibm()
490 MHz = 101 /* .6_ */ ; in compute_imstt_regvals_ibm()
494 MHz = yres == 960 ? 126 : 135; in compute_imstt_regvals_ibm()
[all …]
/linux-4.1.27/Documentation/spi/
Dep93xx_spi70 * We use 10 MHz even though the maximum is 7.4 MHz. The driver
Dspi-summary13 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
/linux-4.1.27/Documentation/i2c/busses/
Di2c-ali15x345 100MHz CPU Front Side bus
46 * "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
60 with host bus up to 83.3 MHz.
Di2c-ocores56 .clock_khz = 50000, /* input clock of 50MHz */
/linux-4.1.27/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dts535 /* 12MHz, 24MHz and 48MHz allowed */
560 /* 12MHz, 24MHz and 48MHz allowed */
Docteon_68xx.dts590 /* 12MHz, 24MHz and 48MHz allowed */
/linux-4.1.27/Documentation/devicetree/bindings/mtd/
Dspear_smi.txt25 clock-rate = <50000000>; /* 50MHz */
/linux-4.1.27/arch/arm/mach-moxart/
DKconfig13 192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Des8328.txt12 - clocks : A 22.5792 or 11.2896 MHz clock
/linux-4.1.27/Documentation/devicetree/bindings/ata/
Dexynos-sata.txt10 - samsung,sata-freq : <frequency in MHz>
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dsi4713.txt4 supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog
Dsamsung-s5k6a3.txt24 specified default 24 MHz value will be used.
Dsamsung-s5k5baf.txt24 specified default 24 MHz value will be used.
Dsamsung-mipi-csis.txt24 value when this property is not specified is 166 MHz;
Dsamsung-s5c73m3.txt34 specified default 24 MHz value will be used.
/linux-4.1.27/Documentation/blockdev/
DREADME.DAC960102 233MHz StrongARM SA 110 Processor
103 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots)
108 233MHz StrongARM SA 110 Processor
109 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots)
114 100MHz Intel i960RN RISC Processor
115 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots)
120 100MHz Intel i960RM RISC Processor
125 100MHz Intel i960RS RISC Processor
131 233MHz StrongARM SA 110 Processor
132 64 Bit 33MHz PCI (backward compatible with 32 Bit PCI slots)
[all …]
/linux-4.1.27/drivers/gpu/drm/gma500/
Dpsb_device.c47 #define MHz 1000000 macro
88 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; in psb_backlight_setup()
Doaktrail_device.c58 #define MHz 1000000 macro
126 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; in device_backlight_init()
Dmdfld_device.c33 #define MHz 1000000 macro
/linux-4.1.27/Documentation/devicetree/bindings/mmc/
Dsdhci-st.txt41 - max-frequency: Can be 200MHz, 100Mz or 50MHz (default) and used for
Ddavinci_mmc.txt15 - max-frequency: Maximum operating clock frequency, default 25MHz.
Dsynopsys-dw-mshc.txt70 * supports-highspeed (DEPRECATED): Enables support for high speed cards (up to 50MHz)
/linux-4.1.27/Documentation/devicetree/bindings/watchdog/
Dmarvel.txt30 "fixed" (Reference 25 MHz fixed-clock).
/linux-4.1.27/Documentation/devicetree/bindings/input/
Dti,nspire-keypad.txt11 - scan-interval: How often to scan in us. Based on a APB speed of 33MHz, the
/linux-4.1.27/drivers/media/tuners/
Dmxl5007t.c66 #define MHz 1000000 macro
435 dig_rf_freq = rf_freq / MHz; in mxl5007t_calc_rf_tune_regs()
437 temp = rf_freq % MHz; in mxl5007t_calc_rf_tune_regs()
/linux-4.1.27/Documentation/devicetree/bindings/net/can/
Dcc770.txt22 value of 16000000 (16 MHz) is used.
Dsja1000.txt22 of 16000000 (16 MHz) is used.
/linux-4.1.27/Documentation/timers/
Dhpet.txt8 Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
Dtimekeeping.txt75 Since a 32-bit counter at say 100 MHz will wrap around to zero after some 43
/linux-4.1.27/Documentation/hwmon/
Dadm102197 era (with 400 MHz FSB) had chips with only one temperature sensor.
110 didn't have these sensors. Next generations of Xeon processors (533 MHz
/linux-4.1.27/arch/alpha/
DKconfig216 floor-standing tower system which originally used a 150MHz 21064 It
356 group. It uses the 21066 processor running at 166MHz or 233MHz. It
403 bool "EV56 CPU (speed >= 366MHz)?" if ALPHA_ALCOR
407 prompt "EV56 CPU (speed >= 333MHz)?"
411 prompt "EV56 CPU (speed >= 400MHz)?"
452 bool "EV67 (or later) CPU (speed > 600MHz)?" if ALPHA_DP264 || ALPHA_EIGER
/linux-4.1.27/arch/arm/mach-s3c24xx/
DKconfig408 Indicate that the build needs to support 12MHz system
414 Indicate that the build needs to support 16.9344MHz system
422 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
429 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
/linux-4.1.27/Documentation/i2c/
Dsummary6 extension (3.4 MHz). It provides an inexpensive bus for connecting many
/linux-4.1.27/Documentation/arm/Samsung-S3C24XX/
DS3C2412.txt9 to 266MHz (see data-sheet for more information)
DSuspend.txt120 and the size of memory. For an 64Mbyte RAM area on an 200MHz
/linux-4.1.27/Documentation/video4linux/bttv/
DInsmod-options17 1: 28 MHz crystal installed
18 2: 35 MHz crystal installed
DCards375 (3) Daughterboard M118-A w/ pic 16c54 and 4 MHz quartz
/linux-4.1.27/Documentation/devicetree/bindings/spi/
Dqcom,spi-qup.txt6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
/linux-4.1.27/Documentation/sound/alsa/soc/
DDAI.txt11 The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
/linux-4.1.27/arch/cris/arch-v10/lib/
Ddram_init.S61 and.d 0x1000, $r3 ; 50 or 100 MHz?
/linux-4.1.27/Documentation/
Dsmsc_ece1099.txt56 supports BC-Link speeds up to 24MHz.
Dbus-virt-phys-mapping.txt178 might find yourself with a 500 MHz Alpha in front of you, and then you'll be
Dkprobes.txt635 i386: Intel Pentium M, 1495 MHz, 2957.31 bogomips
638 x86_64: AMD Opteron 246, 1994 MHz, 3971.48 bogomips
641 ppc64: POWER5 (gr), 1656 MHz (SMT disabled, 1 virtual CPU per physical CPU)
/linux-4.1.27/tools/power/cpupower/po/
Dde.po69 msgid "Average Frequency (including boost) in MHz"
489 " lesbarer Form (MHz, GHz; us, ms)\n"
612 "3. FREQuencies can be passed in Hz, kHz (default), MHz, GHz, or THz\n"
614 " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
621 "3. FREQuenzen k�nnen in Hz, kHz (Standard), MHz, GHz oder THz eingegeben\n"
624 " (FREQuenz in kHz =^ MHz * 1000 =^ GHz * 1000000).\n"
Dfr.po69 msgid "Average Frequency (including boost) in MHz"
483 " pour les options -f, -w et -s (MHz, GHz)\n"
600 "3. FREQuencies can be passed in Hz, kHz (default), MHz, GHz, or THz\n"
602 " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
609 " les valeurs par hz, kHz (par d�faut), MHz, GHz ou THz\n"
610 " (kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
Dcs.po72 msgid "Average Frequency (including boost) in MHz"
602 "3. FREQuencies can be passed in Hz, kHz (default), MHz, GHz, or THz\n"
604 " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
611 "3. Frekvence (FREQ) mohou být zadány v Hz, kHz (výchozí), MHz, GHz nebo THz\n"
613 " (FREQ v kHz =^ Hz * 0,001 = ^ MHz * 1000 =^ GHz * 1000000)\n"
Dit.po69 msgid "Average Frequency (including boost) in MHz"
607 "3. FREQuencies can be passed in Hz, kHz (default), MHz, GHz, or THz\n"
609 " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
616 "3. le FREQuenze possono essere specuficate in Hz, kHz (default), MHz, GHz, "
619 " (FREQuenza in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
Dpt.po67 msgid "Average Frequency (including boost) in MHz"
609 "3. FREQuencies can be passed in Hz, kHz (default), MHz, GHz, or THz\n"
611 " (FREQuency in kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
618 "3. FREQuências podem ser usadas em Hz, kHz (padrão), MHz, GHz, o THz\n"
620 " (FREQuência em kHz =^ Hz * 0.001 =^ MHz * 1000 =^ GHz * 1000000).\n"
/linux-4.1.27/arch/unicore32/kernel/
Dsleep.S87 @ set PLL_DDR_CFG reg, 66MHz
/linux-4.1.27/arch/m32r/platforms/mappi/
Ddot.gdbinit.smp168 # 20MHz
171 # 40MHz
/linux-4.1.27/drivers/net/wireless/mwifiex/
DREADME44 iw dev mlan0 connect -w <SSID> [<freq in MHz>] [<bssid>] [key 0:abcde d:1123456789a]
54 iw dev mlan0 ibss join <SSID> <freq in MHz> [fixed-freq] [fixed-bssid] [key 0:abcde]
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
DKconfig121 Max FCK is 173MHz, so this doesn't work if your PCK
/linux-4.1.27/Documentation/arm/
DSetup120 0-66 MHz. If no params are passed or a value of zero is passed,
/linux-4.1.27/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard.dtsi188 max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
/linux-4.1.27/Documentation/networking/
Ds2io.txt29 eth4: Device is on 64 bit 133MHz PCIX(M1) bus
Dcxgb.txt191 eth#: Chelsio N210 1x10GBaseX NIC (rev #), PCIX 133MHz/64-bit
288 section 56, "133-MHz Mode Split Completion Data Corruption" for more
Dcs89x0.txt302 significantly more efficient. Flooding a 400 MHz Celeron machine
Darcnet-hardware.txt1795 XTL 20 MHz Crystal
1946 XTAL 20 MHz Crystal
2078 XTAL 20 MHz Crystal
Dcan.txt963 @133MHz with four SJA1000 CAN controllers from 2002 under heavy bus
/linux-4.1.27/firmware/keyspan_pda/
Dkeyspan_pda.S291 ;; (xtal 12MHz, internal fosc 24MHz)
344 djnz r1, renum_wait1 ; wait about n*(256^2) 6MHz clocks
Dxircom_pgs.S329 ;; (xtal 12MHz, internal fosc 24MHz)
382 djnz r1, renum_wait1 ; wait about n*(256^2) 6MHz clocks
/linux-4.1.27/Documentation/power/
Dopp.txt32 {300MHz at minimum voltage of 1V}, {800MHz at minimum voltage of 1.2V},
/linux-4.1.27/Documentation/cris/
DREADME60 The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB
/linux-4.1.27/arch/m68k/q40/
DREADME80 The Q40 consists of a 68040@40 MHz, 1MB video RAM, up to 32MB RAM, AT-style
/linux-4.1.27/Documentation/x86/
Dearlyprintk.txt22 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
/linux-4.1.27/Documentation/virtual/kvm/
Dtimekeeping.txt41 or PIT. The PIT has a fixed frequency 1.193182 MHz base clock and three
57 | 1.1932 MHz |---------->| CLOCK OUT | ---------> IRQ 0
221 000 = 4.194 MHz
222 001 = 1.049 MHz
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_ddi.c1135 wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); in skl_ddi_calculate_wrpll()
1138 wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); in skl_ddi_calculate_wrpll()
Dintel_drv.h72 #define MHz(x) KHz(1000 * (x)) macro
Dintel_display.c5777 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; in ironlake_fdi_compute_config()
/linux-4.1.27/arch/powerpc/platforms/85xx/
DKconfig112 MHz and 1600 DMIPS, additional functionality and faster interfaces
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
DKconfig74 100MHz clock and SDR mode.
/linux-4.1.27/drivers/scsi/aic7xxx/
Daic79xx.reg2747 * 960MHz Phase-Locked Loop Control 0
2774 * 960MHz Phase-Locked Loop Control 1
2815 * 960-MHz Phase-Locked Loop Test Count
2825 * 400-MHz Phase-Locked Loop Control 0
2851 * 400-MHz Phase-Locked Loop Control 1
2873 * 400-MHz Phase-Locked Loop Test Count
/linux-4.1.27/arch/cris/arch-v32/
DKconfig178 100MHz clock and SDR mode.
/linux-4.1.27/Documentation/usb/
DWUSB-Design-overview.txt62 ~-41dB (or 0.074 uW/MHz--geography specific data is still being
65 subbands/subchannels (528 MHz each). Each channel is independent of each
/linux-4.1.27/Documentation/sound/alsa/
Dtimestamping.txt59 HDAudio 24MHz or PTP clock for networked solutions) or indirectly
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dfman.txt387 be used, if different from the standard 2.5 MHz.
/linux-4.1.27/arch/xtensa/
DKconfig320 int "CPU clock rate [MHz]"
/linux-4.1.27/Documentation/arm/OMAP/
DDSS294 of 86.5MHz (max possible), and with that you get 1280x1024@57 output from DVI.
/linux-4.1.27/arch/arm/mm/
DKconfig279 is available at five speeds ranging from 100 MHz to 233 MHz.
/linux-4.1.27/Documentation/devicetree/bindings/thermal/
Dthermal.txt209 * cooling state is 3, which means only the lowest OPPs (198MHz@0.85V)
/linux-4.1.27/drivers/leds/
DKconfig74 The LM3642 is a 4MHz fixed-frequency synchronous boost
/linux-4.1.27/drivers/misc/
DKconfig68 TC block with a 5+ MHz base clock rate. Two timer channels
/linux-4.1.27/arch/x86/math-emu/
DREADME172 measured on a 33MHz 386 with 64k cache. The Turbo C tests were under
/linux-4.1.27/drivers/spi/
DKconfig445 mode supports up to 50MHz, up to four chip selects, programmable
/linux-4.1.27/drivers/regulator/
DKconfig371 phase operates at a 2MHz fixed frequency with a 120 deg shift
/linux-4.1.27/sound/pci/
DKconfig165 Digital Enhanced Game Port, 1.024MHz multimedia sequencer timer,
/linux-4.1.27/arch/blackfin/
DKconfig1266 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
/linux-4.1.27/Documentation/m68k/
Dkernel-options.txt827 x = clock input in MHz for WD33c93 chip. Normal values would be from
/linux-4.1.27/arch/x86/
DKconfig2363 tristate "NatSemi SCx200 27MHz High-Resolution Timer Support"
2368 27MHz high-resolution timer. Its also a workaround for
/linux-4.1.27/drivers/watchdog/
DKconfig241 signal, so with reasonably fast systems (PCLK around 50-66MHz)
/linux-4.1.27/drivers/eisa/
Deisa.ids398 CPQFD13 "Compaq 15MHz ESDI Fixed Disk Controller 001283"
/linux-4.1.27/arch/mips/
DKconfig1976 int "Count/Compare Timer Frequency (MHz)"
/linux-4.1.27/drivers/scsi/
DKconfig1185 int "synchronous transfers frequency in MHz"