1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2008-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "MPC8641HPCN";
16	compatible = "fsl,mpc8641hpcn";
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		ethernet2 = &enet2;
24		ethernet3 = &enet3;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		pci0 = &pci0;
28		pci1 = &pci1;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		PowerPC,8641@0 {
36			device_type = "cpu";
37			reg = <0>;
38			d-cache-line-size = <32>;	// 32 bytes
39			i-cache-line-size = <32>;	// 32 bytes
40			d-cache-size = <32768>;		// L1, 32K
41			i-cache-size = <32768>;		// L1, 32K
42			timebase-frequency = <0>;	// 33 MHz, from uboot
43			bus-frequency = <0>;		// From uboot
44			clock-frequency = <0>;		// From uboot
45		};
46		PowerPC,8641@1 {
47			device_type = "cpu";
48			reg = <1>;
49			d-cache-line-size = <32>;	// 32 bytes
50			i-cache-line-size = <32>;	// 32 bytes
51			d-cache-size = <32768>;		// L1, 32K
52			i-cache-size = <32768>;		// L1, 32K
53			timebase-frequency = <0>;	// 33 MHz, from uboot
54			bus-frequency = <0>;		// From uboot
55			clock-frequency = <0>;		// From uboot
56		};
57	};
58
59	memory {
60		device_type = "memory";
61		reg = <0x0 0x00000000 0x0 0x40000000>;	// 1G at 0x0
62	};
63
64	localbus@fffe05000 {
65		#address-cells = <2>;
66		#size-cells = <1>;
67		compatible = "fsl,mpc8641-localbus", "simple-bus";
68		reg = <0x0f 0xffe05000 0x0 0x1000>;
69		interrupts = <19 2>;
70		interrupt-parent = <&mpic>;
71
72		ranges = <0 0 0xf 0xef800000 0x00800000
73			  2 0 0xf 0xffdf8000 0x00008000
74			  3 0 0xf 0xffdf0000 0x00008000>;
75
76		flash@0,0 {
77			compatible = "cfi-flash";
78			reg = <0 0 0x00800000>;
79			bank-width = <2>;
80			device-width = <2>;
81			#address-cells = <1>;
82			#size-cells = <1>;
83			partition@0 {
84				label = "kernel";
85				reg = <0x00000000 0x00300000>;
86			};
87			partition@300000 {
88				label = "firmware b";
89				reg = <0x00300000 0x00100000>;
90				read-only;
91			};
92			partition@400000 {
93				label = "fs";
94				reg = <0x00400000 0x00300000>;
95			};
96			partition@700000 {
97				label = "firmware a";
98				reg = <0x00700000 0x00100000>;
99				read-only;
100			};
101		};
102	};
103
104	soc8641@fffe00000 {
105		#address-cells = <1>;
106		#size-cells = <1>;
107		device_type = "soc";
108		compatible = "simple-bus";
109		ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
110		bus-frequency = <0>;
111
112		mcm-law@0 {
113			compatible = "fsl,mcm-law";
114			reg = <0x0 0x1000>;
115			fsl,num-laws = <10>;
116		};
117
118		mcm@1000 {
119			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120			reg = <0x1000 0x1000>;
121			interrupts = <17 2>;
122			interrupt-parent = <&mpic>;
123		};
124
125		i2c@3000 {
126			#address-cells = <1>;
127			#size-cells = <0>;
128			cell-index = <0>;
129			compatible = "fsl-i2c";
130			reg = <0x3000 0x100>;
131			interrupts = <43 2>;
132			interrupt-parent = <&mpic>;
133			dfsrr;
134		};
135
136		i2c@3100 {
137			#address-cells = <1>;
138			#size-cells = <0>;
139			cell-index = <1>;
140			compatible = "fsl-i2c";
141			reg = <0x3100 0x100>;
142			interrupts = <43 2>;
143			interrupt-parent = <&mpic>;
144			dfsrr;
145		};
146
147		dma@21300 {
148			#address-cells = <1>;
149			#size-cells = <1>;
150			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
151			reg = <0x21300 0x4>;
152			ranges = <0x0 0x21100 0x200>;
153			cell-index = <0>;
154			dma-channel@0 {
155				compatible = "fsl,mpc8641-dma-channel",
156						"fsl,eloplus-dma-channel";
157				reg = <0x0 0x80>;
158				cell-index = <0>;
159				interrupt-parent = <&mpic>;
160				interrupts = <20 2>;
161			};
162			dma-channel@80 {
163				compatible = "fsl,mpc8641-dma-channel",
164						"fsl,eloplus-dma-channel";
165				reg = <0x80 0x80>;
166				cell-index = <1>;
167				interrupt-parent = <&mpic>;
168				interrupts = <21 2>;
169			};
170			dma-channel@100 {
171				compatible = "fsl,mpc8641-dma-channel",
172						"fsl,eloplus-dma-channel";
173				reg = <0x100 0x80>;
174				cell-index = <2>;
175				interrupt-parent = <&mpic>;
176				interrupts = <22 2>;
177			};
178			dma-channel@180 {
179				compatible = "fsl,mpc8641-dma-channel",
180						"fsl,eloplus-dma-channel";
181				reg = <0x180 0x80>;
182				cell-index = <3>;
183				interrupt-parent = <&mpic>;
184				interrupts = <23 2>;
185			};
186		};
187
188		enet0: ethernet@24000 {
189			#address-cells = <1>;
190			#size-cells = <1>;
191			cell-index = <0>;
192			device_type = "network";
193			model = "TSEC";
194			compatible = "gianfar";
195			reg = <0x24000 0x1000>;
196			ranges = <0x0 0x24000 0x1000>;
197			local-mac-address = [ 00 00 00 00 00 00 ];
198			interrupts = <29 2 30 2 34 2>;
199			interrupt-parent = <&mpic>;
200			tbi-handle = <&tbi0>;
201			phy-handle = <&phy0>;
202			phy-connection-type = "rgmii-id";
203
204			mdio@520 {
205				#address-cells = <1>;
206				#size-cells = <0>;
207				compatible = "fsl,gianfar-mdio";
208				reg = <0x520 0x20>;
209
210				phy0: ethernet-phy@0 {
211					interrupt-parent = <&mpic>;
212					interrupts = <10 1>;
213					reg = <0>;
214				};
215				phy1: ethernet-phy@1 {
216					interrupt-parent = <&mpic>;
217					interrupts = <10 1>;
218					reg = <1>;
219				};
220				phy2: ethernet-phy@2 {
221					interrupt-parent = <&mpic>;
222					interrupts = <10 1>;
223					reg = <2>;
224				};
225				phy3: ethernet-phy@3 {
226					interrupt-parent = <&mpic>;
227					interrupts = <10 1>;
228					reg = <3>;
229				};
230				tbi0: tbi-phy@11 {
231					reg = <0x11>;
232					device_type = "tbi-phy";
233				};
234			};
235		};
236
237		enet1: ethernet@25000 {
238			#address-cells = <1>;
239			#size-cells = <1>;
240			cell-index = <1>;
241			device_type = "network";
242			model = "TSEC";
243			compatible = "gianfar";
244			reg = <0x25000 0x1000>;
245			ranges = <0x0 0x25000 0x1000>;
246			local-mac-address = [ 00 00 00 00 00 00 ];
247			interrupts = <35 2 36 2 40 2>;
248			interrupt-parent = <&mpic>;
249			tbi-handle = <&tbi1>;
250			phy-handle = <&phy1>;
251			phy-connection-type = "rgmii-id";
252
253			mdio@520 {
254				#address-cells = <1>;
255				#size-cells = <0>;
256				compatible = "fsl,gianfar-tbi";
257				reg = <0x520 0x20>;
258
259				tbi1: tbi-phy@11 {
260					reg = <0x11>;
261					device_type = "tbi-phy";
262				};
263			};
264		};
265
266		enet2: ethernet@26000 {
267			#address-cells = <1>;
268			#size-cells = <1>;
269			cell-index = <2>;
270			device_type = "network";
271			model = "TSEC";
272			compatible = "gianfar";
273			reg = <0x26000 0x1000>;
274			ranges = <0x0 0x26000 0x1000>;
275			local-mac-address = [ 00 00 00 00 00 00 ];
276			interrupts = <31 2 32 2 33 2>;
277			interrupt-parent = <&mpic>;
278			tbi-handle = <&tbi2>;
279			phy-handle = <&phy2>;
280			phy-connection-type = "rgmii-id";
281
282			mdio@520 {
283				#address-cells = <1>;
284				#size-cells = <0>;
285				compatible = "fsl,gianfar-tbi";
286				reg = <0x520 0x20>;
287
288				tbi2: tbi-phy@11 {
289					reg = <0x11>;
290					device_type = "tbi-phy";
291				};
292			};
293		};
294
295		enet3: ethernet@27000 {
296			#address-cells = <1>;
297			#size-cells = <1>;
298			cell-index = <3>;
299			device_type = "network";
300			model = "TSEC";
301			compatible = "gianfar";
302			reg = <0x27000 0x1000>;
303			ranges = <0x0 0x27000 0x1000>;
304			local-mac-address = [ 00 00 00 00 00 00 ];
305			interrupts = <37 2 38 2 39 2>;
306			interrupt-parent = <&mpic>;
307			tbi-handle = <&tbi3>;
308			phy-handle = <&phy3>;
309			phy-connection-type = "rgmii-id";
310
311			mdio@520 {
312				#address-cells = <1>;
313				#size-cells = <0>;
314				compatible = "fsl,gianfar-tbi";
315				reg = <0x520 0x20>;
316
317				tbi3: tbi-phy@11 {
318					reg = <0x11>;
319					device_type = "tbi-phy";
320				};
321			};
322		};
323
324		serial0: serial@4500 {
325			cell-index = <0>;
326			device_type = "serial";
327			compatible = "fsl,ns16550", "ns16550";
328			reg = <0x4500 0x100>;
329			clock-frequency = <0>;
330			interrupts = <42 2>;
331			interrupt-parent = <&mpic>;
332		};
333
334		serial1: serial@4600 {
335			cell-index = <1>;
336			device_type = "serial";
337			compatible = "fsl,ns16550", "ns16550";
338			reg = <0x4600 0x100>;
339			clock-frequency = <0>;
340			interrupts = <28 2>;
341			interrupt-parent = <&mpic>;
342		};
343
344		mpic: pic@40000 {
345			interrupt-controller;
346			#address-cells = <0>;
347			#interrupt-cells = <2>;
348			reg = <0x40000 0x40000>;
349			compatible = "chrp,open-pic";
350			device_type = "open-pic";
351		};
352
353		global-utilities@e0000 {
354			compatible = "fsl,mpc8641-guts";
355			reg = <0xe0000 0x1000>;
356			fsl,has-rstcr;
357		};
358	};
359
360	pci0: pcie@fffe08000 {
361		cell-index = <0>;
362		compatible = "fsl,mpc8641-pcie";
363		device_type = "pci";
364		#interrupt-cells = <1>;
365		#size-cells = <2>;
366		#address-cells = <3>;
367		reg = <0x0f 0xffe08000 0x0 0x1000>;
368		bus-range = <0x0 0xff>;
369		ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
370			  0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
371		clock-frequency = <33333333>;
372		interrupt-parent = <&mpic>;
373		interrupts = <24 2>;
374		interrupt-map-mask = <0xff00 0 0 7>;
375		interrupt-map = <
376			/* IDSEL 0x11 func 0 - PCI slot 1 */
377			0x8800 0 0 1 &mpic 2 1
378			0x8800 0 0 2 &mpic 3 1
379			0x8800 0 0 3 &mpic 4 1
380			0x8800 0 0 4 &mpic 1 1
381
382			/* IDSEL 0x11 func 1 - PCI slot 1 */
383			0x8900 0 0 1 &mpic 2 1
384			0x8900 0 0 2 &mpic 3 1
385			0x8900 0 0 3 &mpic 4 1
386			0x8900 0 0 4 &mpic 1 1
387
388			/* IDSEL 0x11 func 2 - PCI slot 1 */
389			0x8a00 0 0 1 &mpic 2 1
390			0x8a00 0 0 2 &mpic 3 1
391			0x8a00 0 0 3 &mpic 4 1
392			0x8a00 0 0 4 &mpic 1 1
393
394			/* IDSEL 0x11 func 3 - PCI slot 1 */
395			0x8b00 0 0 1 &mpic 2 1
396			0x8b00 0 0 2 &mpic 3 1
397			0x8b00 0 0 3 &mpic 4 1
398			0x8b00 0 0 4 &mpic 1 1
399
400			/* IDSEL 0x11 func 4 - PCI slot 1 */
401			0x8c00 0 0 1 &mpic 2 1
402			0x8c00 0 0 2 &mpic 3 1
403			0x8c00 0 0 3 &mpic 4 1
404			0x8c00 0 0 4 &mpic 1 1
405
406			/* IDSEL 0x11 func 5 - PCI slot 1 */
407			0x8d00 0 0 1 &mpic 2 1
408			0x8d00 0 0 2 &mpic 3 1
409			0x8d00 0 0 3 &mpic 4 1
410			0x8d00 0 0 4 &mpic 1 1
411
412			/* IDSEL 0x11 func 6 - PCI slot 1 */
413			0x8e00 0 0 1 &mpic 2 1
414			0x8e00 0 0 2 &mpic 3 1
415			0x8e00 0 0 3 &mpic 4 1
416			0x8e00 0 0 4 &mpic 1 1
417
418			/* IDSEL 0x11 func 7 - PCI slot 1 */
419			0x8f00 0 0 1 &mpic 2 1
420			0x8f00 0 0 2 &mpic 3 1
421			0x8f00 0 0 3 &mpic 4 1
422			0x8f00 0 0 4 &mpic 1 1
423
424			/* IDSEL 0x12 func 0 - PCI slot 2 */
425			0x9000 0 0 1 &mpic 3 1
426			0x9000 0 0 2 &mpic 4 1
427			0x9000 0 0 3 &mpic 1 1
428			0x9000 0 0 4 &mpic 2 1
429
430			/* IDSEL 0x12 func 1 - PCI slot 2 */
431			0x9100 0 0 1 &mpic 3 1
432			0x9100 0 0 2 &mpic 4 1
433			0x9100 0 0 3 &mpic 1 1
434			0x9100 0 0 4 &mpic 2 1
435
436			/* IDSEL 0x12 func 2 - PCI slot 2 */
437			0x9200 0 0 1 &mpic 3 1
438			0x9200 0 0 2 &mpic 4 1
439			0x9200 0 0 3 &mpic 1 1
440			0x9200 0 0 4 &mpic 2 1
441
442			/* IDSEL 0x12 func 3 - PCI slot 2 */
443			0x9300 0 0 1 &mpic 3 1
444			0x9300 0 0 2 &mpic 4 1
445			0x9300 0 0 3 &mpic 1 1
446			0x9300 0 0 4 &mpic 2 1
447
448			/* IDSEL 0x12 func 4 - PCI slot 2 */
449			0x9400 0 0 1 &mpic 3 1
450			0x9400 0 0 2 &mpic 4 1
451			0x9400 0 0 3 &mpic 1 1
452			0x9400 0 0 4 &mpic 2 1
453
454			/* IDSEL 0x12 func 5 - PCI slot 2 */
455			0x9500 0 0 1 &mpic 3 1
456			0x9500 0 0 2 &mpic 4 1
457			0x9500 0 0 3 &mpic 1 1
458			0x9500 0 0 4 &mpic 2 1
459
460			/* IDSEL 0x12 func 6 - PCI slot 2 */
461			0x9600 0 0 1 &mpic 3 1
462			0x9600 0 0 2 &mpic 4 1
463			0x9600 0 0 3 &mpic 1 1
464			0x9600 0 0 4 &mpic 2 1
465
466			/* IDSEL 0x12 func 7 - PCI slot 2 */
467			0x9700 0 0 1 &mpic 3 1
468			0x9700 0 0 2 &mpic 4 1
469			0x9700 0 0 3 &mpic 1 1
470			0x9700 0 0 4 &mpic 2 1
471
472			// IDSEL 0x1c  USB
473			0xe000 0 0 1 &i8259 12 2
474			0xe100 0 0 2 &i8259 9 2
475			0xe200 0 0 3 &i8259 10 2
476			0xe300 0 0 4 &i8259 11 2
477
478			// IDSEL 0x1d  Audio
479			0xe800 0 0 1 &i8259 6 2
480
481			// IDSEL 0x1e Legacy
482			0xf000 0 0 1 &i8259 7 2
483			0xf100 0 0 1 &i8259 7 2
484
485			// IDSEL 0x1f IDE/SATA
486			0xf800 0 0 1 &i8259 14 2
487			0xf900 0 0 1 &i8259 5 2
488			>;
489
490		pcie@0 {
491			reg = <0 0 0 0 0>;
492			#size-cells = <2>;
493			#address-cells = <3>;
494			device_type = "pci";
495			ranges = <0x02000000 0x0 0xe0000000
496				  0x02000000 0x0 0xe0000000
497				  0x0 0x20000000
498
499				  0x01000000 0x0 0x00000000
500				  0x01000000 0x0 0x00000000
501				  0x0 0x00010000>;
502			uli1575@0 {
503				reg = <0 0 0 0 0>;
504				#size-cells = <2>;
505				#address-cells = <3>;
506				ranges = <0x02000000 0x0 0xe0000000
507					  0x02000000 0x0 0xe0000000
508					  0x0 0x20000000
509					  0x01000000 0x0 0x00000000
510					  0x01000000 0x0 0x00000000
511					  0x0 0x00010000>;
512				isa@1e {
513					device_type = "isa";
514					#interrupt-cells = <2>;
515					#size-cells = <1>;
516					#address-cells = <2>;
517					reg = <0xf000 0 0 0 0>;
518					ranges = <1 0 0x01000000 0 0
519						  0x00001000>;
520					interrupt-parent = <&i8259>;
521
522					i8259: interrupt-controller@20 {
523						reg = <1 0x20 2
524						       1 0xa0 2
525						       1 0x4d0 2>;
526						interrupt-controller;
527						device_type = "interrupt-controller";
528						#address-cells = <0>;
529						#interrupt-cells = <2>;
530						compatible = "chrp,iic";
531						interrupts = <9 2>;
532						interrupt-parent = <&mpic>;
533					};
534
535					i8042@60 {
536						#size-cells = <0>;
537						#address-cells = <1>;
538						reg = <1 0x60 1 1 0x64 1>;
539						interrupts = <1 3 12 3>;
540						interrupt-parent =
541							<&i8259>;
542
543						keyboard@0 {
544							reg = <0>;
545							compatible = "pnpPNP,303";
546						};
547
548						mouse@1 {
549							reg = <1>;
550							compatible = "pnpPNP,f03";
551						};
552					};
553
554					rtc@70 {
555						compatible =
556							"pnpPNP,b00";
557						reg = <1 0x70 2>;
558					};
559
560					gpio@400 {
561						reg = <1 0x400 0x80>;
562					};
563				};
564			};
565		};
566
567	};
568
569	pci1: pcie@fffe09000 {
570		cell-index = <1>;
571		compatible = "fsl,mpc8641-pcie";
572		device_type = "pci";
573		#interrupt-cells = <1>;
574		#size-cells = <2>;
575		#address-cells = <3>;
576		reg = <0x0f 0xffe09000 0x0 0x1000>;
577		bus-range = <0x0 0xff>;
578		ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
579			  0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
580		clock-frequency = <33333333>;
581		interrupt-parent = <&mpic>;
582		interrupts = <25 2>;
583		interrupt-map-mask = <0xf800 0 0 7>;
584		interrupt-map = <
585			/* IDSEL 0x0 */
586			0x0000 0 0 1 &mpic 4 1
587			0x0000 0 0 2 &mpic 5 1
588			0x0000 0 0 3 &mpic 6 1
589			0x0000 0 0 4 &mpic 7 1
590			>;
591		pcie@0 {
592			reg = <0 0 0 0 0>;
593			#size-cells = <2>;
594			#address-cells = <3>;
595			device_type = "pci";
596			ranges = <0x02000000 0x0 0xe0000000
597				  0x02000000 0x0 0xe0000000
598				  0x0 0x20000000
599
600				  0x01000000 0x0 0x00000000
601				  0x01000000 0x0 0x00000000
602				  0x0 0x00010000>;
603		};
604	};
605};
606