1/*
2 * Marvell PXA3xxx family clocks
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
13 * should go away.
14 */
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/of.h>
20#include <mach/smemc.h>
21#include <mach/pxa3xx-regs.h>
22
23#include <dt-bindings/clock/pxa-clock.h>
24#include "clk-pxa.h"
25
26#define KHz 1000
27#define MHz (1000 * 1000)
28
29enum {
30	PXA_CORE_60Mhz = 0,
31	PXA_CORE_RUN,
32	PXA_CORE_TURBO,
33};
34
35enum {
36	PXA_BUS_60Mhz = 0,
37	PXA_BUS_HSS,
38};
39
40/* crystal frequency to HSIO bus frequency multiplier (HSS) */
41static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
42
43/* crystal frequency to static memory controller multiplier (SMCFS) */
44static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
45static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
46
47static const char * const get_freq_khz[] = {
48	"core", "ring_osc_60mhz", "run", "cpll", "system_bus"
49};
50
51/*
52 * Get the clock frequency as reflected by ACSR and the turbo flag.
53 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings.
55 */
56unsigned int pxa3xx_get_clk_frequency_khz(int info)
57{
58	struct clk *clk;
59	unsigned long clks[5];
60	int i;
61
62	for (i = 0; i < 5; i++) {
63		clk = clk_get(NULL, get_freq_khz[i]);
64		if (IS_ERR(clk)) {
65			clks[i] = 0;
66		} else {
67			clks[i] = clk_get_rate(clk);
68			clk_put(clk);
69		}
70	}
71	if (info) {
72		pr_info("RO Mode clock: %ld.%02ldMHz\n",
73			clks[1] / 1000000, (clks[0] % 1000000) / 10000);
74		pr_info("Run Mode clock: %ld.%02ldMHz\n",
75			clks[2] / 1000000, (clks[1] % 1000000) / 10000);
76		pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
77			clks[3] / 1000000, (clks[2] % 1000000) / 10000);
78		pr_info("System bus clock: %ld.%02ldMHz\n",
79			clks[4] / 1000000, (clks[4] % 1000000) / 10000);
80	}
81	return (unsigned int)clks[0] / KHz;
82}
83
84static unsigned long clk_pxa3xx_ac97_get_rate(struct clk_hw *hw,
85					     unsigned long parent_rate)
86{
87	unsigned long ac97_div, rate;
88
89	ac97_div = AC97_DIV;
90
91	/* This may loose precision for some rates but won't for the
92	 * standard 24.576MHz.
93	 */
94	rate = parent_rate / 2;
95	rate /= ((ac97_div >> 12) & 0x7fff);
96	rate *= (ac97_div & 0xfff);
97
98	return rate;
99}
100PARENTS(clk_pxa3xx_ac97) = { "spll_624mhz" };
101RATE_RO_OPS(clk_pxa3xx_ac97, "ac97");
102
103static unsigned long clk_pxa3xx_smemc_get_rate(struct clk_hw *hw,
104					      unsigned long parent_rate)
105{
106	unsigned long acsr = ACSR;
107	unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
108
109	return (parent_rate / 48)  * smcfs_mult[(acsr >> 23) & 0x7] /
110		df_clkdiv[(memclkcfg >> 16) & 0x3];
111}
112PARENTS(clk_pxa3xx_smemc) = { "spll_624mhz" };
113RATE_RO_OPS(clk_pxa3xx_smemc, "smemc");
114
115static bool pxa3xx_is_ring_osc_forced(void)
116{
117	unsigned long acsr = ACSR;
118
119	return acsr & ACCR_D0CS;
120}
121
122PARENTS(pxa3xx_pbus) = { "ring_osc_60mhz", "spll_624mhz" };
123PARENTS(pxa3xx_32Khz_bus) = { "osc_32_768khz", "osc_32_768khz" };
124PARENTS(pxa3xx_13MHz_bus) = { "osc_13mhz", "osc_13mhz" };
125PARENTS(pxa3xx_ac97_bus) = { "ring_osc_60mhz", "ac97" };
126PARENTS(pxa3xx_sbus) = { "ring_osc_60mhz", "system_bus" };
127PARENTS(pxa3xx_smemcbus) = { "ring_osc_60mhz", "smemc" };
128
129#define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? &CKENB : &CKENA)
130#define PXA3XX_CKEN(dev_id, con_id, parents, mult_lp, div_lp, mult_hp,	\
131		    div_hp, bit, is_lp, flags)				\
132	PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp,		\
133		 mult_hp, div_hp, is_lp,  CKEN_AB(bit),			\
134		 (CKEN_ ## bit % 32), flags)
135#define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp,		\
136			 mult_hp, div_hp, delay)			\
137	PXA3XX_CKEN(dev_id, con_id, pxa3xx_pbus_parents, mult_lp,	\
138		    div_lp, mult_hp, div_hp, bit, pxa3xx_is_ring_osc_forced, 0)
139#define PXA3XX_CKEN_1RATE(dev_id, con_id, bit, parents)			\
140	PXA_CKEN_1RATE(dev_id, con_id, bit, parents,			\
141		       CKEN_AB(bit), (CKEN_ ## bit % 32), 0)
142
143static struct desc_clk_cken pxa3xx_clocks[] __initdata = {
144	PXA3XX_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 4, 1, 42, 1),
145	PXA3XX_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 4, 1, 42, 1),
146	PXA3XX_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 4, 1, 42, 1),
147	PXA3XX_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 5, 1, 19, 0),
148	PXA3XX_PBUS_CKEN("pxa27x-udc", NULL, UDC, 1, 4, 1, 13, 5),
149	PXA3XX_PBUS_CKEN("pxa27x-ohci", NULL, USBH, 1, 4, 1, 13, 0),
150	PXA3XX_PBUS_CKEN("pxa3xx-u2d", NULL, USB2, 1, 4, 1, 13, 0),
151	PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
152	PXA3XX_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 6, 1, 48, 0),
153	PXA3XX_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC1, 1, 4, 1, 24, 0),
154	PXA3XX_PBUS_CKEN("pxa2xx-mci.1", NULL, MMC2, 1, 4, 1, 24, 0),
155	PXA3XX_PBUS_CKEN("pxa2xx-mci.2", NULL, MMC3, 1, 4, 1, 24, 0),
156
157	PXA3XX_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
158			  pxa3xx_32Khz_bus_parents),
159	PXA3XX_CKEN_1RATE("pxa3xx-ssp.0", NULL, SSP1, pxa3xx_13MHz_bus_parents),
160	PXA3XX_CKEN_1RATE("pxa3xx-ssp.1", NULL, SSP2, pxa3xx_13MHz_bus_parents),
161	PXA3XX_CKEN_1RATE("pxa3xx-ssp.2", NULL, SSP3, pxa3xx_13MHz_bus_parents),
162	PXA3XX_CKEN_1RATE("pxa3xx-ssp.3", NULL, SSP4, pxa3xx_13MHz_bus_parents),
163
164	PXA3XX_CKEN(NULL, "AC97CLK", pxa3xx_ac97_bus_parents, 1, 4, 1, 1, AC97,
165		    pxa3xx_is_ring_osc_forced, 0),
166	PXA3XX_CKEN(NULL, "CAMCLK", pxa3xx_sbus_parents, 1, 2, 1, 1, CAMERA,
167		    pxa3xx_is_ring_osc_forced, 0),
168	PXA3XX_CKEN("pxa2xx-fb", NULL, pxa3xx_sbus_parents, 1, 1, 1, 1, LCD,
169		    pxa3xx_is_ring_osc_forced, 0),
170	PXA3XX_CKEN("pxa2xx-pcmcia", NULL, pxa3xx_smemcbus_parents, 1, 4,
171		    1, 1, SMC, pxa3xx_is_ring_osc_forced, CLK_IGNORE_UNUSED),
172};
173
174static struct desc_clk_cken pxa300_310_clocks[] __initdata = {
175
176	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
177	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
178	PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
179};
180
181static struct desc_clk_cken pxa320_clocks[] __initdata = {
182	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 6, 0),
183	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA320_GCU, 1, 1, 1, 1, 0),
184	PXA3XX_CKEN_1RATE("pxa3xx-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
185};
186
187static struct desc_clk_cken pxa93x_clocks[] __initdata = {
188
189	PXA3XX_PBUS_CKEN("pxa3xx-gcu", NULL, PXA300_GCU, 1, 1, 1, 1, 0),
190	PXA3XX_PBUS_CKEN("pxa3xx-nand", NULL, NAND, 1, 2, 1, 4, 0),
191	PXA3XX_CKEN_1RATE("pxa93x-gpio", NULL, GPIO, pxa3xx_13MHz_bus_parents),
192};
193
194static unsigned long clk_pxa3xx_system_bus_get_rate(struct clk_hw *hw,
195					    unsigned long parent_rate)
196{
197	unsigned long acsr = ACSR;
198	unsigned int hss = (acsr >> 14) & 0x3;
199
200	if (pxa3xx_is_ring_osc_forced())
201		return parent_rate;
202	return parent_rate / 48 * hss_mult[hss];
203}
204
205static u8 clk_pxa3xx_system_bus_get_parent(struct clk_hw *hw)
206{
207	if (pxa3xx_is_ring_osc_forced())
208		return PXA_BUS_60Mhz;
209	else
210		return PXA_BUS_HSS;
211}
212
213PARENTS(clk_pxa3xx_system_bus) = { "ring_osc_60mhz", "spll_624mhz" };
214MUX_RO_RATE_RO_OPS(clk_pxa3xx_system_bus, "system_bus");
215
216static unsigned long clk_pxa3xx_core_get_rate(struct clk_hw *hw,
217					      unsigned long parent_rate)
218{
219	return parent_rate;
220}
221
222static u8 clk_pxa3xx_core_get_parent(struct clk_hw *hw)
223{
224	unsigned long xclkcfg;
225	unsigned int t;
226
227	if (pxa3xx_is_ring_osc_forced())
228		return PXA_CORE_60Mhz;
229
230	/* Read XCLKCFG register turbo bit */
231	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
232	t = xclkcfg & 0x1;
233
234	if (t)
235		return PXA_CORE_TURBO;
236	return PXA_CORE_RUN;
237}
238PARENTS(clk_pxa3xx_core) = { "ring_osc_60mhz", "run", "cpll" };
239MUX_RO_RATE_RO_OPS(clk_pxa3xx_core, "core");
240
241static unsigned long clk_pxa3xx_run_get_rate(struct clk_hw *hw,
242					     unsigned long parent_rate)
243{
244	unsigned long acsr = ACSR;
245	unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
246	unsigned int t, xclkcfg;
247
248	/* Read XCLKCFG register turbo bit */
249	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
250	t = xclkcfg & 0x1;
251
252	return t ? (parent_rate / xn) * 2 : parent_rate;
253}
254PARENTS(clk_pxa3xx_run) = { "cpll" };
255RATE_RO_OPS(clk_pxa3xx_run, "run");
256
257static unsigned long clk_pxa3xx_cpll_get_rate(struct clk_hw *hw,
258	unsigned long parent_rate)
259{
260	unsigned long acsr = ACSR;
261	unsigned int xn = (acsr & ACCR_XN_MASK) >> 8;
262	unsigned int xl = acsr & ACCR_XL_MASK;
263	unsigned int t, xclkcfg;
264
265	/* Read XCLKCFG register turbo bit */
266	__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
267	t = xclkcfg & 0x1;
268
269	pr_info("RJK: parent_rate=%lu, xl=%u, xn=%u\n", parent_rate, xl, xn);
270	return t ? parent_rate * xl * xn : parent_rate * xl;
271}
272PARENTS(clk_pxa3xx_cpll) = { "osc_13mhz" };
273RATE_RO_OPS(clk_pxa3xx_cpll, "cpll");
274
275static void __init pxa3xx_register_core(void)
276{
277	clk_register_clk_pxa3xx_cpll();
278	clk_register_clk_pxa3xx_run();
279
280	clkdev_pxa_register(CLK_CORE, "core", NULL,
281			    clk_register_clk_pxa3xx_core());
282}
283
284static void __init pxa3xx_register_plls(void)
285{
286	clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
287				CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
288				13 * MHz);
289	clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
290				CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
291				32768);
292	clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
293				CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
294				120 * MHz);
295	clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
296	clk_register_fixed_factor(NULL, "spll_624mhz", "osc_13mhz", 0, 48, 1);
297	clk_register_fixed_factor(NULL, "ring_osc_60mhz", "ring_osc_120mhz",
298				  0, 1, 2);
299}
300
301#define DUMMY_CLK(_con_id, _dev_id, _parent) \
302	{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
303struct dummy_clk {
304	const char *con_id;
305	const char *dev_id;
306	const char *parent;
307};
308static struct dummy_clk dummy_clks[] __initdata = {
309	DUMMY_CLK(NULL, "pxa93x-gpio", "osc_13mhz"),
310	DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
311	DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
312	DUMMY_CLK(NULL, "pxa3xx-pwri2c.1", "osc_13mhz"),
313};
314
315static void __init pxa3xx_dummy_clocks_init(void)
316{
317	struct clk *clk;
318	struct dummy_clk *d;
319	const char *name;
320	int i;
321
322	for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
323		d = &dummy_clks[i];
324		name = d->dev_id ? d->dev_id : d->con_id;
325		clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
326		clk_register_clkdev(clk, d->con_id, d->dev_id);
327	}
328}
329
330static void __init pxa3xx_base_clocks_init(void)
331{
332	pxa3xx_register_plls();
333	pxa3xx_register_core();
334	clk_register_clk_pxa3xx_system_bus();
335	clk_register_clk_pxa3xx_ac97();
336	clk_register_clk_pxa3xx_smemc();
337	clk_register_gate(NULL, "CLK_POUT", "osc_13mhz", 0,
338			  (void __iomem *)&OSCC, 11, 0, NULL);
339	clkdev_pxa_register(CLK_OSTIMER, "OSTIMER0", NULL,
340			    clk_register_fixed_factor(NULL, "os-timer0",
341						      "osc_13mhz", 0, 1, 4));
342}
343
344int __init pxa3xx_clocks_init(void)
345{
346	int ret;
347
348	pxa3xx_base_clocks_init();
349	pxa3xx_dummy_clocks_init();
350	ret = clk_pxa_cken_init(pxa3xx_clocks, ARRAY_SIZE(pxa3xx_clocks));
351	if (ret)
352		return ret;
353	if (cpu_is_pxa320())
354		return clk_pxa_cken_init(pxa320_clocks,
355					 ARRAY_SIZE(pxa320_clocks));
356	if (cpu_is_pxa300() || cpu_is_pxa310())
357		return clk_pxa_cken_init(pxa300_310_clocks,
358					 ARRAY_SIZE(pxa300_310_clocks));
359	return clk_pxa_cken_init(pxa93x_clocks, ARRAY_SIZE(pxa93x_clocks));
360}
361
362static void __init pxa3xx_dt_clocks_init(struct device_node *np)
363{
364	pxa3xx_clocks_init();
365	clk_pxa_dt_common_init(np);
366}
367CLK_OF_DECLARE(pxa_clks, "marvell,pxa300-clocks", pxa3xx_dt_clocks_init);
368