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Searched refs:write_reg (Results 1 – 138 of 138) sorted by relevance

/linux-4.4.14/drivers/staging/fbtft/
Dfb_bd663474.c44 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
48 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
49 write_reg(par, 0x101, 0x0000); in init_display()
50 write_reg(par, 0x102, 0x3110); in init_display()
51 write_reg(par, 0x103, 0xe200); in init_display()
52 write_reg(par, 0x110, 0x009d); in init_display()
53 write_reg(par, 0x111, 0x0022); in init_display()
54 write_reg(par, 0x100, 0x0120); in init_display()
57 write_reg(par, 0x100, 0x3120); in init_display()
60 write_reg(par, 0x001, 0x0100); in init_display()
[all …]
Dfb_upd161704.c44 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
47 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
51 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
53 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
54 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
56 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
57 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
59 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
60 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
62 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ in init_display()
[all …]
Dfb_ili9320.c37 write_reg(par, 0x0000); in read_devicecode()
60 write_reg(par, 0x00E5, 0x8000); in init_display()
63 write_reg(par, 0x0000, 0x0001); in init_display()
66 write_reg(par, 0x0001, 0x0100); in init_display()
69 write_reg(par, 0x0002, 0x0700); in init_display()
72 write_reg(par, 0x0004, 0x0000); in init_display()
75 write_reg(par, 0x0008, 0x0202); in init_display()
78 write_reg(par, 0x0009, 0x0000); in init_display()
81 write_reg(par, 0x000A, 0x0000); in init_display()
84 write_reg(par, 0x000C, 0x0000); in init_display()
[all …]
Dfb_ili9325.c112 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
113 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
114 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
115 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
116 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
117 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
118 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
119 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
120 write_reg(par, 0x000A, 0x0000); /* FMARK function */ in init_display()
121 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ in init_display()
[all …]
Dfb_s6d1121.c46 write_reg(par, 0x0011, 0x2004); in init_display()
47 write_reg(par, 0x0013, 0xCC00); in init_display()
48 write_reg(par, 0x0015, 0x2600); in init_display()
49 write_reg(par, 0x0014, 0x252A); in init_display()
50 write_reg(par, 0x0012, 0x0033); in init_display()
51 write_reg(par, 0x0013, 0xCC04); in init_display()
52 write_reg(par, 0x0013, 0xCC06); in init_display()
53 write_reg(par, 0x0013, 0xCC4F); in init_display()
54 write_reg(par, 0x0013, 0x674F); in init_display()
55 write_reg(par, 0x0011, 0x2003); in init_display()
[all …]
Dfb_ssd1289.c43 write_reg(par, 0x00, 0x0001); in init_display()
44 write_reg(par, 0x03, 0xA8A4); in init_display()
45 write_reg(par, 0x0C, 0x0000); in init_display()
46 write_reg(par, 0x0D, 0x080C); in init_display()
47 write_reg(par, 0x0E, 0x2B00); in init_display()
48 write_reg(par, 0x1E, 0x00B7); in init_display()
49 write_reg(par, 0x01, in init_display()
51 write_reg(par, 0x02, 0x0600); in init_display()
52 write_reg(par, 0x10, 0x0000); in init_display()
53 write_reg(par, 0x05, 0x0000); in init_display()
[all …]
Dfb_hx8347d.c37 write_reg(par, 0xEA, 0x00); in init_display()
38 write_reg(par, 0xEB, 0x20); in init_display()
39 write_reg(par, 0xEC, 0x0C); in init_display()
40 write_reg(par, 0xED, 0xC4); in init_display()
41 write_reg(par, 0xE8, 0x40); in init_display()
42 write_reg(par, 0xE9, 0x38); in init_display()
43 write_reg(par, 0xF1, 0x01); in init_display()
44 write_reg(par, 0xF2, 0x10); in init_display()
45 write_reg(par, 0x27, 0xA3); in init_display()
48 write_reg(par, 0x1B, 0x1B); in init_display()
[all …]
Dfb_ra8875.c68 write_reg(par, 0x88, 0x0A); in init_display()
69 write_reg(par, 0x89, 0x02); in init_display()
72 write_reg(par, 0x10, 0x0C); in init_display()
74 write_reg(par, 0x04, 0x03); in init_display()
77 write_reg(par, 0x14, 0x27); in init_display()
78 write_reg(par, 0x15, 0x00); in init_display()
79 write_reg(par, 0x16, 0x05); in init_display()
80 write_reg(par, 0x17, 0x04); in init_display()
81 write_reg(par, 0x18, 0x03); in init_display()
83 write_reg(par, 0x19, 0xEF); in init_display()
[all …]
Dfb_tinylcd.c32 write_reg(par, 0xB0, 0x80); in init_display()
33 write_reg(par, 0xC0, 0x0A, 0x0A); in init_display()
34 write_reg(par, 0xC1, 0x45, 0x07); in init_display()
35 write_reg(par, 0xC2, 0x33); in init_display()
36 write_reg(par, 0xC5, 0x00, 0x42, 0x80); in init_display()
37 write_reg(par, 0xB1, 0xD0, 0x11); in init_display()
38 write_reg(par, 0xB4, 0x02); in init_display()
39 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); in init_display()
40 write_reg(par, 0xB7, 0x07); in init_display()
41 write_reg(par, 0x36, 0x58); in init_display()
[all …]
Dfb_ili9340.c34 write_reg(par, 0xEF, 0x03, 0x80, 0x02); in init_display()
35 write_reg(par, 0xCF, 0x00, 0XC1, 0X30); in init_display()
36 write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81); in init_display()
37 write_reg(par, 0xE8, 0x85, 0x00, 0x78); in init_display()
38 write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02); in init_display()
39 write_reg(par, 0xF7, 0x20); in init_display()
40 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
43 write_reg(par, 0xC0, 0x23); in init_display()
46 write_reg(par, 0xC1, 0x10); in init_display()
49 write_reg(par, 0xC5, 0x3e, 0x28); in init_display()
[all …]
Dfb_ssd1306.c55 write_reg(par, 0xAE); in init_display()
58 write_reg(par, 0xD5); in init_display()
59 write_reg(par, 0x80); in init_display()
62 write_reg(par, 0xA8); in init_display()
64 write_reg(par, 0x3F); in init_display()
66 write_reg(par, 0x1F); in init_display()
69 write_reg(par, 0xD3); in init_display()
70 write_reg(par, 0x0); in init_display()
73 write_reg(par, 0x40 | 0x0); in init_display()
76 write_reg(par, 0x8D); in init_display()
[all …]
Dfb_ili9341.c42 write_reg(par, 0x01); /* software reset */ in init_display()
44 write_reg(par, 0x28); /* display off */ in init_display()
46 write_reg(par, 0xCF, 0x00, 0x83, 0x30); in init_display()
47 write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81); in init_display()
48 write_reg(par, 0xE8, 0x85, 0x01, 0x79); in init_display()
49 write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02); in init_display()
50 write_reg(par, 0xF7, 0x20); in init_display()
51 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
53 write_reg(par, 0xC0, 0x26); in init_display()
54 write_reg(par, 0xC1, 0x11); in init_display()
[all …]
Dfb_hx8357d.c38 write_reg(par, HX8357B_SWRESET); in init_display()
42 write_reg(par, HX8357D_SETC, 0xFF, 0x83, 0x57); in init_display()
46 write_reg(par, HX8357_SETRGB, 0x00, 0x00, 0x06, 0x06); in init_display()
49 write_reg(par, HX8357D_SETCOM, 0x25); in init_display()
52 write_reg(par, HX8357_SETOSC, 0x68); in init_display()
55 write_reg(par, HX8357_SETPANEL, 0x05); in init_display()
57 write_reg(par, HX8357_SETPWR1, in init_display()
65 write_reg(par, HX8357D_SETSTBA, in init_display()
73 write_reg(par, HX8357D_SETCYC, in init_display()
82 write_reg(par, HX8357D_SETGAMMA, in init_display()
[all …]
Dfb_ssd1351.c36 write_reg(par, 0xfd, 0x12); /* Command Lock */ in init_display()
37 write_reg(par, 0xfd, 0xb1); /* Command Lock */ in init_display()
38 write_reg(par, 0xae); /* Display Off */ in init_display()
39 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */ in init_display()
40 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */ in init_display()
41 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */ in init_display()
42 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */ in init_display()
43 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
44 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
45 write_reg(par, 0xb5, 0x00); /* Set GPIO */ in init_display()
[all …]
Dfb_uc1701.c77 write_reg(par, LCD_RESET_CMD); in init_display()
82 write_reg(par, LCD_START_LINE); in init_display()
85 write_reg(par, LCD_BOTTOMVIEW | 1); in init_display()
87 write_reg(par, LCD_SCAN_DIR | 0x00); in init_display()
90 write_reg(par, LCD_ALL_PIXEL | 0); in init_display()
93 write_reg(par, LCD_DISPLAY_INVERT | 0); in init_display()
96 write_reg(par, LCD_BIAS | 0); in init_display()
100 write_reg(par, LCD_POWER_CONTROL | 0x07); in init_display()
104 write_reg(par, LCD_VOLTAGE | 0x07); in init_display()
108 write_reg(par, LCD_VOLUME_MODE); in init_display()
[all …]
Dfb_ili9163.c116 write_reg(par, CMD_SWRESET); /* software reset */ in init_display()
118 write_reg(par, CMD_SLPOUT); /* exit sleep */ in init_display()
120 write_reg(par, CMD_PIXFMT, 0x05); /* Set Color Format 16bit */ in init_display()
121 write_reg(par, CMD_GAMMASET, 0x02); /* default gamma curve 3 */ in init_display()
123 write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */ in init_display()
125 write_reg(par, CMD_NORML); in init_display()
126 write_reg(par, CMD_DFUNCTR, 0xff, 0x06); in init_display()
128 write_reg(par, CMD_FRMCTR1, 0x08, 0x02); in init_display()
129 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ in init_display()
131 write_reg(par, CMD_PWCTR1, 0x0A, 0x02); in init_display()
[all …]
Dfb_hx8353d.c35 write_reg(par, 0xB9, 0xFF, 0x83, 0x53); in init_display()
38 write_reg(par, 0xB0, 0x3C, 0x01); in init_display()
41 write_reg(par, 0xB6, 0x94, 0x6C, 0x50); in init_display()
44 write_reg(par, 0xB1, 0x00, 0x01, 0x1B, 0x03, 0x01, 0x08, 0x77, 0x89); in init_display()
47 write_reg(par, 0x3A, 0x05); in init_display()
50 write_reg(par, 0x36, 0xC0); in init_display()
53 write_reg(par, 0x11); in init_display()
57 write_reg(par, 0x29); in init_display()
60 write_reg(par, 0x2D, in init_display()
76 write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); in set_addr_win()
[all …]
Dfb_ssd1331.c28 write_reg(par, 0xae); /* Display Off */ in init_display()
29 write_reg(par, 0xa0, 0x70 | (par->bgr << 2)); /* Set Colour Depth */ in init_display()
30 write_reg(par, 0x72); /* RGB colour */ in init_display()
31 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
32 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
33 write_reg(par, 0xa4); /* NORMALDISPLAY */ in init_display()
34 write_reg(par, 0xa8, 0x3f); /* Set multiplex */ in init_display()
35 write_reg(par, 0xad, 0x8e); /* Set master */ in init_display()
37 write_reg(par, 0xb1, 0x31); /* Precharge */ in init_display()
38 write_reg(par, 0xb3, 0xf0); /* Clock div */ in init_display()
[all …]
Dfb_hx8340bn.c51 write_reg(par, 0xC1, 0xFF, 0x83, 0x40); in init_display()
57 write_reg(par, 0x11); in init_display()
61 write_reg(par, 0xCA, 0x70, 0x00, 0xD9); in init_display()
67 write_reg(par, 0xB0, 0x01, 0x11); in init_display()
70 write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06); in init_display()
78 write_reg(par, 0xB5, 0x35, 0x20, 0x45); in init_display()
85 write_reg(par, 0xB4, 0x33, 0x25, 0x4C); in init_display()
92 write_reg(par, 0x3A, 0x05); in init_display()
97 write_reg(par, 0x29); in init_display()
105 write_reg(par, FBTFT_CASET, 0x00, xs, 0x00, xe); in set_addr_win()
[all …]
Dfb_uc1611.c84 write_reg(par, 0xE2); in init_display()
87 write_reg(par, 0xE8 | (ratio & 0x03)); in init_display()
90 write_reg(par, 0x81); in init_display()
91 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F)); in init_display()
94 write_reg(par, 0x24 | (temp & 0x03)); in init_display()
97 write_reg(par, 0x28 | (load & 0x03)); in init_display()
100 write_reg(par, 0x2C | (pump & 0x03)); in init_display()
103 write_reg(par, 0xA6 | (0x01 & 0x01)); in init_display()
106 write_reg(par, 0xD0 | (0x02 & 0x03)); in init_display()
109 write_reg(par, 0xA8 | 0x07); in init_display()
[all …]
Dfb_st7789v.c89 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); in init_display()
93 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); in init_display()
95 write_reg(par, PORCTRL, 0x08, 0x08, 0x00, 0x22, 0x22); in init_display()
101 write_reg(par, GCTRL, 0x35); in init_display()
107 write_reg(par, VDVVRHEN, 0x01, 0xFF); in init_display()
113 write_reg(par, VRHS, 0x0B); in init_display()
116 write_reg(par, VDVS, 0x20); in init_display()
119 write_reg(par, VCOMS, 0x20); in init_display()
122 write_reg(par, VCMOFSET, 0x20); in init_display()
129 write_reg(par, PWCTRL1, 0xA4, 0xA1); in init_display()
[all …]
Dfb_tls8204.c47 write_reg(par, 0x21); /* 5:1 1 in init_display()
55 write_reg(par, 0x10 | (bs & 0x7)); /* in init_display()
64 write_reg(par, 0x04 | (64 >> 6)); in init_display()
65 write_reg(par, 0x40 | (64 & 0x3F)); in init_display()
68 write_reg(par, 0x20); in init_display()
71 write_reg(par, 0x08 | 4); /* in init_display()
84 write_reg(par, 0x80); /* 7:1 1 in set_addr_win()
89 write_reg(par, 0x40); /* 7:0 0 in set_addr_win()
106 write_reg(par, 0x80 | 0); in write_vmem()
107 write_reg(par, 0x40 | y); in write_vmem()
[all …]
Dfb_pcd8544.c54 write_reg(par, 0x21); in init_display()
62 write_reg(par, 0x04 | (tc & 0x3)); in init_display()
72 write_reg(par, 0x10 | (bs & 0x7)); in init_display()
81 write_reg(par, 0x22); in init_display()
90 write_reg(par, 0x08 | 4); in init_display()
102 write_reg(par, 0x80); in set_addr_win()
110 write_reg(par, 0x40); in set_addr_win()
145 write_reg(par, 0x23); /* turn on extended instruction set */ in set_gamma()
146 write_reg(par, 0x80 | curves[0]); in set_gamma()
147 write_reg(par, 0x22); /* turn off extended instruction set */ in set_gamma()
Dfb_ili9486.c60 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); in set_addr_win()
63 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); in set_addr_win()
66 write_reg(par, 0x2C); in set_addr_win()
73 write_reg(par, 0x36, 0x80 | (par->bgr << 3)); in set_var()
76 write_reg(par, 0x36, 0x20 | (par->bgr << 3)); in set_var()
79 write_reg(par, 0x36, 0x40 | (par->bgr << 3)); in set_var()
82 write_reg(par, 0x36, 0xE0 | (par->bgr << 3)); in set_var()
Dfb_ili9481.c57 write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); in set_addr_win()
60 write_reg(par, 0x2b, ys >> 8, ys & 0xff, ye >> 8, ye & 0xff); in set_addr_win()
63 write_reg(par, 0x2c); in set_addr_win()
73 write_reg(par, 0x36, ROWxCOL | HFLIP | VFLIP | (par->bgr << 3)); in set_var()
76 write_reg(par, 0x36, VFLIP | (par->bgr << 3)); in set_var()
79 write_reg(par, 0x36, ROWxCOL | (par->bgr << 3)); in set_var()
82 write_reg(par, 0x36, HFLIP | (par->bgr << 3)); in set_var()
Dfb_s6d02a1.c102 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); in set_addr_win()
105 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); in set_addr_win()
108 write_reg(par, 0x2C); in set_addr_win()
124 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); in set_var()
127 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); in set_var()
130 write_reg(par, 0x36, par->bgr << 3); in set_var()
133 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); in set_var()
Dflexfb.c240 write_reg(par, 0x0020, xs); in flexfb_set_addr_win_1()
241 write_reg(par, 0x0021, ys); in flexfb_set_addr_win_1()
244 write_reg(par, 0x0020, width - 1 - xs); in flexfb_set_addr_win_1()
245 write_reg(par, 0x0021, height - 1 - ys); in flexfb_set_addr_win_1()
248 write_reg(par, 0x0020, width - 1 - ys); in flexfb_set_addr_win_1()
249 write_reg(par, 0x0021, xs); in flexfb_set_addr_win_1()
252 write_reg(par, 0x0020, ys); in flexfb_set_addr_win_1()
253 write_reg(par, 0x0021, height - 1 - xs); in flexfb_set_addr_win_1()
256 write_reg(par, 0x0022); /* Write Data to GRAM */ in flexfb_set_addr_win_1()
267 write_reg(par, 0x4e, xs); in flexfb_set_addr_win_2()
[all …]
Dfb_st7735r.c95 write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF); in set_addr_win()
98 write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF); in set_addr_win()
101 write_reg(par, 0x2C); in set_addr_win()
117 write_reg(par, 0x36, MX | MY | (par->bgr << 3)); in set_var()
120 write_reg(par, 0x36, MY | MV | (par->bgr << 3)); in set_var()
123 write_reg(par, 0x36, par->bgr << 3); in set_var()
126 write_reg(par, 0x36, MX | MV | (par->bgr << 3)); in set_var()
149 write_reg(par, 0xE0 + i, in set_gamma()
Dfb_agm1264k-fl.c80 write_reg(par, i, 0x3f); /* display on */ in init_display()
81 write_reg(par, i, 0x40); /* set x to 0 */ in init_display()
82 write_reg(par, i, 0xb0); /* set page to 0 */ in init_display()
83 write_reg(par, i, 0xc0); /* set start line to 0 */ in init_display()
365 write_reg(par, 0x00, (1 << 6) | (u8)addr_win.xs); in write_vmem()
366 write_reg(par, 0x00, (0x17 << 3) | (u8)y); in write_vmem()
387 write_reg(par, 0x01, 1 << 6); in write_vmem()
388 write_reg(par, 0x01, (0x17 << 3) | (u8)y); in write_vmem()
Dfb_watterott.c144 write_reg(par, CMD_VERSION); in firmware_version()
166 write_reg(par, 0x00); /* make sure mode is set */ in init_display()
177 write_reg(par, 0x00); in init_display()
211 write_reg(par, CMD_LCD_ORIENTATION, rotate); in set_var()
242 write_reg(par, CMD_LCD_LED, brightness); in backlight_chip_update_status()
Dfbtft_device.c1273 write_reg(par, 0x2A, 0, xs + 2, 0, xe + 2); in adafruit18_green_tab_set_addr_win()
1274 write_reg(par, 0x2B, 0, ys + 1, 0, ye + 1); in adafruit18_green_tab_set_addr_win()
1275 write_reg(par, 0x2C); in adafruit18_green_tab_set_addr_win()
Dfbtft.h256 #define write_reg(par, ...) \ macro
Dfbtft-core.c323 write_reg(par, 0x2A, in fbtft_set_addr_win()
327 write_reg(par, 0x2B, in fbtft_set_addr_win()
331 write_reg(par, 0x2C); in fbtft_set_addr_win()
/linux-4.4.14/arch/sh/boards/mach-kfr2r09/
Dlcd_wqvga.c68 static void write_reg(void *sohandle, in write_reg() function
85 write_reg(sohandle, so, 1, data[i]); in write_data()
94 write_reg(sohandle, so, 0, 0xb0); in read_device_code()
95 write_reg(sohandle, so, 1, 0x00); in read_device_code()
98 write_reg(sohandle, so, 0, 0xb1); in read_device_code()
99 write_reg(sohandle, so, 1, 0x00); in read_device_code()
102 write_reg(sohandle, so, 0, 0xbf); in read_device_code()
120 write_reg(sohandle, so, 0, 0x2c); in write_memory_start()
133 write_reg(sohandle, so, 1, 0x00); in clear_memory()
140 write_reg(sohandle, so, 0, 0xb0); in display_on()
[all …]
/linux-4.4.14/drivers/media/pci/ivtv/
Divtv-yuv.c179 write_reg(read_dec(i), 0x02804); in ivtv_yuv_filter()
180 write_reg(read_dec(i), 0x0281c); in ivtv_yuv_filter()
182 write_reg(read_dec(i), 0x02808); in ivtv_yuv_filter()
183 write_reg(read_dec(i), 0x02820); in ivtv_yuv_filter()
185 write_reg(read_dec(i), 0x0280c); in ivtv_yuv_filter()
186 write_reg(read_dec(i), 0x02824); in ivtv_yuv_filter()
188 write_reg(read_dec(i), 0x02810); in ivtv_yuv_filter()
189 write_reg(read_dec(i), 0x02828); in ivtv_yuv_filter()
191 write_reg(read_dec(i), 0x02814); in ivtv_yuv_filter()
192 write_reg(read_dec(i), 0x0282c); in ivtv_yuv_filter()
[all …]
Divtv-gpio.c116 write_reg(curdir, IVTV_REG_GPIO_DIR); in ivtv_reset_ir_gpio()
118 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_ir_gpio()
122 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_ir_gpio()
124 write_reg(curdir, IVTV_REG_GPIO_DIR); in ivtv_reset_ir_gpio()
139 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_tuner_gpio()
143 write_reg(curout, IVTV_REG_GPIO_OUT); in ivtv_reset_tuner_gpio()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_tuner()
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_radio()
256 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_audio_routing()
[all …]
Divtv-firmware.c100 write_reg(IVTV_CMD_VDM_STOP, IVTV_REG_VDM); in ivtv_halt_firmware()
103 write_reg(IVTV_CMD_AO_STOP, IVTV_REG_AO); in ivtv_halt_firmware()
106 write_reg(IVTV_CMD_APU_PING, IVTV_REG_APU); in ivtv_halt_firmware()
110 write_reg(IVTV_CMD_VPU_STOP16, IVTV_REG_VPU); in ivtv_halt_firmware()
112 write_reg(IVTV_CMD_VPU_STOP15, IVTV_REG_VPU); in ivtv_halt_firmware()
115 write_reg(IVTV_CMD_HW_BLOCKS_RST, IVTV_REG_HW_BLOCKS); in ivtv_halt_firmware()
118 write_reg(IVTV_CMD_SPU_STOP, IVTV_REG_SPU); in ivtv_halt_firmware()
123 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_ENC_SDRAM_PRECHARGE); in ivtv_halt_firmware()
126 write_reg(IVTV_CMD_SDRAM_REFRESH_INIT, IVTV_REG_ENC_SDRAM_REFRESH); in ivtv_halt_firmware()
130 write_reg(IVTV_CMD_SDRAM_PRECHARGE_INIT, IVTV_REG_DEC_SDRAM_PRECHARGE); in ivtv_halt_firmware()
[all …]
Divtv-irq.c81 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); in ivtv_pio_work_handler()
99 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); in ivtv_pio_work_handler()
436 write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR); in ivtv_dma_enc_start_xfer()
452 write_reg(s->sg_handle, IVTV_REG_DECDMAADDR); in ivtv_dma_dec_start_xfer()
560 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_dma_read()
623 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_enc_dma_complete()
702 write_reg(status, IVTV_REG_DMASTATUS); in ivtv_irq_dma_err()
857 write_reg(yuv_offset[next_dma_frame] >> 4, 0x82c); in ivtv_irq_vsync()
858 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x830); in ivtv_irq_vsync()
859 write_reg(yuv_offset[next_dma_frame] >> 4, 0x834); in ivtv_irq_vsync()
[all …]
Divtvfb.c271 write_reg((ivtv_window->top << 16) | ivtv_window->left, 0x02a04); in ivtvfb_set_display_window()
274 …write_reg(((ivtv_window->top+ivtv_window->height) << 16) | (ivtv_window->left+ivtv_window->width),… in ivtvfb_set_display_window()
526 write_reg(read_reg(0x02a00) | 0x0002000, 0x02a00); in ivtvfb_set_var()
528 write_reg(read_reg(0x02a00) & ~0x0002000, 0x02a00); in ivtvfb_set_var()
846 write_reg(osd_pan_index, 0x02A0C); in ivtvfb_pan_display()
884 write_reg(regno, 0x02a30); in ivtvfb_setcolreg()
885 write_reg(color, 0x02a34); in ivtvfb_setcolreg()
967 write_reg(i, 0x02a30); in ivtvfb_restore()
968 write_reg(oi->palette_cur[i], 0x02a34); in ivtvfb_restore()
970 write_reg(oi->pan_cur, 0x02a0c); in ivtvfb_restore()
[all …]
Divtv-i2c.c340 write_reg(~state, IVTV_REG_I2C_SETSCL_OFFSET); in ivtv_setscl()
348 write_reg(~state & 1, IVTV_REG_I2C_SETSDA_OFFSET); in ivtv_setsda()
652 write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSCL_OFFSET); in ivtv_setscl_old()
666 write_reg(~itv->i2c_state, IVTV_REG_I2C_SETSDA_OFFSET); in ivtv_setsda_old()
Divtv-udma.c215 write_reg(itv->udma.SG_handle, IVTV_REG_DECDMAADDR); in ivtv_udma_start()
Divtv-driver.h813 #define write_reg(val, reg) writel(val, itv->reg_mem + (reg)) macro
815 do { write_reg(val, reg); read_reg(reg); } while (0)
/linux-4.4.14/drivers/media/radio/
Dradio-tea5777.c198 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
200 tea->write_reg &= ~TEA5777_W_FM_PLL_MASK; in radio_tea5777_set_freq()
201 tea->write_reg |= (u64)freq << TEA5777_W_FM_PLL_SHIFT; in radio_tea5777_set_freq()
202 tea->write_reg &= ~TEA5777_W_FM_FREF_MASK; in radio_tea5777_set_freq()
203 tea->write_reg |= TEA5777_W_FM_FREF_VALUE << in radio_tea5777_set_freq()
205 tea->write_reg &= ~TEA5777_W_FM_FORCEMONO_MASK; in radio_tea5777_set_freq()
207 tea->write_reg |= 1LL << TEA5777_W_FM_FORCEMONO_SHIFT; in radio_tea5777_set_freq()
210 tea->write_reg &= ~TEA5777_W_AM_FM_MASK; in radio_tea5777_set_freq()
211 tea->write_reg |= (1LL << TEA5777_W_AM_FM_SHIFT); in radio_tea5777_set_freq()
213 tea->write_reg &= ~TEA5777_W_AM_PLL_MASK; in radio_tea5777_set_freq()
[all …]
Dradio-tea5777.h50 int (*write_reg)(struct radio_tea5777 *tea, u64 val); member
77 u64 write_reg; member
Dradio-shark2.c141 .write_reg = shark_write_reg,
/linux-4.4.14/drivers/staging/media/cxd2099/
Dcxd2099.c229 static int write_reg(struct cxd *ci, u8 reg, u8 val) in write_reg() function
304 status = write_reg(ci, 0x00, 0x00); in init()
307 status = write_reg(ci, 0x01, 0x00); in init()
310 status = write_reg(ci, 0x02, 0x10); in init()
313 status = write_reg(ci, 0x03, 0x00); in init()
316 status = write_reg(ci, 0x05, 0xFF); in init()
319 status = write_reg(ci, 0x06, 0x1F); in init()
322 status = write_reg(ci, 0x07, 0x1F); in init()
325 status = write_reg(ci, 0x08, 0x28); in init()
328 status = write_reg(ci, 0x14, 0x20); in init()
[all …]
/linux-4.4.14/drivers/net/ethernet/intel/igb/
De1000_phy.c107 if (!(hw->phy.ops.write_reg)) in igb_phy_reset_dsp()
110 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); in igb_phy_reset_dsp()
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); in igb_phy_reset_dsp()
500 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); in igb_copper_link_setup_82580()
525 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); in igb_copper_link_setup_82580()
591 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88()
618 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in igb_copper_link_setup_m88()
698 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
713 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in igb_copper_link_setup_m88_gen2()
797 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); in igb_copper_link_setup_igp()
[all …]
De1000_82575.c122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); in igb_check_for_link_media_swap()
154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
161 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); in igb_check_for_link_media_swap()
202 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; in igb_init_phy_params_82575()
209 phy->ops.write_reg = igb_write_phy_reg_82580; in igb_init_phy_params_82575()
214 phy->ops.write_reg = igb_write_phy_reg_gs40g; in igb_init_phy_params_82575()
218 phy->ops.write_reg = igb_write_phy_reg_igp; in igb_init_phy_params_82575()
251 ret_val = phy->ops.write_reg(hw, in igb_init_phy_params_82575()
918 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in igb_phy_hw_reset_sgmii_82575()
[all …]
De1000_i210.c756 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); in __igb_access_xmdio_reg()
760 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); in __igb_access_xmdio_reg()
764 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | in __igb_access_xmdio_reg()
772 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); in __igb_access_xmdio_reg()
777 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); in __igb_access_xmdio_reg()
Digb.h566 if (hw->phy.ops.write_reg) in igb_write_phy_reg()
567 return hw->phy.ops.write_reg(hw, offset, data); in igb_write_phy_reg()
De1000_hw.h344 s32 (*write_reg)(struct e1000_hw *, u32, u16); member
/linux-4.4.14/drivers/net/can/sja1000/
Dsja1000.c94 priv->write_reg(priv, SJA1000_CMR, val); in sja1000_write_cmdreg()
122 priv->write_reg(priv, SJA1000_IER, IRQ_OFF); in set_reset_mode()
132 priv->write_reg(priv, SJA1000_MOD, MOD_RM); in set_reset_mode()
153 priv->write_reg(priv, SJA1000_IER, IRQ_ALL); in set_normal_mode()
155 priv->write_reg(priv, SJA1000_IER, in set_normal_mode()
165 priv->write_reg(priv, SJA1000_MOD, mod_reg_val); in set_normal_mode()
188 priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN); in chipset_init()
191 priv->write_reg(priv, SJA1000_ACCC0, 0x00); in chipset_init()
192 priv->write_reg(priv, SJA1000_ACCC1, 0x00); in chipset_init()
193 priv->write_reg(priv, SJA1000_ACCC2, 0x00); in chipset_init()
[all …]
Dsja1000_platform.c85 priv->write_reg = sp_write_reg32; in sp_populate()
89 priv->write_reg = sp_write_reg16; in sp_populate()
94 priv->write_reg = sp_write_reg8; in sp_populate()
111 priv->write_reg = sp_write_reg32; in sp_populate_of()
115 priv->write_reg = sp_write_reg16; in sp_populate_of()
120 priv->write_reg = sp_write_reg8; in sp_populate_of()
Dems_pci.c170 priv->write_reg(priv, SJA1000_MOD, 1); in ems_pci_check_chan()
172 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); in ems_pci_check_chan()
311 priv->write_reg = ems_pci_v1_write_reg; in ems_pci_add_card()
315 priv->write_reg = ems_pci_v2_write_reg; in ems_pci_add_card()
Dsja1000_isa.c172 priv->write_reg = sja1000_isa_mem_write_reg; in sja1000_isa_probe()
179 priv->write_reg = sja1000_isa_port_write_reg_indirect; in sja1000_isa_probe()
183 priv->write_reg = sja1000_isa_port_write_reg; in sja1000_isa_probe()
Dsja1000.h159 void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val); member
Dtscan1.c138 priv->write_reg = tscan1_write; in tscan1_probe()
Dplx_pci.c376 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); in plx_pci_check_sja1000()
581 priv->write_reg = plx_pci_write_reg; in plx_pci_add_card()
Dems_pcmcia.c224 priv->write_reg = ems_pcmcia_write_reg; in ems_pcmcia_add_card()
Dpeak_pci.c490 priv->write_reg = peak_pciec_write_reg; in peak_pciec_probe()
631 priv->write_reg = peak_pci_write_reg; in peak_pci_probe()
Dkvaser_pci.c256 priv->write_reg = kvaser_pci_write_reg; in kvaser_pci_add_chan()
Dpeak_pcmcia.c567 priv->write_reg = pcan_write_canreg; in pcan_add_channels()
/linux-4.4.14/drivers/rtc/
Drtc-r9701.c43 static int write_reg(struct device *dev, int address, unsigned char data) in write_reg() function
106 ret = write_reg(dev, RHRCNT, bin2bcd(dt->tm_hour)); in r9701_set_datetime()
107 ret = ret ? ret : write_reg(dev, RMINCNT, bin2bcd(dt->tm_min)); in r9701_set_datetime()
108 ret = ret ? ret : write_reg(dev, RSECCNT, bin2bcd(dt->tm_sec)); in r9701_set_datetime()
109 ret = ret ? ret : write_reg(dev, RDAYCNT, bin2bcd(dt->tm_mday)); in r9701_set_datetime()
110 ret = ret ? ret : write_reg(dev, RMONCNT, bin2bcd(dt->tm_mon + 1)); in r9701_set_datetime()
111 ret = ret ? ret : write_reg(dev, RYRCNT, bin2bcd(dt->tm_year - 100)); in r9701_set_datetime()
112 ret = ret ? ret : write_reg(dev, RWKCNT, 1 << dt->tm_wday); in r9701_set_datetime()
/linux-4.4.14/drivers/net/can/
Dxilinx_can.c139 void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg, member
229 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
280 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
281 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
317 priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL); in xcan_chip_start()
328 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
329 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
444 priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id); in xcan_start_xmit()
446 priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc); in xcan_start_xmit()
448 priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]); in xcan_start_xmit()
[all …]
/linux-4.4.14/drivers/media/i2c/
Dtw2804.c118 static int write_reg(struct i2c_client *client, u8 reg, u8 value, u8 channel) in write_reg() function
218 return write_reg(client, addr, reg, state->channel); in tw2804_s_ctrl()
226 return write_reg(client, addr, reg, state->channel); in tw2804_s_ctrl()
229 return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0); in tw2804_s_ctrl()
232 return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0); in tw2804_s_ctrl()
235 return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0); in tw2804_s_ctrl()
238 return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0); in tw2804_s_ctrl()
241 return write_reg(client, TW2804_REG_BRIGHTNESS, in tw2804_s_ctrl()
245 return write_reg(client, TW2804_REG_CONTRAST, in tw2804_s_ctrl()
249 return write_reg(client, TW2804_REG_SATURATION, in tw2804_s_ctrl()
[all …]
Duda1342.c26 static int write_reg(struct i2c_client *client, int reg, int value) in write_reg() function
40 write_reg(client, 0x00, 0x1241); /* select input 1 */ in uda1342_s_routing()
43 write_reg(client, 0x00, 0x1441); /* select input 2 */ in uda1342_s_routing()
78 write_reg(client, 0x00, 0x8000); /* reset registers */ in uda1342_probe()
79 write_reg(client, 0x00, 0x1241); /* select input 1 */ in uda1342_probe()
Dtw9906.c73 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) in write_reg() function
85 if (write_reg(sd, regs[i], regs[i + 1]) < 0) in write_regs()
93 write_reg(sd, 0x02, 0x40 | (input << 1)); in tw9906_s_video_routing()
128 write_reg(sd, 0x10, ctrl->val); in tw9906_s_ctrl()
131 write_reg(sd, 0x11, ctrl->val); in tw9906_s_ctrl()
134 write_reg(sd, 0x15, ctrl->val); in tw9906_s_ctrl()
Dtw9903.c102 static int write_reg(struct v4l2_subdev *sd, u8 reg, u8 value) in write_reg() function
114 if (write_reg(sd, regs[i], regs[i + 1]) < 0) in write_regs()
122 write_reg(sd, 0x02, 0x40 | (input << 1)); in tw9903_s_video_routing()
158 write_reg(sd, 0x10, ctrl->val); in tw9903_s_ctrl()
161 write_reg(sd, 0x11, ctrl->val); in tw9903_s_ctrl()
164 write_reg(sd, 0x15, ctrl->val); in tw9903_s_ctrl()
/linux-4.4.14/drivers/macintosh/
Dtherm_windtunnel.c120 write_reg( struct i2c_client *cl, int reg, int data, int len ) in write_reg() function
158 write_reg( x.fan, 0x25, val, 1 ); in tune_fan()
159 write_reg( x.fan, 0x20, 0, 1 ); in tune_fan()
224 if( write_reg( x.thermostat, 1, val, 1 ) ) in setup_hardware()
228 write_reg( x.fan, 0x01, 0x01, 1 ); in setup_hardware()
230 write_reg( x.fan, 0x23, 0x91, 1 ); in setup_hardware()
232 write_reg( x.fan, 0x00, 0x95, 1 ); in setup_hardware()
242 write_reg( x.thermostat, 2, x.overheat_hyst, 2 ); in setup_hardware()
243 write_reg( x.thermostat, 3, x.overheat_temp, 2 ); in setup_hardware()
268 write_reg( x.fan, 0x01, x.r1, 1 ); in restore_regs()
[all …]
Dtherm_adt746x.c94 write_reg(struct thermostat* th, int reg, u8 data) in write_reg() function
175 write_reg(th, MANUAL_MODE[fan], in write_fan_speed()
177 write_reg(th, FAN_SPD_SET[fan], speed); in write_fan_speed()
185 write_reg(th, in write_fan_speed()
191 write_reg(th, MANUAL_MODE[fan], manual&(~AUTO_MASK)); in write_fan_speed()
313 write_reg(th, LIMIT_REG[i], th->limits[i]); in set_limit()
521 write_reg(th, CONFIG_REG, 1); in probe_thermostat()
583 write_reg(th, LIMIT_REG[i], th->initial_limits[i]); in remove_thermostat()
/linux-4.4.14/drivers/ide/
Dopti621.c38 static void write_reg(u8 value, int reg) in write_reg() function
113 write_reg(drive->dn & 1, MISC_REG); in opti621_set_pio_mode()
115 write_reg(tim, READ_REG); in opti621_set_pio_mode()
117 write_reg(tim, WRITE_REG); in opti621_set_pio_mode()
121 write_reg(0x85, CNTRL_REG); in opti621_set_pio_mode()
125 write_reg(misc, MISC_REG); in opti621_set_pio_mode()
/linux-4.4.14/drivers/tty/
Dsynclinkmp.c622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1534 write_reg(info, CTL, RegValue); in set_break()
2080 write_reg(info, IER2, 0); in isr_timer()
2092 write_reg(info, (unsigned char)(timer + TMCS), 0); in isr_timer()
2110 write_reg(info, SR1, status); in isr_rxint()
2113 write_reg(info, SR2, status2); in isr_rxint()
2228 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txeom()
2229 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txeom()
2230 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txeom()
2233 write_reg(info, CMD, TXRESET); in isr_txeom()
[all …]
/linux-4.4.14/drivers/video/fbdev/mbx/
Dmbxfb.c38 #define write_reg(val, reg) do { writel((val), (reg)); } while(0) macro
448 write_reg(vsctrl, VSCTRL); in mbxfb_setupOverlay()
449 write_reg(vscadr, VSCADR); in mbxfb_setupOverlay()
450 write_reg(vubase, VUBASE); in mbxfb_setupOverlay()
451 write_reg(vvbase, VVBASE); in mbxfb_setupOverlay()
452 write_reg(vsadr, VSADR); in mbxfb_setupOverlay()
455 write_reg(sssize, SSSIZE); in mbxfb_setupOverlay()
456 write_reg(spoctrl, SPOCTRL); in mbxfb_setupOverlay()
457 write_reg(shctrl, SHCTRL); in mbxfb_setupOverlay()
465 write_reg(vovrclk, VOVRCLK); in mbxfb_setupOverlay()
[all …]
/linux-4.4.14/drivers/gpio/
Dgpio-generic.c173 bgc->write_reg(bgc->reg_dat, bgc->data); in bgpio_set()
185 bgc->write_reg(bgc->reg_set, mask); in bgpio_set_with_clear()
187 bgc->write_reg(bgc->reg_clr, mask); in bgpio_set_with_clear()
203 bgc->write_reg(bgc->reg_set, bgc->data); in bgpio_set_set()
245 bgc->write_reg(reg, bgc->data); in bgpio_set_multiple_single_reg()
276 bgc->write_reg(bgc->reg_set, set_mask); in bgpio_set_multiple_with_clear()
278 bgc->write_reg(bgc->reg_clr, clear_mask); in bgpio_set_multiple_with_clear()
308 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_in()
333 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_out()
348 bgc->write_reg(bgc->reg_dir, bgc->dir); in bgpio_dir_in_inv()
[all …]
Dgpio-brcmstb.c89 bgc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
161 bank->bgc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
163 bank->bgc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
165 bank->bgc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
230 bank->bgc.write_reg(reg_base + GIO_STAT(bank->id), in brcmstb_gpio_irq_bank_handler()
500 bank->bgc.write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
Dgpio-grgpio.c112 bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask); in grgpio_set_imask()
166 priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); in grgpio_irq_set_type()
167 priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge); in grgpio_irq_set_type()
Dgpio-xgene-sb.c72 bgc->write_reg(reg, data); in xgene_gpio_set_bit()
Dgpio-dwapb.c106 bgc->write_reg(reg_base + offset, val); in dwapb_write()
/linux-4.4.14/drivers/net/ethernet/realtek/
Datp.c273 write_reg(ioaddr, MODSEL, 0x00); in atp_probe1()
321 write_reg(ioaddr, CMR2, CMR2_NULL); in atp_probe1()
374 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */ in get_node_ID()
385 write_reg(ioaddr, CMR2, CMR2_NULL); in get_node_ID()
475 write_reg(ioaddr, CMR2, CMR2_IRQOUT); in hardware_init()
482 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in hardware_init()
493 write_reg(ioaddr, TxCNT1, length >> 8); in trigger_send()
494 write_reg(ioaddr, CMR1, CMR1_Xmit); in trigger_send()
568 write_reg(ioaddr, IMR, 0); in atp_send_packet()
583 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in atp_send_packet()
[all …]
Datp.h158 write_reg(short port, unsigned char reg, unsigned char value) in write_reg() function
/linux-4.4.14/drivers/net/can/c_can/
Dc_can.c248 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); in c_can_irq_control()
288 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); in c_can_inval_tx_object()
296 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); in c_can_inval_msg_object()
297 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); in c_can_inval_msg_object()
333 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); in c_can_setup_tx_object()
336 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, in c_can_setup_tx_object()
359 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); in c_can_handle_lost_msg_obj()
430 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); in c_can_setup_receive_object()
511 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); in c_can_set_bittiming()
516 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); in c_can_set_bittiming()
[all …]
Dc_can_pci.c99 priv->write_reg(priv, index + 1, val >> 16); in c_can_pci_write_reg32()
100 priv->write_reg(priv, index, val); in c_can_pci_write_reg32()
193 priv->write_reg = c_can_pci_write_reg_aligned_to_32bit; in c_can_pci_probe()
197 priv->write_reg = c_can_pci_write_reg_aligned_to_16bit; in c_can_pci_probe()
201 priv->write_reg = c_can_pci_write_reg_32bit; in c_can_pci_probe()
Dc_can_platform.c155 priv->write_reg(priv, index + 1, val >> 16); in c_can_plat_write_reg32()
156 priv->write_reg(priv, index, val); in c_can_plat_write_reg32()
308 priv->write_reg = c_can_plat_write_reg_aligned_to_32bit; in c_can_plat_probe()
315 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; in c_can_plat_probe()
325 priv->write_reg = c_can_plat_write_reg_aligned_to_16bit; in c_can_plat_probe()
Dc_can.h204 void (*write_reg) (const struct c_can_priv *priv, enum reg index, u16 val); member
/linux-4.4.14/drivers/isdn/hardware/mISDN/
Dhfcsusb.c90 static int write_reg(struct hfcsusb *hw, __u8 reg, __u8 val) in write_reg() function
202 write_reg(hw, HFCUSB_P_DATA, hw->led_state); in handle_led()
657 write_reg(hw, HFCUSB_STATES, 2 | HFCUSB_NT_G2_G3); in ph_state_nt()
736 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 0 : 2); in hfcsusb_setup_bch()
737 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); in hfcsusb_setup_bch()
738 write_reg(hw, HFCUSB_INC_RES_F, 2); in hfcsusb_setup_bch()
739 write_reg(hw, HFCUSB_FIFO, (bch->nr == 1) ? 1 : 3); in hfcsusb_setup_bch()
740 write_reg(hw, HFCUSB_CON_HDLC, conhdlc); in hfcsusb_setup_bch()
741 write_reg(hw, HFCUSB_INC_RES_F, 2); in hfcsusb_setup_bch()
753 write_reg(hw, HFCUSB_SCTRL, sctrl); in hfcsusb_setup_bch()
[all …]
DmISDNisar.c75 isar->write_reg(isar->hw, ISAR_CTRL_H, creg); in send_mbox()
76 isar->write_reg(isar->hw, ISAR_CTRL_L, len); in send_mbox()
77 isar->write_reg(isar->hw, ISAR_WADR, 0); in send_mbox()
94 isar->write_reg(isar->hw, ISAR_HIS, his); in send_mbox()
108 isar->write_reg(isar->hw, ISAR_RADR, 0); in rcv_mbox()
123 isar->write_reg(isar->hw, ISAR_IIA, 0); in rcv_mbox()
167 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in ISARVersion()
214 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in load_firmware()
323 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA); in load_firmware()
409 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); in load_firmware()
[all …]
DmISDNinfineon.c488 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); in ipac_chip_reset()
490 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); in ipac_chip_reset()
492 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); in ipac_chip_reset()
493 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); in ipac_chip_reset()
534 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
535 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
536 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); in reset_inf()
541 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); in reset_inf()
542 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); in reset_inf()
543 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); in reset_inf()
[all …]
Dipac.h34 write_reg_func *write_reg; member
77 write_reg_func *write_reg; member
Disar.h51 write_reg_func *write_reg; member
Diohelper.h100 dest.write_reg = &Write##name##_##typ; \
DmISDNipac.c40 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
42 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
44 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
/linux-4.4.14/sound/ppc/
Dsnd_ps3.c73 static inline void write_reg(unsigned int reg, u32 val) in write_reg() function
80 write_reg(reg, newval); in update_reg()
85 write_reg(reg, newval); in update_mask_reg()
271 write_reg(PS3_AUDIO_SOURCE(dma_ch), in snd_ps3_program_dma()
277 write_reg(PS3_AUDIO_DEST(dma_ch), in snd_ps3_program_dma()
281 write_reg(PS3_AUDIO_DEST(dma_ch), in snd_ps3_program_dma()
286 write_reg(PS3_AUDIO_DMASIZE(dma_ch), 0); in snd_ps3_program_dma()
295 write_reg(PS3_AUDIO_KICK(dma_ch), in snd_ps3_program_dma()
298 write_reg(PS3_AUDIO_KICK(dma_ch), in snd_ps3_program_dma()
333 write_reg(PS3_AUDIO_AX_IS, PS3_AUDIO_AX_IE_ASOBEIE(0)); in snd_ps3_interrupt()
[all …]
/linux-4.4.14/drivers/char/pcmcia/
Dsynclink_cs.c321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg)) macro
328 write_reg(info, (reg), \
331 write_reg(info, (reg), \
358 { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361 { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
701 write_reg(info, (unsigned char) (channel + CMDR), cmd); in issue_command()
1025 write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get)); in tx_ready()
1888 write_reg(info, PVR, val); in set_interface()
2921 write_reg(info, (unsigned char) (channel + BGR), in mgslpc_set_rate()
2925 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
[all …]
/linux-4.4.14/drivers/net/irda/
Dstir4200.c194 static int write_reg(struct stir_cb *stir, __u16 reg, __u8 value) in write_reg() function
516 err = write_reg(stir, REG_CTRL1, CTRL1_SRESET); in change_speed()
521 err = write_reg(stir, REG_DPLL, 0x15); in change_speed()
526 err = write_reg(stir, REG_PDCLK, stir_modes[i].pdclk); in change_speed()
539 err = write_reg(stir, REG_MODE, mode); in change_speed()
544 err = write_reg(stir, REG_CTRL1, in change_speed()
549 err = write_reg(stir, REG_CTRL1, (tx_power & 3) << 1); in change_speed()
554 err = write_reg(stir, REG_CTRL2, (rx_sensitivity & 7) << 5); in change_speed()
639 err = write_reg(stir, REG_FIFOCTL, FIFOCTL_CLR); in fifo_txwait()
642 err = write_reg(stir, REG_FIFOCTL, 0); in fifo_txwait()
[all …]
/linux-4.4.14/drivers/block/paride/
Dpd.c267 static inline void write_reg(struct pd_unit *disk, int reg, int val) in write_reg() function
322 write_reg(disk, 6, DRIVE(disk) + h); in pd_send_command()
323 write_reg(disk, 1, 0); /* the IDE task file */ in pd_send_command()
324 write_reg(disk, 2, n); in pd_send_command()
325 write_reg(disk, 3, s); in pd_send_command()
326 write_reg(disk, 4, c0); in pd_send_command()
327 write_reg(disk, 5, c1); in pd_send_command()
328 write_reg(disk, 7, func); in pd_send_command()
666 write_reg(disk, 6, DRIVE(disk)); in pd_identify()
Dpg.c273 static inline void write_reg(struct pg *dev, int reg, int val) in write_reg() function
326 write_reg(dev, 6, DRIVE(dev)); in pg_command()
331 write_reg(dev, 4, dlen % 256); in pg_command()
332 write_reg(dev, 5, dlen / 256); in pg_command()
333 write_reg(dev, 7, 0xa0); /* ATAPI packet command */ in pg_command()
395 write_reg(dev, 6, DRIVE(dev)); in pg_reset()
396 write_reg(dev, 7, 8); in pg_reset()
Dpt.c262 static inline void write_reg(struct pi_adapter *pi, int reg, int val) in write_reg() function
302 write_reg(pi, 6, DRIVE(tape)); in pt_command()
309 write_reg(pi, 4, dlen % 256); in pt_command()
310 write_reg(pi, 5, dlen / 256); in pt_command()
311 write_reg(pi, 7, 0xa0); /* ATAPI packet command */ in pt_command()
406 write_reg(pi, 6, DRIVE(tape)); in pt_poll_dsc()
458 write_reg(pi, 6, DRIVE(tape)); in pt_reset()
459 write_reg(pi, 7, 8); in pt_reset()
Dpf.c398 static inline void write_reg(struct pf_unit *pf, int reg, int val) in write_reg() function
431 write_reg(pf, 6, 0xa0+0x10*pf->drive); in pf_command()
438 write_reg(pf, 4, dlen % 256); in pf_command()
439 write_reg(pf, 5, dlen / 256); in pf_command()
440 write_reg(pf, 7, 0xa0); /* ATAPI packet command */ in pf_command()
542 write_reg(pf, 6, 0xa0+0x10*pf->drive); in pf_reset()
543 write_reg(pf, 7, 8); in pf_reset()
Dpcd.c349 static inline void write_reg(struct pcd_unit *cd, int reg, int val) in write_reg() function
382 write_reg(cd, 6, 0xa0 + 0x10 * cd->drive); in pcd_command()
389 write_reg(cd, 4, dlen % 256); in pcd_command()
390 write_reg(cd, 5, dlen / 256); in pcd_command()
391 write_reg(cd, 7, 0xa0); /* ATAPI packet command */ in pcd_command()
545 write_reg(cd, 6, 0xa0 + 0x10 * cd->drive); in pcd_reset()
546 write_reg(cd, 7, 8); in pcd_reset()
/linux-4.4.14/drivers/media/usb/go7007/
Ds2250-board.c159 static int write_reg(struct i2c_client *client, u8 reg, u8 value) in write_reg() function
303 if (write_reg(client, regs[i], regs[i+1]) < 0) { in write_regs()
439 write_reg(state->audio, 0x08, 0x02); /* Line In */ in s2250_s_audio_routing()
442 write_reg(state->audio, 0x08, 0x04); /* Mic */ in s2250_s_audio_routing()
445 write_reg(state->audio, 0x08, 0x05); /* Mic Boost */ in s2250_s_audio_routing()
579 write_reg(client, 0x08, 0x02); /* Line In */ in s2250_probe()
/linux-4.4.14/arch/sh/boards/mach-migor/
Dlcd_qvga.c52 static void write_reg(void *sys_ops_handle, in write_reg() function
163 write_reg(sohandle, so, 0x00, 0x22); in migor_lcd_qvga_setup()
/linux-4.4.14/drivers/media/platform/ti-vpe/
Dvpdma.c247 static void write_reg(struct vpdma_data *vpdma, int offset, u32 value) in write_reg() function
266 write_reg(vpdma, offset, val); in write_field_reg()
440 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr); in vpdma_submit_descs()
442 write_reg(vpdma, VPDMA_LIST_ATTR, in vpdma_submit_descs()
762 write_reg(vpdma, VPDMA_INT_LIST0_MASK, val); in vpdma_enable_list_complete_irq()
768 write_reg(vpdma, VPDMA_INT_LIST0_STAT, in vpdma_clear_list_stat()
831 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr); in vpdma_firmware_cb()
Dvpe.c430 static void write_reg(struct vpe_dev *dev, int offset, u32 value) in write_reg() function
462 write_reg(dev, offset, val); in write_field_reg()
602 write_reg(dev, VPE_CLK_ENABLE, val); in vpe_set_clock_enable()
1077 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE); in enable_irqs()
1078 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT | in enable_irqs()
1086 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff); in disable_irqs()
1087 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff); in disable_irqs()
1232 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0); in vpe_irq()
1238 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1); in vpe_irq()
/linux-4.4.14/drivers/net/can/cc770/
Dcc770.h152 priv->write_reg(priv, offsetof(struct cc770_regs, member), value)
181 void (*write_reg)(const struct cc770_priv *priv, int reg, u8 val); member
Dcc770_isa.c214 priv->write_reg = cc770_isa_mem_write_reg; in cc770_isa_probe()
221 priv->write_reg = cc770_isa_port_write_reg_indirect; in cc770_isa_probe()
224 priv->write_reg = cc770_isa_port_write_reg; in cc770_isa_probe()
Dcc770_platform.c200 priv->write_reg = cc770_platform_write_reg; in cc770_platform_probe()
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
Dmxl111sf-demod.h30 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member
Dmxl111sf-tuner.h54 int (*write_reg)(struct mxl111sf_state *state, u8 addr, u8 data); member
Dmxl111sf-tuner.c58 return (state->cfg->write_reg) ? in mxl111sf_tuner_write_reg()
59 state->cfg->write_reg(state->mxl_state, addr, data) : in mxl111sf_tuner_write_reg()
Dmxl111sf-demod.c56 return (state->cfg->write_reg) ? in mxl111sf_demod_write_reg()
57 state->cfg->write_reg(state->mxl_state, addr, data) : in mxl111sf_demod_write_reg()
Dmxl111sf.c736 .write_reg = mxl111sf_write_reg,
862 .write_reg = mxl111sf_write_reg,
/linux-4.4.14/drivers/mtd/spi-nor/
Dspi-nor.c159 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); in write_sr()
168 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); in write_enable()
176 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); in write_disable()
202 status = nor->write_reg(nor, cmd, NULL, 0); in set_4byte()
210 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); in set_4byte()
288 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); in erase_chip()
1043 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); in write_sr_cr()
1097 !nor->read_reg || !nor->write_reg || !nor->erase) { in spi_nor_check()
Dnxp-spifi.c339 spifi->nor.write_reg = nxp_spifi_write_reg; in nxp_spifi_setup_flash()
Dfsl-quadspi.c1021 nor->write_reg = fsl_qspi_write_reg; in fsl_qspi_probe()
/linux-4.4.14/include/video/
Dbroadsheetfb.h49 void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); member
/linux-4.4.14/include/linux/
Dbasic_mmio_gpio.h33 void (*write_reg)(void __iomem *reg, unsigned long data); member
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
Dixgbe_phy.c469 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_reset_phy_generic()
718 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, in ixgbe_setup_phy_link_generic()
734 hw->phy.ops.write_reg(hw, in ixgbe_setup_phy_link_generic()
751 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_phy_link_generic()
766 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_generic()
937 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, in ixgbe_setup_phy_link_tnx()
952 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
968 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_phy_link_tnx()
983 hw->phy.ops.write_reg(hw, MDIO_CTRL1, in ixgbe_setup_phy_link_tnx()
1042 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, in ixgbe_reset_phy_nl()
[all …]
Dixgbe_x550.c1547 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1561 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1577 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, in ixgbe_enable_lasi_ext_t_x550em()
1592 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2007 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2012 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2105 status = hw->phy.ops.write_reg(hw, in ixgbe_init_ext_t_x550em()
2434 .write_reg = &ixgbe_write_phy_reg_generic, \
Dixgbe_x540.c879 .write_reg = &ixgbe_write_phy_reg_generic,
Dixgbe_82598.c1221 .write_reg = &ixgbe_write_phy_reg_generic,
Dixgbe_82599.c2250 .write_reg = &ixgbe_write_phy_reg_generic,
Dixgbe_type.h3321 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); member
Dixgbe_common.c258 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc()
Dixgbe_main.c7699 return hw->phy.ops.write_reg(hw, addr, devad, value); in ixgbe_mdio_write()
/linux-4.4.14/include/linux/mtd/
Dspi-nor.h173 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); member
/linux-4.4.14/drivers/mtd/onenand/
Domap2.c87 static inline void write_reg(struct omap2_onenand *c, unsigned short value, in write_reg() function
155 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
205 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1); in omap2_onenand_wait()
/linux-4.4.14/drivers/mtd/devices/
Dm25p80.c198 nor->write_reg = m25p80_write_reg; in m25p_probe()
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
D82571.c1912 .write_reg = e1000e_write_phy_reg_igp,
1930 .write_reg = e1000e_write_phy_reg_m88,
1948 .write_reg = e1000e_write_phy_reg_bm2,
De1000.h536 return hw->phy.ops.write_reg(hw, offset, data); in e1e_wphy()
Dhw.h515 s32 (*write_reg)(struct e1000_hw *, u32, u16); member
D80003es2lan.c1385 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
Dich8lan.c452 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
538 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
580 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
5716 .write_reg = e1000e_write_phy_reg_igp,
/linux-4.4.14/Documentation/video4linux/
Dv4l2-controls.txt247 write_reg(0x123, ctrl->val);
250 write_reg(0x456, ctrl->val);
500 write_reg(0x123, mute->val ? 0 : ctrl->val);
504 write_reg(0x456, ctrl->val);
/linux-4.4.14/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic.h1556 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1772 int (*write_reg) (struct qlcnic_adapter *, ulong, u32); member
1865 return adapter->ahw->hw_ops->write_reg(adapter, off, data); in qlcnic_hw_write_wx_2M()
Dqlcnic_sriov_common.c50 .write_reg = qlcnic_83xx_wrt_reg_indirect,
Dqlcnic_main.c587 .write_reg = qlcnic_82xx_hw_write_wx_2M,
Dqlcnic_83xx_hw.c201 .write_reg = qlcnic_83xx_wrt_reg_indirect,
/linux-4.4.14/drivers/video/fbdev/
Dbroadsheetfb.c1128 par->write_reg = broadsheet_write_reg; in broadsheetfb_probe()