Lines Matching refs:write_reg
81 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); in ivtv_pio_work_handler()
99 write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44); in ivtv_pio_work_handler()
436 write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR); in ivtv_dma_enc_start_xfer()
452 write_reg(s->sg_handle, IVTV_REG_DECDMAADDR); in ivtv_dma_dec_start_xfer()
560 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_dma_read()
623 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_irq_enc_dma_complete()
702 write_reg(status, IVTV_REG_DMASTATUS); in ivtv_irq_dma_err()
857 write_reg(yuv_offset[next_dma_frame] >> 4, 0x82c); in ivtv_irq_vsync()
858 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x830); in ivtv_irq_vsync()
859 write_reg(yuv_offset[next_dma_frame] >> 4, 0x834); in ivtv_irq_vsync()
860 write_reg((yuv_offset[next_dma_frame] + IVTV_YUV_BUFFER_UV_OFFSET) >> 4, 0x838); in ivtv_irq_vsync()
945 if (combo) write_reg(combo, IVTV_REG_IRQSTATUS); in ivtv_irq_handler()
1085 write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS); in ivtv_unfinished_dma()