321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))  macro
328 	write_reg(info, (reg), \
331 	write_reg(info, (reg), \
358 	{ info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
361 	{ info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
701 	write_reg(info, (unsigned char) (channel + CMDR), cmd);  in issue_command()
1025 			write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));  in tx_ready()
1888 	write_reg(info, PVR, val);  in set_interface()
2921 		write_reg(info, (unsigned char) (channel + BGR),  in mgslpc_set_rate()
2925 		write_reg(info, (unsigned char) (channel + CCR2), val);  in mgslpc_set_rate()
2952 	write_reg(info, CHB + MODE, val);  in enable_auxclk()
2964 	write_reg(info, CHB + CCR0, 0xc0);  in enable_auxclk()
2977 	write_reg(info, CHB + CCR1, 0x17);  in enable_auxclk()
2992 		write_reg(info, CHB + CCR2, 0x38);  in enable_auxclk()
2994 		write_reg(info, CHB + CCR2, 0x30);  in enable_auxclk()
3007 	write_reg(info, CHB + CCR4, 0x50);  in enable_auxclk()
3024 	write_reg(info, CHA + CCR1, val);  in loopback_enable()
3028 	write_reg(info, CHA + CCR2, val);  in loopback_enable()
3038 	write_reg(info, CHA + MODE, val);  in loopback_enable()
3095 	write_reg(info, CHA + MODE, val);  in hdlc_mode()
3123 	write_reg(info, CHA + CCR0, val);  in hdlc_mode()
3137 	write_reg(info, CHA + CCR1, val);  in hdlc_mode()
3161 	write_reg(info, CHA + CCR2, val);  in hdlc_mode()
3192 	write_reg(info, CHA + CCR3, val);  in hdlc_mode()
3203 	write_reg(info, CHA + PRE, val);  in hdlc_mode()
3217 	write_reg(info, CHA + CCR4, val);  in hdlc_mode()
3228 	write_reg(info, CHA + RLCR, 0);  in hdlc_mode()
3243 	write_reg(info, CHA + XBCH, val);  in hdlc_mode()
3365 	write_reg(info, CHA + CCR0, 0x80);  in reset_device()
3366 	write_reg(info, CHB + CCR0, 0x80);  in reset_device()
3367 	write_reg(info, CHA + MODE, 0);  in reset_device()
3368 	write_reg(info, CHB + MODE, 0);  in reset_device()
3385 	write_reg(info, PCR, 0x06);  in reset_device()
3409 	write_reg(info, IPC, 0x05);  in reset_device()
3441 	write_reg(info, CHA + MODE, val);  in async_mode()
3453 	write_reg(info, CHA + CCR0, 0x83);  in async_mode()
3464 	write_reg(info, CHA + CCR1, 0x1f);  in async_mode()
3478 	write_reg(info, CHA + CCR2, 0x10);  in async_mode()
3487 	write_reg(info, CHA + CCR3, 0);  in async_mode()
3499 	write_reg(info, CHA + CCR4, 0x50);  in async_mode()
3525 	write_reg(info, CHA + DAFO, val);  in async_mode()
3539 	write_reg(info, CHA + RFC, 0x5c);  in async_mode()
3545 	write_reg(info, CHA + RLCR, 0);  in async_mode()
3560 	write_reg(info, CHA + XBCH, val);  in async_mode()
3632 	write_reg(info, CHA + MODE, val);  in set_signals()
3756 		write_reg(info, XAD1, patterns[i]);  in register_test()
3757 		write_reg(info, XAD2, patterns[(i + 1) % count]);  in register_test()
3785 	write_reg(info, CHA + TIMR, 0);	/* 512 cycles */  in irq_test()