139 	void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,  member
229 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);  in set_reset_mode()
280 	priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);  in xcan_set_bittiming()
281 	priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);  in xcan_set_bittiming()
317 	priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);  in xcan_chip_start()
328 	priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);  in xcan_chip_start()
329 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);  in xcan_chip_start()
444 	priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);  in xcan_start_xmit()
446 	priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);  in xcan_start_xmit()
448 		priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);  in xcan_start_xmit()
452 		priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);  in xcan_start_xmit()
551 	priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);  in xcan_err_interrupt()
561 		priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);  in xcan_err_interrupt()
602 		priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);  in xcan_err_interrupt()
712 			priv->write_reg(priv, XCAN_ICR_OFFSET,  in xcan_rx_poll()
716 			priv->write_reg(priv, XCAN_ICR_OFFSET,  in xcan_rx_poll()
720 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);  in xcan_rx_poll()
731 		priv->write_reg(priv, XCAN_IER_OFFSET, ier);  in xcan_rx_poll()
748 		priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);  in xcan_tx_interrupt()
783 		priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |  in xcan_interrupt()
795 		priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |  in xcan_interrupt()
805 		priv->write_reg(priv, XCAN_IER_OFFSET, ier);  in xcan_interrupt()
826 	priv->write_reg(priv, XCAN_IER_OFFSET, ier);  in xcan_chip_stop()
827 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);  in xcan_chip_stop()
984 	priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);  in xcan_suspend()
1019 	priv->write_reg(priv, XCAN_MSR_OFFSET, 0);  in xcan_resume()
1020 	priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);  in xcan_resume()
1126 	priv->write_reg = xcan_write_reg_le;  in xcan_probe()
1130 		priv->write_reg = xcan_write_reg_be;  in xcan_probe()