Lines Matching refs:write_reg
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
1534 write_reg(info, CTL, RegValue); in set_break()
2080 write_reg(info, IER2, 0); in isr_timer()
2092 write_reg(info, (unsigned char)(timer + TMCS), 0); in isr_timer()
2110 write_reg(info, SR1, status); in isr_rxint()
2113 write_reg(info, SR2, status2); in isr_rxint()
2228 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txeom()
2229 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txeom()
2230 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txeom()
2233 write_reg(info, CMD, TXRESET); in isr_txeom()
2234 write_reg(info, CMD, TXENABLE); in isr_txeom()
2236 write_reg(info, CMD, TXBUFCLR); in isr_txeom()
2242 write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); in isr_txeom()
2287 write_reg(info, SR1, status); in isr_txint()
2334 write_reg(info, IE0, info->ie0_value); in isr_txrdy()
2349 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaok()
2366 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); in isr_rxdmaerror()
2380 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ in isr_txdmaok()
2381 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ in isr_txdmaok()
2382 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in isr_txdmaok()
2391 write_reg(info, IE0, info->ie0_value); in isr_txdmaok()
2402 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); in isr_txdmaerror()
2440 write_reg(info, IE1, info->ie1_value); in isr_io_pin()
2460 write_reg(info, IE1, info->ie1_value); in isr_io_pin()
2740 write_reg(info, IE1, info->ie1_value); in program_hw()
2990 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ in tx_abort()
2991 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ in tx_abort()
2993 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_abort()
2994 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_abort()
2996 write_reg(info, CMD, TXABORT); in tx_abort()
3072 write_reg(info, IE1, info->ie1_value); in wait_mgsl_event()
3137 write_reg(info, IE1, info->ie1_value); in wait_mgsl_event()
3940 write_reg(info, LPR, 1); /* set low power mode */ in synclinkmp_cleanup()
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4040 write_reg(info, RXS, 0x40); in enable_loopback()
4041 write_reg(info, TXS, 0x40); in enable_loopback()
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4054 write_reg(info, RXS, 0x00); in enable_loopback()
4055 write_reg(info, TXS, 0x00); in enable_loopback()
4101 write_reg(info, TXS, in set_rate()
4103 write_reg(info, RXS, in set_rate()
4105 write_reg(info, TMC, (unsigned char)TMCValue); in set_rate()
4108 write_reg(info, TXS,0); in set_rate()
4109 write_reg(info, RXS,0); in set_rate()
4110 write_reg(info, TMC, 0); in set_rate()
4122 write_reg(info, CMD, RXRESET); in rx_stop()
4125 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ in rx_stop()
4127 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_stop()
4128 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ in rx_stop()
4129 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ in rx_stop()
4145 write_reg(info, CMD, RXRESET); in rx_start()
4150 write_reg(info, IE0, info->ie0_value); in rx_start()
4153 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ in rx_start()
4154 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ in rx_start()
4177 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ in rx_start()
4178 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ in rx_start()
4182 write_reg(info, IE0, info->ie0_value); in rx_start()
4185 write_reg(info, CMD, RXENABLE); in rx_start()
4201 write_reg(info, CMD, TXRESET); in tx_start()
4202 write_reg(info, CMD, TXENABLE); in tx_start()
4228 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_start()
4229 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_start()
4242 write_reg(info, IE1, info->ie1_value); in tx_start()
4243 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); in tx_start()
4245 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ in tx_start()
4246 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ in tx_start()
4255 write_reg(info, IE0, info->ie0_value); in tx_start()
4272 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ in tx_stop()
4273 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ in tx_stop()
4275 write_reg(info, CMD, TXRESET); in tx_stop()
4278 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ in tx_stop()
4279 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ in tx_stop()
4282 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ in tx_stop()
4325 write_reg(info, TRB, info->x_char); in tx_load_fifo()
4328 write_reg(info, TRB, info->tx_buf[info->tx_get++]); in tx_load_fifo()
4354 write_reg(info, IE0, info->ie0_value); in reset_port()
4355 write_reg(info, IE1, info->ie1_value); in reset_port()
4356 write_reg(info, IE2, info->ie2_value); in reset_port()
4358 write_reg(info, CMD, CHRESET); in reset_port()
4397 write_reg(info, MD0, RegValue); in async_mode()
4419 write_reg(info, MD1, RegValue); in async_mode()
4431 write_reg(info, MD2, RegValue); in async_mode()
4440 write_reg(info, RXS, RegValue); in async_mode()
4449 write_reg(info, TXS, RegValue); in async_mode()
4465 write_reg(info, RRC, 0x00); in async_mode()
4472 write_reg(info, TRC0, 0x10); in async_mode()
4479 write_reg(info, TRC1, 0x1e); in async_mode()
4496 write_reg(info, CTL, RegValue); in async_mode()
4500 write_reg(info, IE0, info->ie0_value); in async_mode()
4504 write_reg(info, IE1, info->ie1_value); in async_mode()
4508 write_reg(info, IE2, info->ie2_value); in async_mode()
4527 write_reg(info, TXDMA + DIR, 0); in hdlc_mode()
4528 write_reg(info, RXDMA + DIR, 0); in hdlc_mode()
4548 write_reg(info, MD0, RegValue); in hdlc_mode()
4560 write_reg(info, MD1, RegValue); in hdlc_mode()
4593 write_reg(info, MD2, RegValue); in hdlc_mode()
4607 write_reg(info, RXS, RegValue); in hdlc_mode()
4620 write_reg(info, TXS, RegValue); in hdlc_mode()
4642 write_reg(info, RRC, rx_active_fifo_level); in hdlc_mode()
4649 write_reg(info, TRC0, tx_active_fifo_level); in hdlc_mode()
4656 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); in hdlc_mode()
4669 write_reg(info, TXDMA + DMR, 0x14); in hdlc_mode()
4670 write_reg(info, RXDMA + DMR, 0x14); in hdlc_mode()
4673 write_reg(info, RXDMA + CPB, in hdlc_mode()
4677 write_reg(info, TXDMA + CPB, in hdlc_mode()
4684 write_reg(info, IE0, info->ie0_value); in hdlc_mode()
4701 write_reg(info, CTL, RegValue); in hdlc_mode()
4732 write_reg(info, IDL, RegValue); in tx_set_idle()
4776 write_reg(info, CTL, RegValue); in set_signals()
5066 write_reg(info, TMC, testval[i]); in register_test()
5067 write_reg(info, IDL, testval[(i+1)%count]); in register_test()
5068 write_reg(info, SA0, testval[(i+2)%count]); in register_test()
5069 write_reg(info, SA1, testval[(i+3)%count]); in register_test()
5104 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); in irq_test()
5106 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ in irq_test()
5120 write_reg(info, (unsigned char)(timer + TMCS), 0x50); in irq_test()
5141 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ in sca_init()
5142 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ in sca_init()
5143 write_reg(info, WCRL, 0); /* wait controller low range */ in sca_init()
5144 write_reg(info, WCRM, 0); /* wait controller mid range */ in sca_init()
5145 write_reg(info, WCRH, 0); /* wait controller high range */ in sca_init()
5156 write_reg(info, DPCR, dma_priority); in sca_init()
5159 write_reg(info, DMER, 0x80); in sca_init()
5162 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ in sca_init()
5163 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ in sca_init()
5164 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ in sca_init()
5172 write_reg(info, ITCR, 0); in sca_init()
5554 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) in write_reg() function