94 	priv->write_reg(priv, SJA1000_CMR, val);  in sja1000_write_cmdreg()
122 	priv->write_reg(priv, SJA1000_IER, IRQ_OFF);  in set_reset_mode()
132 		priv->write_reg(priv, SJA1000_MOD, MOD_RM);  in set_reset_mode()
153 				priv->write_reg(priv, SJA1000_IER, IRQ_ALL);  in set_normal_mode()
155 				priv->write_reg(priv, SJA1000_IER,  in set_normal_mode()
165 		priv->write_reg(priv, SJA1000_MOD, mod_reg_val);  in set_normal_mode()
188 	priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);  in chipset_init()
191 	priv->write_reg(priv, SJA1000_ACCC0, 0x00);  in chipset_init()
192 	priv->write_reg(priv, SJA1000_ACCC1, 0x00);  in chipset_init()
193 	priv->write_reg(priv, SJA1000_ACCC2, 0x00);  in chipset_init()
194 	priv->write_reg(priv, SJA1000_ACCC3, 0x00);  in chipset_init()
196 	priv->write_reg(priv, SJA1000_ACCM0, 0xFF);  in chipset_init()
197 	priv->write_reg(priv, SJA1000_ACCM1, 0xFF);  in chipset_init()
198 	priv->write_reg(priv, SJA1000_ACCM2, 0xFF);  in chipset_init()
199 	priv->write_reg(priv, SJA1000_ACCM3, 0xFF);  in chipset_init()
201 	priv->write_reg(priv, SJA1000_OCR, priv->ocr | OCR_MODE_NORMAL);  in chipset_init()
217 	priv->write_reg(priv, SJA1000_TXERR, 0x0);  in sja1000_start()
218 	priv->write_reg(priv, SJA1000_RXERR, 0x0);  in sja1000_start()
258 	priv->write_reg(priv, SJA1000_BTR0, btr0);  in sja1000_set_bittiming()
259 	priv->write_reg(priv, SJA1000_BTR1, btr1);  in sja1000_set_bittiming()
307 		priv->write_reg(priv, SJA1000_FI, fi);  in sja1000_start_xmit()
308 		priv->write_reg(priv, SJA1000_ID1, (id & 0x1fe00000) >> 21);  in sja1000_start_xmit()
309 		priv->write_reg(priv, SJA1000_ID2, (id & 0x001fe000) >> 13);  in sja1000_start_xmit()
310 		priv->write_reg(priv, SJA1000_ID3, (id & 0x00001fe0) >> 5);  in sja1000_start_xmit()
311 		priv->write_reg(priv, SJA1000_ID4, (id & 0x0000001f) << 3);  in sja1000_start_xmit()
314 		priv->write_reg(priv, SJA1000_FI, fi);  in sja1000_start_xmit()
315 		priv->write_reg(priv, SJA1000_ID1, (id & 0x000007f8) >> 3);  in sja1000_start_xmit()
316 		priv->write_reg(priv, SJA1000_ID2, (id & 0x00000007) << 5);  in sja1000_start_xmit()
320 		priv->write_reg(priv, dreg++, cf->data[i]);  in sja1000_start_xmit()