Searched refs:miss (Results 1 - 200 of 452) sorted by relevance

123

/linux-4.4.14/arch/frv/mm/
H A DMakefile8 pgalloc.o highmem.o fault.o extable.o cache-page.o tlb-flush.o tlb-miss.o \
H A Dtlb-miss.S1 /* tlb-miss.S: TLB miss handlers
122 # Kernel instruction TLB miss handler
128 # SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
252 # Kernel data TLB miss handler
258 # SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
381 # Userspace instruction TLB miss handler (with PGE prediction)
385 # SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
499 # Userspace data TLB miss handler
503 # SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
H A Dfault.c46 [0x0] = "mmu-miss", [0x8] = "multi-dat", [0x9] = "multi-sat", do_page_fault()
47 [0xa] = "tlb-miss", [0xc] = "privilege", [0xd] = "write-prot", do_page_fault()
H A Dmmu-context.c87 * restore the current TLB miss handler mapped page tables into the MMU context and set up a
/linux-4.4.14/arch/cris/arch-v10/mm/
H A Dfault.c51 int miss, we, writeac; handle_mmu_bus_fault() local
66 miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause); handle_mmu_bus_fault()
70 D(printk("bus_fault from IRP 0x%lx: addr 0x%lx, miss %d, inv %d, we %d, acc %d, dx %d pid %d\n", handle_mmu_bus_fault()
71 regs->irp, address, miss, inv, we, acc, index, page_id)); handle_mmu_bus_fault()
74 if (miss) handle_mmu_bus_fault()
79 /* Reload TLB with new entry to avoid an extra miss exception. handle_mmu_bus_fault()
/linux-4.4.14/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c44 * 0x03 UTLB miss
45 * 0x04 Operand cache read miss
46 * 0x05 Operand cache write miss
48 * 0x07 Instruction TLB miss
49 * 0x08 Instruction cache miss
55 * 0x0f Operand cache miss (r/w)
70 * 0x24 Pipeline freeze by I-cache miss
71 * 0x25 Pipeline freeze by D-cache miss
/linux-4.4.14/arch/sparc/mm/
H A Dinit_64.h25 /* Exported for kernel TLB miss handling in ktlb.S */
H A Dtlb.c187 * Instead, we let the first TLB miss on a hugepage set_pmd_at()
H A Dfault_64.c412 /* If we took a ITLB miss on a non-executable page, catch do_sparc64_fault()
H A Dtsb.c397 * accessing the old TSB via TLB miss handling. This is OK tsb_grow()
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dsiginfo.h20 #define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */
/linux-4.4.14/arch/arm/mach-gemini/
H A Didle.c14 * interrupts first since scheduler can miss a tick, but there is gemini_idle()
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c72 * 0x0220 UTLB miss caused by instruction fetch
73 * 0x0222 UTLB miss caused by operand access
77 * 0x002a instruction cache miss
83 * 0x0032 operand cache read miss
84 * 0x003a operand cache write miss
92 * 0x0033 number of wait cycles due to operand cache read miss
93 * 0x003b number of wait cycles due to operand cache write miss
/linux-4.4.14/arch/powerpc/mm/
H A Dtlb_low_64e.S2 * Low level TLB miss handlers for Book3E
37 * TLB miss handling for Book3E with a bolted linear mapping *
44 * modified by the TLB miss handlers themselves, since the TLB miss
45 * handler code will not itself cause a recursive TLB miss.
93 /* Data TLB miss */
136 * This is the guts of the TLB miss handler for bolted-linear.
230 /* We need to check if it was an instruction miss */
242 /* Instruction TLB miss */
263 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
297 * This is the guts of the TLB miss handler for e6500 and derivatives.
520 /* We need to check if it was an instruction miss */
535 * TLB miss handling for Book3E with TLB reservation and HES support *
540 /* Data TLB miss */
609 /* Instruction TLB miss */
656 * This is the guts of the first-level TLB miss handler for direct
770 /* We need to check if it was an instruction miss */
786 * This is the guts of the second-level TLB miss handler for direct
802 * It can be re-entered by the linear mapping miss handler. However, to
898 /* We have overriden MAS2:EPN but currently our primary TLB miss
903 * ITLB miss handler to also store SRR0 in the exception frame
908 * are not a level 0 exception (we interrupted the TLB miss) we
931 * always called as a second level tlb miss for SW load or as a first
932 * level TLB miss for HW load, so we should be able to peek at the
938 * from an instruction tlb miss anyway).
975 * TLB miss handling for Book3E with hw page table support *
980 /* Data TLB miss */
1017 /* Instruction TLB miss */
1061 * This is the guts of the second-level TLB miss handler for direct
1072 * It can be re-entered by the linear mapping miss handler. However, to
1165 /* We need to check if it was an instruction miss. We know this
1180 * This is the guts of "any" level TLB miss handler for kernel linear
1196 * as we know we'll have clobbered them if we interrupt the main TLB miss
1249 * miss handler, due to MAS and TLB reservation being clobbered.
H A Dtlb_nohash.c151 * exceptions. This is used for bolted and e6500 TLB miss handlers which
152 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
568 * If we want to use HW tablewalk, enable it by patching the TLB miss setup_mmu_htw()
664 * now our boot and TLB miss code hard wires it. Ideally early_init_mmu_global()
666 * TLB miss code (either that or use the PACA to store early_init_mmu_global()
705 * for use by the TLB miss code early_init_mmu_global()
H A D44x_mmu.c49 /* The TLB miss handlers hard codes the watermark in a cmpli ppc44x_update_tlb_hwater()
52 * in the 2 TLB miss handlers when updating the value ppc44x_update_tlb_hwater()
H A Dslb.c204 * user memory (to get a stack trace) and possible cause an SLB miss switch_slb()
298 /* Prepare our SLB miss handler based on our page size */ slb_initialize()
H A Dhash_native_64.c306 DBG_LOW(" -> miss\n"); native_hpte_updatepp()
470 /* Even if we miss, we need to invalidate the TLB */ native_hugepage_invalidate()
H A Dicswx.c195 * results from a CT miss in the ACOP register.
H A Dtlb_nohash_low.S86 * an interrupt which causes a TLB miss can clobber the MMUCR
/linux-4.4.14/arch/blackfin/include/asm/
H A Dtraps.h100 "Data access CPLB miss\n" \
101 level " - Used by the MMU to signal a CPLB miss on a data access.\n"
116 "Instruction fetch CPLB miss\n" \
117 level " - CPLB miss on an instruction fetch.\n"
H A Dpda.h33 * the exception cause to ensure we don't miss a
H A Ddef_LPBlackfin.h319 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
321 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
/linux-4.4.14/arch/powerpc/include/asm/
H A Dexception-64e.h17 * Since TLB miss and other standard exceptions can be interrupted by
19 * checks, and since the two later can themselves cause a TLB miss when
26 * to save in there. That includes saving the SPRGs used by the TLB miss
53 * The TLB miss exception uses different slots.
86 /* TLB miss exception prolog
H A Dpte-40x.h27 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
32 * is cleared in the TLB miss handler before the TLB entry is loaded.
H A Dkvm_booke_hv_asm.h55 * Only the bolted version of TLB miss exception handlers is supported now.
H A Dpte-8xx.h34 #define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
H A Dmmu-8xx.h44 * about the last instruction TLB miss. When MI_RPN is written, bits in
117 * about the last instruction TLB miss. When MD_RPN is written, bits in
H A Dhugetlb.h157 * entry in the TLB miss handler asm will fault ad infinitum. huge_ptep_set_access_flags()
H A Dmmu-book3e.h311 * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
H A Dpaca.h118 * We can have up to 3 levels of reentrancy in the TLB miss handler,
H A Dpgtable-ppc32.h282 * because everything runs with translation enabled (even the TLB miss
H A Dpgtable.h250 * waiting for the inevitable extra hash-table miss exception.
/linux-4.4.14/arch/m32r/mm/
H A Dmmu.S40 bnez r1, 1f ; instruction TLB miss?
42 ;; data TLB miss
71 ;; instrucntion TLB miss
226 beqz r1, 1f ; data TLB miss?
228 ;; instrucntion TLB miss
243 ;; data TLB miss
/linux-4.4.14/arch/arc/include/asm/
H A Dtlb-mmu1.h50 ; Inefficient due to two-register paradigm of this miss handler
80 ; Always checks whether instruction will be kicked out by dtlb miss variable
H A Dbarrier.h16 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
/linux-4.4.14/arch/alpha/oprofile/
H A Dop_model_ev67.c122 PM_ITB_MISS, /* ITB miss */
123 PM_DTB_MISS, /* DTB miss */
126 PM_ICACHE_MISS, /* Icache miss */
194 to PALcode. Recognize ITB miss by PALcode ev67_handle_interrupt()
/linux-4.4.14/arch/sh/mm/
H A Dtlbex_32.c2 * TLB miss handler for SH with an MMU.
H A Dtlbex_64.c2 * The SH64 TLB miss.
H A Dcache-sh5.c217 miss handling will be OK (TBC). Since it's for the current process, sh64_icache_inv_current_user_range()
357 * in the TLB miss handling).
H A Dfault.c375 /* ITLB miss on NX page */ access_error()
/linux-4.4.14/arch/nios2/include/asm/
H A Dmmu_context.h22 * For the fast tlb miss handlers, we keep a pointer to the current pgd.
/linux-4.4.14/drivers/md/bcache/
H A Drequest.c284 * From a cache miss, we can just insert the keys for the data bch_data_insert_start()
505 * Read from a single key, handling the initial cache miss if the key starts in
530 /* if this was a complete miss we shouldn't get here */ cache_lookup_fn()
734 * We had a cache miss; cache_bio now contains data ready to be inserted cached_dev_read_done()
791 struct bio *miss, *cache_bio; cached_dev_cache_miss() local
794 miss = bio_next_split(bio, sectors, GFP_NOIO, s->d->bio_split); cached_dev_cache_miss()
795 ret = miss == bio ? MAP_DONE : MAP_CONTINUE; cached_dev_cache_miss()
817 miss = bio_next_split(bio, sectors, GFP_NOIO, s->d->bio_split); cached_dev_cache_miss()
820 ret = miss == bio ? MAP_DONE : -EINTR; cached_dev_cache_miss()
828 cache_bio->bi_iter.bi_sector = miss->bi_iter.bi_sector; cached_dev_cache_miss()
829 cache_bio->bi_bdev = miss->bi_bdev; cached_dev_cache_miss()
842 s->cache_miss = miss; cached_dev_cache_miss()
851 miss->bi_end_io = request_endio; cached_dev_cache_miss()
852 miss->bi_private = &s->cl; cached_dev_cache_miss()
853 closure_bio_submit(miss, &s->cl); cached_dev_cache_miss()
H A Dbtree.h91 * miss and we wish to insert this data into the cache, we have to insert a
/linux-4.4.14/kernel/locking/
H A Dpercpu-rwsem.c131 * the fast-past, so we can not miss the result of __this_cpu_add() percpu_down_write()
154 * to ensure the reader can't miss the changes done by us. percpu_up_write()
H A Drwsem-spinlock.c91 * otherwise we could miss the wakeup on the other __rwsem_do_wake()
/linux-4.4.14/arch/mn10300/include/asm/
H A Dexceptions.h32 EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */
33 EXCEP_DTLBMISS = 0x000108, /* data TLB miss */
H A Dcpu-regs.h155 #define sISR_ITMISS 0x00010000 /* instruction TLB miss */
156 #define sISR_DTMISS 0x00020000 /* data TLB miss */
292 #define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */
/linux-4.4.14/arch/openrisc/include/asm/
H A Dspr_defs.h475 #define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
476 #define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
494 #define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
495 #define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
512 #define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
513 #define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
517 #define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
518 #define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
/linux-4.4.14/arch/openrisc/mm/
H A Dinit.c159 /* Since the old TLB miss handler has been running up until now, paging_init()
195 /* New TLB miss handlers and kernel page tables are in now place. paging_init()
/linux-4.4.14/arch/frv/kernel/
H A Dbreak.S40 .space 2*4 /* saved PCSR, PSR for TLB-miss handler fixup */
82 # catch the return from a TLB-miss handler that had single-step disabled
166 # handle BREAK instruction in TLB-miss handler return path
409 # step through an ITLB-miss handler from user mode
454 # step through a DTLB-miss handler from user mode
463 # step through an ITLB-miss handler from kernel mode
472 # step through a DTLB-miss handler from kernel mode
783 # handle a return from TLB-miss that requires single-step reactivation
/linux-4.4.14/arch/ia64/include/asm/
H A Dkregs.h120 #define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
122 #define IA64_DCR_DK_BIT 10 /* defer key miss faults */
H A Dmeminit.h57 #define IGNORE_PFN0 1 /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */
H A Dasmmacro.h70 * path (ivt.S - TLB miss processing) or in places where it might not be
/linux-4.4.14/arch/m32r/include/asm/
H A Dm32r.h112 #define MESTS_IT (1 << 0) /* Instruction TLB miss */
114 #define MESTS_DT (1 << 4) /* Operand TLB miss */
/linux-4.4.14/drivers/net/ethernet/mellanox/mlxsw/
H A Dtrap.h40 /* Ethernet EMAD and FDB miss */
/linux-4.4.14/arch/powerpc/perf/
H A De6500-pmu.c64 * There are data/instruction MMU misses, but that's a miss on
H A De500-pmu.c65 * There are data/instruction MMU misses, but that's a miss on
/linux-4.4.14/arch/score/include/asm/
H A Dmmu_context.h14 * For the fast tlb miss handlers, we keep a per cpu array of pointers
/linux-4.4.14/arch/sparc/kernel/
H A Dleon_pmc.c47 * MMU does not get a TLB miss here by using the MMU BYPASS ASI. pmc_leon_idle_fixup()
H A Dtsb.S16 /* Invoked from TLB miss handler, we are in the
142 * miss.
H A Dktlb.S1 /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
H A Dsun4v_tlb_miss.S1 /* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
/linux-4.4.14/arch/mips/lib/
H A Dmips-atomic.c31 * page and fetching the next instruction causes TLB miss, the result
/linux-4.4.14/arch/parisc/mm/
H A Dfault.c102 * Data TLB miss fault/data page fault parisc_acctyp()
303 case 15: /* Data TLB miss fault/Data page fault */ do_page_fault()
321 case 17: /* NA data TLB miss / page fault */ do_page_fault()
326 case 16: /* Non-access instruction TLB miss fault */ do_page_fault()
/linux-4.4.14/arch/unicore32/mm/
H A Dfault.c421 { do_pf, SIGSEGV, SEGV_MAPERR, "page miss" },
422 { do_bad, SIGBUS, 0, "middle page miss" },
423 { do_bad, SIGBUS, 0, "large page miss" },
424 { do_pf, SIGSEGV, SEGV_MAPERR, "super page (section) miss" },
/linux-4.4.14/arch/alpha/include/asm/
H A Dmce.h40 unsigned long va; /* Effective VA of fault or miss. */
H A Dcore_apecs.h350 unsigned long va; /* Effective VA of fault or miss. */
/linux-4.4.14/net/wireless/
H A Dwext-proc.c64 stats->discard.misc, stats->miss.beacon); wireless_seq_printf_stats()
/linux-4.4.14/include/uapi/linux/
H A Datmmpc.h106 #define DATA_PLANE_PURGE 208 /* Data plane purge because of egress cache hit miss or dead MPS */
H A Dperf_event.h901 /* memory hierarchy (memory level, hit or miss) */
904 #define PERF_MEM_LVL_MISS 0x04 /* miss level */
922 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */
934 #define PERF_MEM_TLB_MISS 0x04 /* miss level */
/linux-4.4.14/arch/parisc/kernel/
H A Dentry.S186 * that the tlb miss handlers are close to final form.
189 /* Register definitions for tlb miss handler macros */
197 * itlb miss interruption handler (parisc 1.1 - 32 bit)
211 * itlb miss interruption handler (parisc 2.0)
228 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
242 * naitlb miss interruption handler (parisc 2.0)
260 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
274 * dtlb miss interruption handler (parisc 2.0)
291 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
303 /* nadtlb miss interruption handler (parisc 2.0) */
1059 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1124 * Note for all tlb miss handlers:
1406 * I miss is a little different, since we allow users to fault
1430 * I miss is a little different, since we allow users to fault
2056 * get_register is used by the non access tlb miss handlers to
2135 * set_register is used by the non access tlb miss handlers to
H A Dtime.c56 * disabled, so we may miss one or more ticks.
99 * We want IT to fire modulo clocktick even if we miss/skip some. timer_interrupt()
H A Dtraps.c567 /* Instruction TLB miss fault/Instruction page fault */ handle_interruption()
649 /* Data TLB miss fault/Data page fault */ handle_interruption()
652 /* Non-access instruction TLB miss fault */ handle_interruption()
657 /* Non-access data TLB miss fault/Non-access data page fault */ handle_interruption()
H A Dpacache.S25 * so that the fast path emulation in the non access miss handler
551 * Subtle: the dtlb miss handlers support the temp alias region by
552 * "knowing" that if a dtlb miss happens within the temp alias
559 * miss on the translation, the dtlb miss handler inserts the
H A Dperf_images.h131 * ctr2: total cycles in the miss handlers
177 * ctr1: counts dmisses inside tlb miss handlers
178 * ctr2: counts cycles in the tlb miss handlers
1572 * IRTN_AV fires twice for every I-cache miss returning from RIB to the IFU.
1573 * It will not fire if a second I-cache miss is issued from the IFU to RIB
1577 * The ratio of I-cache miss transactions on Runway to the ICORE_AV count is
1586 * This should be just I-cache miss and I-prefetch transactions.
2199 * ctr2: total cycles in the miss handlers
2245 * ctr1: dmisses inside the TLB miss handler
2246 * ctr2: cycles in the TLB miss handler
/linux-4.4.14/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/
H A DEventClass.py78 # DSE: Data Source Encoding, where the latency happens, hit or miss
/linux-4.4.14/arch/ia64/kernel/
H A Divt.S96 * (the "original") TLB miss, which may either be caused by an instruction
99 * What we do here is normal TLB miss handing for the _original_ miss,
104 * miss gets inserted only if the pte entry indicates that the page is
111 MOV_FROM_IFA(r16) // get address that caused the TLB miss
177 MOV_FROM_ISR(r19) // cr.isr bit 32 tells us if this is an insn miss
180 MOV_FROM_IHA(r22) // get the VHPT address that caused the TLB miss
182 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
253 * page table. If a nested TLB miss occurs, we switch into physical
297 * page table. If a nested TLB miss occurs, we switch into physical
339 MOV_FROM_IFA(r16) // get address that caused the TLB miss
377 MOV_FROM_IFA(r16) // get address that caused the TLB miss
435 * table is missing, a nested TLB miss fault is triggered and control is
535 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
799 // If any of the above loads miss in L1D, we'll stall here until
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A Dcommon-beacon.c51 * time to receive beacons, and configures the beacon miss handling so
94 * Calculate the number of consecutive beacons to miss* before taking ath9k_cmn_beacon_config_sta()
H A Dwow.c249 * To avoid false wake, we enable beacon miss interrupt only ath9k_suspend()
H A Dbeacon.c339 * a problem and should not occur. If we miss too ath9k_beacon_tasklet()
412 * again. If we miss a beacon for that slot then we'll be ath9k_beacon_tasklet()
H A Dcommon.c54 * Key miss events are only relevant for pairwise keys where the ath9k_cmn_rx_accept()
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dperf_event_intel_ds.c61 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
172 * 0 = did not miss 2nd level TLB load_latency_data()
H A Dvmware.c120 * kernel may miss a wrap of the counter if the vcpu is descheduled for a
/linux-4.4.14/arch/arc/kernel/
H A Dentry-arcv2.S31 VECTOR EV_TLBMissI ; Intruction TLB miss
32 VECTOR EV_TLBMissD ; Data TLB miss
H A Dentry-compact.S122 VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
123 VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
/linux-4.4.14/kernel/trace/
H A Dtrace_branch.c261 * The miss is overlayed on correct, and hit on incorrect. branch_stat_show()
355 seq_puts(m, " miss hit % " all_branch_stat_headers()
/linux-4.4.14/arch/mips/include/asm/
H A Dwar.h122 * CACHE instructions should be separated from any potential data cache miss
170 * accessing memory if the previous icache miss was also to that line.
H A Dmmu_context.h53 * For the fast tlb miss handlers, we keep a per cpu array of pointers
H A Dpgtable-32.h26 * TLB before trap_init() puts the TLB miss handler in place. It
/linux-4.4.14/lib/
H A Dbtree.c333 goto miss; btree_get_prev()
337 goto miss; btree_get_prev()
342 goto miss; btree_get_prev()
350 goto miss; btree_get_prev()
353 miss: btree_get_prev()
/linux-4.4.14/arch/openrisc/kernel/
H A Dentry.S220 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part
520 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
523 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
639 * disabled the rest of the way here because we can't afford to miss any
963 * effective addresses and beeing interrupted by iTLB miss would kill it.
964 * dTLB miss seams to never accour in the bad place since data accesses
969 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
H A Dhead.S74 * TLB miss handlers temorary stores
339 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
344 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
767 /* ---[ boot dtlb miss handler ]----------------------------------------- */
861 /* ---[ boot itlb miss handler ]----------------------------------------- */
960 /* ==============================================[ DTLB miss handler ]=== */
977 * get EA of the miss
1070 /* ==============================================[ ITLB miss handler ]=== */
1078 * get EA of the miss
/linux-4.4.14/drivers/iommu/
H A Dmsm_iommu.c156 /* TLB miss configuration: perform HTW on miss */ __program_context()
196 * the TLB miss penalty. __program_context()
/linux-4.4.14/arch/m32r/kernel/
H A Dentry.S164 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
212 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
229 DISABLE_INTERRUPTS(r4) ; make sure we don't miss an interrupt
/linux-4.4.14/drivers/vfio/
H A Dvirqfd.c173 * before we registered and trigger it as if we didn't miss it. vfio_virqfd_enable()
/linux-4.4.14/drivers/net/ethernet/arc/
H A Demac_main.c551 unsigned long miss, rxerr; arc_emac_stats() local
555 miss = arc_reg_get(priv, R_MISS); arc_emac_stats()
561 stats->rx_errors += miss; arc_emac_stats()
567 stats->rx_missed_errors += miss; arc_emac_stats()
/linux-4.4.14/arch/x86/mm/
H A Dpageattr-test.c94 " 4k %lu large %lu gb %lu x %lu[%lx-%lx] miss %lu\n", print_split()
H A Dmmio-mod.c410 pr_warning("multiple CPUs still online, may miss events.\n");
434 pr_warning("multiple CPUs are online, may miss events. " enter_uniprocessor()
/linux-4.4.14/arch/alpha/lib/
H A Dev6-copy_page.S57 less important than the dcache miss case. */
/linux-4.4.14/net/caif/
H A Dcffrml.c106 * get a cache-miss. cffrml_receive()
/linux-4.4.14/include/linux/
H A Drbtree.h118 * rb_erase() may rebalance the tree, causing us to miss some nodes.
H A Ddcache.h479 * a true miss, a whiteout that isn't represented by a 0,0 chardev or a
486 * type field of the flags may be set to something other than miss or whiteout.
H A Dcompiler.h95 unsigned long miss; member in struct:ftrace_branch_data::__anon12195::__anon12197
H A Dseqlock.h354 * to miss an entire modification sequence, once it resumes it might
/linux-4.4.14/arch/mips/kernel/
H A Dentry.S47 local_irq_disable # make sure we dont miss an
H A Dsmp.c202 * set the bits for every online CPU so we don't miss stop_this_cpu()
/linux-4.4.14/arch/score/mm/
H A Dtlb-score.c176 if (idx < 0) /* p_bit(31) - 1: miss, 0: hit*/ local_flush_tlb_page()
/linux-4.4.14/arch/sh/include/asm/
H A Dthread_info.h21 #define FAULT_CODE_ITLB (1 << 2) /* ITLB miss */
/linux-4.4.14/arch/sparc/include/asm/
H A Dmmu_context_64.h87 /* We have to be extremely careful here or else we will miss switch_mm()
H A Dtsb.h10 * TLB miss trap handler software does the actual lookup via something
/linux-4.4.14/arch/nios2/kernel/
H A Dcpuinfo.c119 cpuinfo.fast_tlb_miss_exc_addr = fcpu(cpu, "altr,fast-tlb-miss-addr"); setup_cpuinfo()
H A Dsetup.c72 /* Copy the fast TLB miss handler */ copy_fast_tlb_miss_handler()
H A Dentry.S86 .word unhandled_exception /* 12 - Double TLB miss (data) */
142 * whether it's trap, tlb-miss or interrupt. If we don't do this
/linux-4.4.14/arch/blackfin/kernel/cplb-nompu/
H A Dcplbmgr.c5 * Description: CPLB miss handler.
/linux-4.4.14/drivers/net/wireless/ath/ath5k/
H A Ddesc.h74 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 /* key cache miss */
100 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 /* key cache miss */
/linux-4.4.14/arch/microblaze/mm/
H A Dfault.c100 /* On a kernel SLB miss we can only check for a valid exception entry */ do_page_fault()
106 /* for instr TLB miss and instr storage exception ESR_S is undefined */ do_page_fault()
/linux-4.4.14/arch/arm/mm/
H A Dproc-v6.S231 * corruption with hit-under-miss enabled). The conditional code below
233 * and the FI bit in the control register) disables hit-under-miss
/linux-4.4.14/tools/perf/util/
H A Dsort.c786 u64 hit, miss; hist_entry__tlb_snprintf() local
794 miss = m & PERF_MEM_TLB_MISS; hist_entry__tlb_snprintf()
813 if (miss) hist_entry__tlb_snprintf()
814 strncat(out, " miss", sz - l); hist_entry__tlb_snprintf()
863 u64 hit, miss; hist_entry__lvl_snprintf() local
871 miss = m & PERF_MEM_LVL_MISS; hist_entry__lvl_snprintf()
890 if (miss) hist_entry__lvl_snprintf()
891 strncat(out, " miss", sz - l); hist_entry__lvl_snprintf()
H A Dstat-shadow.c75 * more semantic information such as miss/hit ratios,
/linux-4.4.14/arch/sh/kernel/cpu/sh5/
H A Dentry.S270 /* Set args for Non-debug, Not a TLB miss class handler */
391 /* Set args for Non-debug, TLB miss class handler */
622 /* Set args for Non-debug, Not a TLB miss class handler */
652 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault, 3=debug)
1075 * (r4) Event (0 = interrupt, 1 = TLB miss fault, 2 = Not TLB miss fault)
1109 /* ITLB miss */
1154 * (r4) Not used. Event (0=interrupt, 1=TLB miss fault, 2=Not TLB miss fault)
/linux-4.4.14/drivers/block/
H A Dps3vram.c65 unsigned int miss; member in struct:ps3vram_cache
400 cache->miss++; ps3vram_cache_match()
522 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); ps3vram_proc_show()
/linux-4.4.14/arch/c6x/kernel/
H A Dentry.S266 ;; make sure we don't miss an interrupt setting need_resched or
308 ;; make sure we don't miss an interrupt setting need_resched or
372 ;; make sure we don't miss an interrupt setting need_resched or
/linux-4.4.14/arch/parisc/include/uapi/asm/
H A Dpdc.h129 #define PDC_TLB 19 /* manage hardware TLB miss handling */
131 #define PDC_TLB_SETUP 1 /* set up miss handling */
/linux-4.4.14/arch/frv/include/asm/
H A Dspr-regs.h233 #define ESR0_ATXC_MMU_MISS 0x00000000 /* - MMU miss exception and more (?) */
236 #define ESR0_ATXC_AMRTLB_MISS 0x00a00000 /* - MMU/TLB miss exception */
/linux-4.4.14/drivers/net/ethernet/mellanox/mlx5/core/
H A Dhealth.c261 dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n"); poll_health()
/linux-4.4.14/arch/tile/include/uapi/arch/
H A Dchip_tilegx.h119 /** Do uncacheable requests miss in the cache regardless of whether
H A Dchip_tilepro.h119 /** Do uncacheable requests miss in the cache regardless of whether
/linux-4.4.14/arch/x86/xen/
H A Dspinlock.c50 * that we won't miss a wakeup event because of the clearing. xen_qlock_wait()
/linux-4.4.14/arch/xtensa/kernel/
H A Dvectors.S277 * We only allow the ITLB miss exception if we are in kernel space.
386 * a9/a13 gets a 2nd-level miss exception (not hardware TLB refill).
485 * Fixup handler for TLB miss in double exception handler for window owerflow.
552 * TLB miss handler may not be atomic and pointer to page table
H A Dentry.S904 * If the WindowUnderflow code gets a TLB miss the page will get mapped
1363 * We get here if the spill routine causes an exception, e.g. tlb miss.
1508 * TLB miss exceptions. Note that for now, user and kernel miss
/linux-4.4.14/fs/
H A Dutimes.c214 would test only in do_utimes we would miss those invalid SYSCALL_DEFINE3()
/linux-4.4.14/arch/powerpc/kernel/
H A Dpaca.c189 /* On Book3E, initialize the TLB miss exception frames */ setup_paca()
H A Dswsusp_32.S145 * hash miss during the copy, as our hash table will
H A Dhead_32.S485 * Handle TLB miss for instruction on 603/603e.
560 * Handle TLB miss for DATA Load operation on 603/603e
644 * Handle TLB miss for DATA Store on 603/603e
H A Dhead_booke.h258 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
/linux-4.4.14/arch/sparc/boot/
H A Dpiggyback.c164 /* Go back 512 bytes so we do not miss HdrS */ get_hdrs_offset()
/linux-4.4.14/arch/m68k/kernel/
H A Dtraps.c716 case 5: /* 0101 TLB opword X miss */ access_errorcf()
720 case 6: /* 0110 TLB extension word X miss */ access_errorcf()
724 case 10: /* 1010 TLB W miss */ access_errorcf()
727 case 14: /* 1110 TLB R miss */ access_errorcf()
/linux-4.4.14/arch/metag/include/asm/
H A Dcacheflush.h178 * It is assumed this access will miss, as the caller should have just l2c_fence_flush()
/linux-4.4.14/arch/blackfin/kernel/cplb-mpu/
H A Dcplbmgr.c192 * find one, then the fact that we're in the miss handler means icplb_miss()
/linux-4.4.14/net/irda/
H A Dtimer.c56 * we miss it. irlap_start_query_timer()
H A Ddiscovery.c57 * miss some new devices popping up...
H A Dirlmp_frame.c328 * to perform discovery, but we don't want to miss the opportunity
/linux-4.4.14/net/openvswitch/
H A Dvport.h62 * on this port that miss the flow table.
/linux-4.4.14/drivers/video/fbdev/nvidia/
H A Dnv_hw.c510 vpagemiss = 1; /* self generating page miss */ nv10CalcArbitration()
513 crtpagemiss = 2; /* self generating page miss */ nv10CalcArbitration()
527 + cpm_us /* CRT Page miss */ nv10CalcArbitration()
538 crtpagemiss = 1; /* self generating page miss */ nv10CalcArbitration()
539 crtpagemiss += 1; /* MA0 page miss */ nv10CalcArbitration()
/linux-4.4.14/arch/microblaze/kernel/
H A Dhw_exception_handler.S59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
305 /* 18 - Data TLB miss exception */
307 /* 19 - Instruction TLB miss exception */
845 /* Both the instruction and data TLB miss get to this point to load the TLB.
/linux-4.4.14/drivers/edac/
H A Dmce_amd.c204 pr_cont("Copyback parity error on a tag miss.\n"); cat_mc0_mce()
303 ((xec == 2) ? "locked miss" decode_mc0_mce()
/linux-4.4.14/arch/tile/kernel/
H A Dprocess.c430 * are disabled, so we can't take any DMATLB miss or access _switch_to()
466 * entered with interrupts disabled so we don't miss an event
/linux-4.4.14/arch/x86/kernel/
H A Dreboot.c483 * We will miss cases where VMX is not enabled on all CPUs. This emergency_vmx_disable_all()
485 * CPUs anyway. But we can miss it on the small window where KVM emergency_vmx_disable_all()
/linux-4.4.14/mm/
H A Dreadahead.c425 * sequential cache miss ondemand_readahead()
474 * page_cache_sync_readahead() should be called when a cache miss happened:
H A Dmremap.c116 * order guarantees that we won't miss both the old and new ptes). move_ptes()
H A Dvmpressure.c53 * When there are too little pages left to scan, vmpressure() may miss the
/linux-4.4.14/kernel/
H A Dsoftirq.c201 * not miss-qualify lock contexts and miss possible deadlocks.
/linux-4.4.14/fs/proc/
H A Darray.c628 * We might miss some children here if children get_children_pid()
635 * skips N extra children, we miss N tasks." (c) get_children_pid()
/linux-4.4.14/arch/microblaze/include/asm/
H A Dpgtable.h193 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct pte_mkspecial()
198 * is cleared in the TLB miss handler before the TLB entry is loaded. pte_mkspecial()
/linux-4.4.14/arch/mn10300/kernel/
H A Dentry.S90 # make sure we don't miss an interrupt setting need_resched or
128 # make sure we don't miss an interrupt setting need_resched or
/linux-4.4.14/arch/avr32/kernel/
H A Dentry-avr32b.S142 /* The slow path of the TLB miss handler */
224 mask_interrupts /* make sure we don't miss an interrupt
/linux-4.4.14/drivers/scsi/qla2xxx/
H A Dqla_mr.h513 #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
/linux-4.4.14/drivers/staging/lustre/lustre/llite/
H A Dllite_internal.h1122 __u64 sai_miss; /* miss count:
1124 * hidden dentry miss;
1126 * include hidden dentry miss.
1130 unsigned int sai_consecutive_miss; /* consecutive miss */
/linux-4.4.14/drivers/staging/most/hdm-i2c/
H A Dhdm_i2c.c291 * possibility to miss interrupts when ISR is getting executed.
/linux-4.4.14/drivers/media/usb/usbvision/
H A Dusbvision-i2c.c225 hit-and-miss. */ usbvision_i2c_register()
/linux-4.4.14/drivers/mfd/
H A Dtps65910.c489 /* Work around silicon erratum SWCZ010: the tps65910 may miss the tps65910_i2c_probe()
H A Dwm831x-irq.c509 /* Acknowledge now so we don't miss wm831x_irq_thread()
/linux-4.4.14/drivers/misc/
H A Dfsa9480.c505 * the interrupt handler does. So, we don't miss pending and fsa9480_resume()
/linux-4.4.14/drivers/net/wireless/cw1200/
H A Ddebug.c278 seq_printf(seq, "TX miss: %d\n", cw1200_status_show()
/linux-4.4.14/arch/x86/kernel/cpu/mcheck/
H A Dmce_intel.c436 * to not miss any events. intel_init_cmci()
/linux-4.4.14/kernel/sched/
H A Dloadavg.c51 * this would add another cross-cpu cacheline miss and atomic operation
/linux-4.4.14/arch/powerpc/oprofile/
H A Dop_model_power4.c316 /* Were we in our exception vectors or SLB real mode miss handler? */ get_pc()
/linux-4.4.14/arch/sh/kernel/
H A Dhead_32.S71 * Prefetch if possible to reduce cache miss penalty.
/linux-4.4.14/arch/mn10300/mm/
H A Dfault.c107 * - bit 0: TLB miss flag
/linux-4.4.14/arch/ia64/sn/kernel/
H A Dirq.c418 * but we should never miss a real lost interrupt.
/linux-4.4.14/arch/blackfin/kernel/
H A Dprocess.c54 * interrupts here to ensure we don't miss a wakeup call.
H A Dtraps.c310 /* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */ trap_c()
/linux-4.4.14/drivers/infiniband/hw/mlx5/
H A Dmr.c459 cache->ent[c].miss++; alloc_cached_mr()
550 ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir, mlx5_mr_cache_debugfs_init()
551 &ent->miss); mlx5_mr_cache_debugfs_init()
/linux-4.4.14/arch/arc/mm/
H A Dtlb.c85 * as a result of a miss, the removed entry is still allowed to exist in the
90 * During a miss handler, the new "TLBWriteNI" command is used to load
967 * At the time of a TLB miss/installation tlb_paranoid_check()
H A Dtlbex.S411 ; Restore the 4-scratch regs saved by fast path miss handler
/linux-4.4.14/fs/cachefiles/
H A Drdwr.c125 * the monitor may miss the event - so we have to ensure that we do get cachefiles_read_reissue()
299 * the monitor may miss the event - so we have to ensure that we do get cachefiles_read_backing_file_one()
551 * installed, so the monitor may miss the event - so we have to list_for_each_entry_safe()
/linux-4.4.14/drivers/video/fbdev/riva/
H A Driva_hw.c948 vpagemiss = 1; /* self generating page miss */ nv10CalcArbitration()
951 crtpagemiss = 2; /* self generating page miss */ nv10CalcArbitration()
962 +cpm_us /* CRT Page miss */ nv10CalcArbitration()
971 crtpagemiss = 1; /* self generating page miss */ nv10CalcArbitration()
972 crtpagemiss += 1; /* MA0 page miss */ nv10CalcArbitration()
/linux-4.4.14/drivers/usb/wusbcore/
H A Dwa-hc.h367 * it...no RC specific function is called...unless I miss
/linux-4.4.14/drivers/usb/core/
H A Dport.c230 * may miss a suspend event for the SuperSpeed port. link_peers()
/linux-4.4.14/drivers/staging/lustre/lustre/include/
H A Dobd_support.h113 miss the recovery window */
/linux-4.4.14/drivers/media/pci/saa7164/
H A Dsaa7164-bus.c409 printk(KERN_ERR "%s() Unexpected msg miss-match\n", __func__); saa7164_bus_get()
/linux-4.4.14/drivers/input/touchscreen/
H A Dti_am335x_tsc.c365 * bogus, miss-spelled version. titsc_parse_dt()
/linux-4.4.14/drivers/misc/cxl/
H A Dirq.c119 pr_devel("Scheduling segment miss handling for later pe: %i\n", ctx->pe); cxl_irq()
/linux-4.4.14/drivers/net/wireless/ath/wil6210/
H A Dtxrx.h378 * bit 2 : Key miss:1
/linux-4.4.14/drivers/power/
H A Dmax8925_power.c408 /* check for power - can miss interrupt at boot time */ max8925_init_charger()
/linux-4.4.14/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.c109 /* not sure about which phy maps to which msm.. probably I miss some */ hdmi_init()
/linux-4.4.14/fs/nfsd/
H A Dnfscache.c404 * Since the common case is a cache miss followed by an insert, nfsd_cache_lookup()
/linux-4.4.14/scripts/basic/
H A Dfixdep.c90 * we cannot miss a rebuild. Since people tend to not mention totally
/linux-4.4.14/fs/btrfs/
H A Dxattr.c175 * listxattrs) to miss a value, this is specially important do_setxattr()
/linux-4.4.14/include/linux/mtd/
H A Dmap.h78 * to zero, and ensure we'll never miss the end of an comparison (bjd) */
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
H A Dentry.S348 ! 0x400: Instruction and Data TLB miss exception vector
/linux-4.4.14/arch/hexagon/include/asm/
H A Dpgtable.h456 * all zeros for swap entries, which speeds up the miss handler at the cost of
/linux-4.4.14/arch/ia64/lib/
H A Ddo_csum.S238 (pC1[1])adds carry1=1,carry1 // since we miss the last one
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsram242x.S26 * audited and tested to ensure that they don't cause a TLB miss while
H A Dsram243x.S26 * audited and tested to ensure that they don't cause a TLB miss while
/linux-4.4.14/drivers/gpio/
H A Dgpio-bcm-kona.c463 * miss any interrupt occurred during executing them. bcm_kona_gpio_irq_handler()
H A Dgpio-tegra.c290 * miss edges tegra_gpio_irq_handler()
/linux-4.4.14/drivers/misc/sgi-gru/
H A Dgrufault.c492 /* TFH state was idle - no miss pending */ gru_try_dropin()
524 * caused by a TLB miss.
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_psr.c47 * software frontbuffer tracking to make sure it doesn't miss a screen
547 * won't ever miss a flush when bailing out here. intel_psr_work()

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