1/*
2 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
3 *
4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * vineetg: May 2011
12 *  -Userspace unaligned access emulation
13 *
14 * vineetg: Feb 2011 (ptrace low level code fixes)
15 *  -traced syscall return code (r0) was not saved into pt_regs for restoring
16 *   into user reg-file when traded task rets to user space.
17 *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
18 *   were not invoking post-syscall trace hook (jumping directly into
19 *   ret_from_system_call)
20 *
21 * vineetg: Nov 2010:
22 *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
23 *  -To maintain the slot size of 8 bytes/vector, added nop, which is
24 *   not executed at runtime.
25 *
26 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
27 *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
28 *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
29 *   need ptregs anymore
30 *
31 * Vineetg: Oct 2009
32 *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
33 *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
34 *   active (AE bit enabled).  This causes a double fault for a subseq valid
35 *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
36 *   Instr Error could also cause similar scenario, so same there as well.
37 *
38 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
39 *
40 * Vineetg: Aug 28th 2008: Bug #94984
41 *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
42 *   Normally CPU does this automatically, however when doing FAKE rtie,
43 *   we need to explicitly do this. The problem in macros
44 *   FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
45 *   was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
46 *   setting it and not clearing it clears ZOL context
47 *
48 * Vineetg: May 16th, 2008
49 *  - r25 now contains the Current Task when in kernel
50 *
51 * Vineetg: Dec 22, 2007
52 *    Minor Surgery of Low Level ISR to make it SMP safe
53 *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
54 *    - _current_task is made an array of NR_CPUS
55 *    - Access of _current_task wrapped inside a macro so that if hardware
56 *       team agrees for a dedicated reg, no other code is touched
57 *
58 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
59 */
60
61#include <linux/errno.h>
62#include <linux/linkage.h>	/* {EXTRY,EXIT} */
63#include <asm/entry.h>
64#include <asm/irqflags.h>
65
66	.cpu A7
67
68;############################ Vector Table #################################
69
70.macro VECTOR  lbl
71#if 1   /* Just in case, build breaks */
72	j   \lbl
73#else
74	b   \lbl
75	nop
76#endif
77.endm
78
79	.section .vector, "ax",@progbits
80	.align 4
81
82/* Each entry in the vector table must occupy 2 words. Since it is a jump
83 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
84 * will use the 'j limm' form of the intrsuction as long as somewhere is in
85 * a section other than .vector.
86 */
87
88; ********* Critical System Events **********************
89VECTOR   res_service             ; 0x0, Reset Vector	(0x0)
90VECTOR   mem_service             ; 0x8, Mem exception   (0x1)
91VECTOR   instr_service           ; 0x10, Instrn Error   (0x2)
92
93; ******************** Device ISRs **********************
94#ifdef CONFIG_ARC_IRQ3_LV2
95VECTOR   handle_interrupt_level2
96#else
97VECTOR   handle_interrupt_level1
98#endif
99
100VECTOR   handle_interrupt_level1
101
102#ifdef CONFIG_ARC_IRQ5_LV2
103VECTOR   handle_interrupt_level2
104#else
105VECTOR   handle_interrupt_level1
106#endif
107
108#ifdef CONFIG_ARC_IRQ6_LV2
109VECTOR   handle_interrupt_level2
110#else
111VECTOR   handle_interrupt_level1
112#endif
113
114.rept   25
115VECTOR   handle_interrupt_level1 ; Other devices
116.endr
117
118/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
119
120; ******************** Exceptions **********************
121VECTOR   EV_MachineCheck         ; 0x100, Fatal Machine check   (0x20)
122VECTOR   EV_TLBMissI             ; 0x108, Intruction TLB miss   (0x21)
123VECTOR   EV_TLBMissD             ; 0x110, Data TLB miss         (0x22)
124VECTOR   EV_TLBProtV             ; 0x118, Protection Violation  (0x23)
125				 ;         or Misaligned Access
126VECTOR   EV_PrivilegeV           ; 0x120, Privilege Violation   (0x24)
127VECTOR   EV_Trap                 ; 0x128, Trap exception        (0x25)
128VECTOR   EV_Extension            ; 0x130, Extn Intruction Excp  (0x26)
129
130.rept   24
131VECTOR   reserved                ; Reserved Exceptions
132.endr
133
134
135;##################### Scratch Mem for IRQ stack switching #############
136
137ARCFP_DATA int1_saved_reg
138	.align 32
139	.type   int1_saved_reg, @object
140	.size   int1_saved_reg, 4
141int1_saved_reg:
142	.zero 4
143
144/* Each Interrupt level needs its own scratch */
145ARCFP_DATA int2_saved_reg
146	.type   int2_saved_reg, @object
147	.size   int2_saved_reg, 4
148int2_saved_reg:
149	.zero 4
150
151; ---------------------------------------------
152	.section .text, "ax",@progbits
153
154
155reserved:
156	flag 1		; Unexpected event, halt
157
158;##################### Interrupt Handling ##############################
159
160#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
161; ---------------------------------------------
162;  Level 2 ISR: Can interrupt a Level 1 ISR
163; ---------------------------------------------
164ENTRY(handle_interrupt_level2)
165
166	INTERRUPT_PROLOGUE 2
167
168	;------------------------------------------------------
169	; if L2 IRQ interrupted a L1 ISR, disable preemption
170	;
171	; This is to avoid a potential L1-L2-L1 scenario
172	;  -L1 IRQ taken
173	;  -L2 interrupts L1 (before L1 ISR could run)
174	;  -preemption off IRQ, user task in syscall picked to run
175	;  -RTIE to userspace
176	;	Returns from L2 context fine
177	;	But both L1 and L2 re-enabled, so another L1 can be taken
178	;	while prev L1 is still unserviced
179	;
180	;------------------------------------------------------
181
182	; L2 interrupting L1 implies both L2 and L1 active
183	; However both A2 and A1 are NOT set in STATUS32, thus
184	; need to check STATUS32_L2 to determine if L1 was active
185
186	ld r9, [sp, PT_status32]        ; get statu32_l2 (saved in pt_regs)
187	bbit0 r9, STATUS_A1_BIT, 1f     ; L1 not active when L2 IRQ, so normal
188
189	; bump thread_info->preempt_count (Disable preemption)
190	GET_CURR_THR_INFO_FROM_SP   r10
191	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
192	add     r9, r9, 1
193	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
194
1951:
196	;------------------------------------------------------
197	; setup params for Linux common ISR and invoke it
198	;------------------------------------------------------
199	lr  r0, [icause2]
200	and r0, r0, 0x1f
201
202	bl.d  @arch_do_IRQ
203	mov r1, sp
204
205	mov r8,0x2
206	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
207
208	b   ret_from_exception
209
210END(handle_interrupt_level2)
211
212#endif
213
214; ---------------------------------------------
215; User Mode Memory Bus Error Interrupt Handler
216; (Kernel mode memory errors handled via seperate exception vectors)
217; ---------------------------------------------
218ENTRY(mem_service)
219
220	INTERRUPT_PROLOGUE 2
221
222	mov r0, ilink2
223	mov r1, sp
224
225	; User process needs to be killed with SIGBUS, but first need to get
226	; out of the L2 interrupt context (drop to pure kernel mode) and jump
227	; off to "C" code where SIGBUS in enqueued
228	lr  r3, [status32]
229	bclr r3, r3, STATUS_A2_BIT
230	or  r3, r3, (STATUS_E1_MASK|STATUS_E2_MASK)
231	sr  r3, [status32_l2]
232	mov ilink2, 1f
233	rtie
2341:
235	bl  do_memory_error
236	b   ret_from_exception
237END(mem_service)
238
239; ---------------------------------------------
240;  Level 1 ISR
241; ---------------------------------------------
242ENTRY(handle_interrupt_level1)
243
244	INTERRUPT_PROLOGUE 1
245
246	lr  r0, [icause1]
247	and r0, r0, 0x1f
248
249#ifdef CONFIG_TRACE_IRQFLAGS
250	; icause1 needs to be read early, before calling tracing, which
251	; can clobber scratch regs, hence use of stack to stash it
252	push r0
253	TRACE_ASM_IRQ_DISABLE
254	pop  r0
255#endif
256
257	bl.d  @arch_do_IRQ
258	mov r1, sp
259
260	mov r8,0x1
261	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
262
263	b   ret_from_exception
264END(handle_interrupt_level1)
265
266;################### Non TLB Exception Handling #############################
267
268; ---------------------------------------------
269; Protection Violation Exception Handler
270; ---------------------------------------------
271
272ENTRY(EV_TLBProtV)
273
274	EXCEPTION_PROLOGUE
275
276	lr  r2, [ecr]
277	lr  r0, [efa]	; Faulting Data address (not part of pt_regs saved above)
278
279	; Exception auto-disables further Intr/exceptions.
280	; Re-enable them by pretending to return from exception
281	; (so rest of handler executes in pure K mode)
282
283	FAKE_RET_FROM_EXCPN
284
285	mov   r1, sp	; Handle to pt_regs
286
287	;------ (5) Type of Protection Violation? ----------
288	;
289	; ProtV Hardware Exception is triggered for Access Faults of 2 types
290	;   -Access Violaton	: 00_23_(00|01|02|03)_00
291	;			         x  r  w  r+w
292	;   -Unaligned Access	: 00_23_04_00
293	;
294	bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
295
296	;========= (6a) Access Violation Processing ========
297	bl  do_page_fault
298	b   ret_from_exception
299
300	;========== (6b) Non aligned access ============
3014:
302
303	SAVE_CALLEE_SAVED_USER
304	mov r2, sp              ; callee_regs
305
306	bl  do_misaligned_access
307
308	; TBD: optimize - do this only if a callee reg was involved
309	; either a dst of emulated LD/ST or src with address-writeback
310	RESTORE_CALLEE_SAVED_USER
311
312	b   ret_from_exception
313
314END(EV_TLBProtV)
315
316; Wrapper for Linux page fault handler called from EV_TLBMiss*
317; Very similar to ProtV handler case (6a) above, but avoids the extra checks
318; for Misaligned access
319;
320ENTRY(call_do_page_fault)
321
322	EXCEPTION_PROLOGUE
323	lr  r0, [efa]	; Faulting Data address
324	mov   r1, sp
325	FAKE_RET_FROM_EXCPN
326
327	mov blink, ret_from_exception
328	b  do_page_fault
329
330END(call_do_page_fault)
331
332;############# Common Handlers for ARCompact and ARCv2 ##############
333
334#include "entry.S"
335
336;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
337;
338; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
339; IRQ shd definitely not happen between now and rtie
340; All 2 entry points to here already disable interrupts
341
342.Lrestore_regs:
343
344	TRACE_ASM_IRQ_ENABLE
345
346	lr	r10, [status32]
347
348	; Restore REG File. In case multiple Events outstanding,
349	; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
350	; Note that we use realtime STATUS32 (not pt_regs->status32) to
351	; decide that.
352
353	and.f	0, r10, (STATUS_A1_MASK|STATUS_A2_MASK)
354	bz	.Lexcep_or_pure_K_ret
355
356	; Returning from Interrupts (Level 1 or 2)
357
358#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
359
360	; Level 2 interrupt return Path - from hardware standpoint
361	bbit0  r10, STATUS_A2_BIT, not_level2_interrupt
362
363	;------------------------------------------------------------------
364	; However the context returning might not have taken L2 intr itself
365	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
366	; Special considerations needed for the context which took L2 intr
367
368	ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
369	brne r9, event_IRQ2, 149f
370
371	;------------------------------------------------------------------
372	; if L2 IRQ interrupted an L1 ISR,  we'd disabled preemption earlier
373	; so that sched doesn't move to new task, causing L1 to be delayed
374	; undeterministically. Now that we've achieved that, let's reset
375	; things to what they were, before returning from L2 context
376	;----------------------------------------------------------------
377
378	ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
379	bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal
380
381	; decrement thread_info->preempt_count (re-enable preemption)
382	GET_CURR_THR_INFO_FROM_SP   r10
383	ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
384
385	; paranoid check, given A1 was active when A2 happened, preempt count
386	; must not be 0 because we would have incremented it.
387	; If this does happen we simply HALT as it means a BUG !!!
388	cmp     r9, 0
389	bnz     2f
390	flag 1
391
3922:
393	sub     r9, r9, 1
394	st      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
395
396149:
397	INTERRUPT_EPILOGUE 2	; return from level 2 interrupt
398debug_marker_l2:
399	rtie
400
401not_level2_interrupt:
402
403#endif
404
405	INTERRUPT_EPILOGUE 1	; return from level 1 interrupt
406debug_marker_l1:
407	rtie
408
409.Lexcep_or_pure_K_ret:
410
411	;this case is for syscalls or Exceptions or pure kernel mode
412
413	EXCEPTION_EPILOGUE
414debug_marker_syscall:
415	rtie
416
417END(ret_from_exception)
418