1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 *	Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/of_device.h>
27#include <linux/platform_device.h>
28#include <linux/module.h>
29#include <linux/irqdomain.h>
30#include <linux/irqchip/chained_irq.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pm.h>
33
34#define GPIO_BANK(x)		((x) >> 5)
35#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
36#define GPIO_BIT(x)		((x) & 0x7)
37
38#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
39					GPIO_PORT(x) * 4)
40
41#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
42#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
43#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
44#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
45#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
46#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
47#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
48#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)
49
50#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
51#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
52#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
53#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
54#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
55#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
56
57#define GPIO_INT_LVL_MASK		0x010101
58#define GPIO_INT_LVL_EDGE_RISING	0x000101
59#define GPIO_INT_LVL_EDGE_FALLING	0x000100
60#define GPIO_INT_LVL_EDGE_BOTH		0x010100
61#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
62#define GPIO_INT_LVL_LEVEL_LOW		0x000000
63
64struct tegra_gpio_bank {
65	int bank;
66	int irq;
67	spinlock_t lvl_lock[4];
68#ifdef CONFIG_PM_SLEEP
69	u32 cnf[4];
70	u32 out[4];
71	u32 oe[4];
72	u32 int_enb[4];
73	u32 int_lvl[4];
74	u32 wake_enb[4];
75#endif
76};
77
78static struct device *dev;
79static struct irq_domain *irq_domain;
80static void __iomem *regs;
81static u32 tegra_gpio_bank_count;
82static u32 tegra_gpio_bank_stride;
83static u32 tegra_gpio_upper_offset;
84static struct tegra_gpio_bank *tegra_gpio_banks;
85
86static inline void tegra_gpio_writel(u32 val, u32 reg)
87{
88	__raw_writel(val, regs + reg);
89}
90
91static inline u32 tegra_gpio_readl(u32 reg)
92{
93	return __raw_readl(regs + reg);
94}
95
96static int tegra_gpio_compose(int bank, int port, int bit)
97{
98	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
99}
100
101static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
102{
103	u32 val;
104
105	val = 0x100 << GPIO_BIT(gpio);
106	if (value)
107		val |= 1 << GPIO_BIT(gpio);
108	tegra_gpio_writel(val, reg);
109}
110
111static void tegra_gpio_enable(int gpio)
112{
113	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
114}
115
116static void tegra_gpio_disable(int gpio)
117{
118	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
119}
120
121static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
122{
123	return pinctrl_request_gpio(offset);
124}
125
126static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
127{
128	pinctrl_free_gpio(offset);
129	tegra_gpio_disable(offset);
130}
131
132static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
133{
134	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
135}
136
137static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
138{
139	/* If gpio is in output mode then read from the out value */
140	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
141		return (tegra_gpio_readl(GPIO_OUT(offset)) >>
142				GPIO_BIT(offset)) & 0x1;
143
144	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
145}
146
147static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
148{
149	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
150	tegra_gpio_enable(offset);
151	return 0;
152}
153
154static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
155					int value)
156{
157	tegra_gpio_set(chip, offset, value);
158	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
159	tegra_gpio_enable(offset);
160	return 0;
161}
162
163static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
164{
165	return irq_find_mapping(irq_domain, offset);
166}
167
168static struct gpio_chip tegra_gpio_chip = {
169	.label			= "tegra-gpio",
170	.request		= tegra_gpio_request,
171	.free			= tegra_gpio_free,
172	.direction_input	= tegra_gpio_direction_input,
173	.get			= tegra_gpio_get,
174	.direction_output	= tegra_gpio_direction_output,
175	.set			= tegra_gpio_set,
176	.to_irq			= tegra_gpio_to_irq,
177	.base			= 0,
178};
179
180static void tegra_gpio_irq_ack(struct irq_data *d)
181{
182	int gpio = d->hwirq;
183
184	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
185}
186
187static void tegra_gpio_irq_mask(struct irq_data *d)
188{
189	int gpio = d->hwirq;
190
191	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
192}
193
194static void tegra_gpio_irq_unmask(struct irq_data *d)
195{
196	int gpio = d->hwirq;
197
198	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
199}
200
201static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
202{
203	int gpio = d->hwirq;
204	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
205	int port = GPIO_PORT(gpio);
206	int lvl_type;
207	int val;
208	unsigned long flags;
209	int ret;
210
211	switch (type & IRQ_TYPE_SENSE_MASK) {
212	case IRQ_TYPE_EDGE_RISING:
213		lvl_type = GPIO_INT_LVL_EDGE_RISING;
214		break;
215
216	case IRQ_TYPE_EDGE_FALLING:
217		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
218		break;
219
220	case IRQ_TYPE_EDGE_BOTH:
221		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
222		break;
223
224	case IRQ_TYPE_LEVEL_HIGH:
225		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
226		break;
227
228	case IRQ_TYPE_LEVEL_LOW:
229		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
230		break;
231
232	default:
233		return -EINVAL;
234	}
235
236	ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
237	if (ret) {
238		dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
239		return ret;
240	}
241
242	spin_lock_irqsave(&bank->lvl_lock[port], flags);
243
244	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
245	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
246	val |= lvl_type << GPIO_BIT(gpio);
247	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
248
249	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
250
251	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
252	tegra_gpio_enable(gpio);
253
254	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
255		irq_set_handler_locked(d, handle_level_irq);
256	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
257		irq_set_handler_locked(d, handle_edge_irq);
258
259	return 0;
260}
261
262static void tegra_gpio_irq_shutdown(struct irq_data *d)
263{
264	int gpio = d->hwirq;
265
266	gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
267}
268
269static void tegra_gpio_irq_handler(struct irq_desc *desc)
270{
271	int port;
272	int pin;
273	int unmasked = 0;
274	struct irq_chip *chip = irq_desc_get_chip(desc);
275	struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
276
277	chained_irq_enter(chip, desc);
278
279	for (port = 0; port < 4; port++) {
280		int gpio = tegra_gpio_compose(bank->bank, port, 0);
281		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
282			tegra_gpio_readl(GPIO_INT_ENB(gpio));
283		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
284
285		for_each_set_bit(pin, &sta, 8) {
286			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
287
288			/* if gpio is edge triggered, clear condition
289			 * before executing the handler so that we don't
290			 * miss edges
291			 */
292			if (lvl & (0x100 << pin)) {
293				unmasked = 1;
294				chained_irq_exit(chip, desc);
295			}
296
297			generic_handle_irq(gpio_to_irq(gpio + pin));
298		}
299	}
300
301	if (!unmasked)
302		chained_irq_exit(chip, desc);
303
304}
305
306#ifdef CONFIG_PM_SLEEP
307static int tegra_gpio_resume(struct device *dev)
308{
309	unsigned long flags;
310	int b;
311	int p;
312
313	local_irq_save(flags);
314
315	for (b = 0; b < tegra_gpio_bank_count; b++) {
316		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
317
318		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
319			unsigned int gpio = (b<<5) | (p<<3);
320			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
321			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
322			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
323			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
324			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
325		}
326	}
327
328	local_irq_restore(flags);
329	return 0;
330}
331
332static int tegra_gpio_suspend(struct device *dev)
333{
334	unsigned long flags;
335	int b;
336	int p;
337
338	local_irq_save(flags);
339	for (b = 0; b < tegra_gpio_bank_count; b++) {
340		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
341
342		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
343			unsigned int gpio = (b<<5) | (p<<3);
344			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
345			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
346			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
347			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
348			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
349
350			/* Enable gpio irq for wake up source */
351			tegra_gpio_writel(bank->wake_enb[p],
352					  GPIO_INT_ENB(gpio));
353		}
354	}
355	local_irq_restore(flags);
356	return 0;
357}
358
359static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
360{
361	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
362	int gpio = d->hwirq;
363	u32 port, bit, mask;
364
365	port = GPIO_PORT(gpio);
366	bit = GPIO_BIT(gpio);
367	mask = BIT(bit);
368
369	if (enable)
370		bank->wake_enb[port] |= mask;
371	else
372		bank->wake_enb[port] &= ~mask;
373
374	return irq_set_irq_wake(bank->irq, enable);
375}
376#endif
377
378#ifdef	CONFIG_DEBUG_FS
379
380#include <linux/debugfs.h>
381#include <linux/seq_file.h>
382
383static int dbg_gpio_show(struct seq_file *s, void *unused)
384{
385	int i;
386	int j;
387
388	for (i = 0; i < tegra_gpio_bank_count; i++) {
389		for (j = 0; j < 4; j++) {
390			int gpio = tegra_gpio_compose(i, j, 0);
391			seq_printf(s,
392				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
393				i, j,
394				tegra_gpio_readl(GPIO_CNF(gpio)),
395				tegra_gpio_readl(GPIO_OE(gpio)),
396				tegra_gpio_readl(GPIO_OUT(gpio)),
397				tegra_gpio_readl(GPIO_IN(gpio)),
398				tegra_gpio_readl(GPIO_INT_STA(gpio)),
399				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
400				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
401		}
402	}
403	return 0;
404}
405
406static int dbg_gpio_open(struct inode *inode, struct file *file)
407{
408	return single_open(file, dbg_gpio_show, &inode->i_private);
409}
410
411static const struct file_operations debug_fops = {
412	.open		= dbg_gpio_open,
413	.read		= seq_read,
414	.llseek		= seq_lseek,
415	.release	= single_release,
416};
417
418static void tegra_gpio_debuginit(void)
419{
420	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
421					NULL, NULL, &debug_fops);
422}
423
424#else
425
426static inline void tegra_gpio_debuginit(void)
427{
428}
429
430#endif
431
432static struct irq_chip tegra_gpio_irq_chip = {
433	.name		= "GPIO",
434	.irq_ack	= tegra_gpio_irq_ack,
435	.irq_mask	= tegra_gpio_irq_mask,
436	.irq_unmask	= tegra_gpio_irq_unmask,
437	.irq_set_type	= tegra_gpio_irq_set_type,
438	.irq_shutdown	= tegra_gpio_irq_shutdown,
439#ifdef CONFIG_PM_SLEEP
440	.irq_set_wake	= tegra_gpio_irq_set_wake,
441#endif
442};
443
444static const struct dev_pm_ops tegra_gpio_pm_ops = {
445	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
446};
447
448struct tegra_gpio_soc_config {
449	u32 bank_stride;
450	u32 upper_offset;
451};
452
453static struct tegra_gpio_soc_config tegra20_gpio_config = {
454	.bank_stride = 0x80,
455	.upper_offset = 0x800,
456};
457
458static struct tegra_gpio_soc_config tegra30_gpio_config = {
459	.bank_stride = 0x100,
460	.upper_offset = 0x80,
461};
462
463static const struct of_device_id tegra_gpio_of_match[] = {
464	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
465	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
466	{ },
467};
468
469/* This lock class tells lockdep that GPIO irqs are in a different
470 * category than their parents, so it won't report false recursion.
471 */
472static struct lock_class_key gpio_lock_class;
473
474static int tegra_gpio_probe(struct platform_device *pdev)
475{
476	const struct of_device_id *match;
477	struct tegra_gpio_soc_config *config;
478	struct resource *res;
479	struct tegra_gpio_bank *bank;
480	int ret;
481	int gpio;
482	int i;
483	int j;
484
485	dev = &pdev->dev;
486
487	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
488	if (!match) {
489		dev_err(&pdev->dev, "Error: No device match found\n");
490		return -ENODEV;
491	}
492	config = (struct tegra_gpio_soc_config *)match->data;
493
494	tegra_gpio_bank_stride = config->bank_stride;
495	tegra_gpio_upper_offset = config->upper_offset;
496
497	for (;;) {
498		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
499		if (!res)
500			break;
501		tegra_gpio_bank_count++;
502	}
503	if (!tegra_gpio_bank_count) {
504		dev_err(&pdev->dev, "Missing IRQ resource\n");
505		return -ENODEV;
506	}
507
508	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
509
510	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
511			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
512			GFP_KERNEL);
513	if (!tegra_gpio_banks)
514		return -ENODEV;
515
516	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
517					   tegra_gpio_chip.ngpio,
518					   &irq_domain_simple_ops, NULL);
519	if (!irq_domain)
520		return -ENODEV;
521
522	for (i = 0; i < tegra_gpio_bank_count; i++) {
523		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
524		if (!res) {
525			dev_err(&pdev->dev, "Missing IRQ resource\n");
526			return -ENODEV;
527		}
528
529		bank = &tegra_gpio_banks[i];
530		bank->bank = i;
531		bank->irq = res->start;
532	}
533
534	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
535	regs = devm_ioremap_resource(&pdev->dev, res);
536	if (IS_ERR(regs))
537		return PTR_ERR(regs);
538
539	for (i = 0; i < tegra_gpio_bank_count; i++) {
540		for (j = 0; j < 4; j++) {
541			int gpio = tegra_gpio_compose(i, j, 0);
542			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
543		}
544	}
545
546	tegra_gpio_chip.of_node = pdev->dev.of_node;
547
548	ret = gpiochip_add(&tegra_gpio_chip);
549	if (ret < 0) {
550		irq_domain_remove(irq_domain);
551		return ret;
552	}
553
554	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
555		int irq = irq_create_mapping(irq_domain, gpio);
556		/* No validity check; all Tegra GPIOs are valid IRQs */
557
558		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
559
560		irq_set_lockdep_class(irq, &gpio_lock_class);
561		irq_set_chip_data(irq, bank);
562		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
563					 handle_simple_irq);
564	}
565
566	for (i = 0; i < tegra_gpio_bank_count; i++) {
567		bank = &tegra_gpio_banks[i];
568
569		irq_set_chained_handler_and_data(bank->irq,
570						 tegra_gpio_irq_handler, bank);
571
572		for (j = 0; j < 4; j++)
573			spin_lock_init(&bank->lvl_lock[j]);
574	}
575
576	tegra_gpio_debuginit();
577
578	return 0;
579}
580
581static struct platform_driver tegra_gpio_driver = {
582	.driver		= {
583		.name	= "tegra-gpio",
584		.pm	= &tegra_gpio_pm_ops,
585		.of_match_table = tegra_gpio_of_match,
586	},
587	.probe		= tegra_gpio_probe,
588};
589
590static int __init tegra_gpio_init(void)
591{
592	return platform_driver_register(&tegra_gpio_driver);
593}
594postcore_initcall(tegra_gpio_init);
595