interrupt (reference) in projects: linux-4.4.14

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/linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/
D	ti,c64x+megamod-pic.txt	6 The core interrupt controller provides 16 prioritized interrupts to the 8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt 14 - #interrupt-cells: <1> 18 Single cell specifying the core interrupt priority level (4-15) where 23 core_pic: interrupt-controller@0 { 24 interrupt-controller; 25 #interrupt-cells = <1>; 33 The megamodule PIC consists of four interrupt mupliplexers each of which 34 combine up to 32 interrupt inputs into a single interrupt output which 35 may be cascaded into the core interrupt controller. The megamodule PIC [all …]
D	brcm,bcm7120-l2-intc.txt	1 Broadcom BCM7120-style Level 2 interrupt controller 3 This interrupt controller hardware is a second level interrupt controller that 4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based 7 Such an interrupt controller has the following hardware design: 9 - outputs multiple interrupts signals towards its interrupt controller parent 12 directly output an interrupt signal towards the interrupt controller parent, 13 or if they will output an interrupt signal at this 2nd level interrupt 20 - not all bits within the interrupt controller actually map to an interrupt 24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) 26 0 -----[ MUX ] ------------\|==========> GIC interrupt 75 [all …]
D	samsung,exynos4210-combiner.txt	3 Samsung's Exynos4 architecture includes a interrupt combiner controller which 4 can combine interrupt sources as a group and provide a single interrupt request 5 for the group. The interrupt request from each group are connected to a parent 6 interrupt controller, such as GIC in case of Exynos4210. 8 The interrupt combiner controller consists of multiple combiners. Up to eight 9 interrupt sources can be connected to a combiner. The combiner outputs one 10 combined interrupt for its eight interrupt sources. The combined interrupt 11 is usually connected to a parent interrupt controller. 13 A single node in the device tree is used to describe the interrupt combiner 15 interrupt controller module shares config/control registers with other [all …]
D	marvell,orion-intc.txt	1 Marvell Orion SoC interrupt controllers 3 * Main interrupt controller 7 - reg: base address(es) of interrupt registers starting with CAUSE register 8 - interrupt-controller: identifies the node as an interrupt controller 9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1 11 The interrupt sources map to the corresponding bits in the interrupt 18 intc: interrupt-controller { 20 interrupt-controller; 21 #interrupt-cells = <1>; 26 * Bridge interrupt controller [all …]
D	mrvl,intc.txt	6 - reg : Address and length of the register set of the interrupt controller. 7 If the interrupt controller is intc, address and length means the range 8 of the whold interrupt controller. If the interrupt controller is mux-intc, 10 range of intc. mux-intc is secondary interrupt controller. 11 - reg-names : Name of the register set of the interrupt controller. It's 12 only required in mux-intc interrupt controller. 13 - interrupts : Should be the port interrupt shared by mux interrupts. It's 14 only required in mux-intc interrupt controller. 15 - interrupt-controller : Identifies the node as an interrupt controller. 16 - #interrupt-cells : Specifies the number of cells needed to encode an [all …]
D	interrupts.txt	1 Specifying interrupt information for devices 11 properties contain a list of interrupt specifiers, one per output interrupt. The 12 format of the interrupt specifier is determined by the interrupt controller to 16 interrupt-parent = <&intc1>; 19 The "interrupt-parent" property is used to specify the controller to which 20 interrupts are routed and contains a single phandle referring to the interrupt 22 interrupt client node or in any of its parent nodes. Interrupts listed in the 23 "interrupts" property are always in reference to the node's interrupt parent. 26 to reference multiple interrupt parents. Each entry in this property contains 27 both the parent phandle and the interrupt specifier. "interrupts-extended" [all …]
D	abilis,tb10x-ictl.txt	4 The Abilis TB10x SOC contains a custom interrupt controller. It performs 5 one-to-one mapping of external interrupt sources to CPU interrupts and 13 - interrupt-congroller: Identifies the node as an interrupt controller. 14 - #interrupt cells: Specifies the number of cells used to encode an interrupt 16 - interrupt-parent: Specifies the parent interrupt controller. 17 - interrupts: Specifies the list of interrupt lines which are handled by 18 the interrupt controller in the parent controller's notation. Interrupts 24 intc: interrupt-controller { /* Parent interrupt controller / 25 interrupt-controller; 26 #interrupt-cells = <1>; / For example below */ [all …]
D	qca,ath79-misc-intc.txt	1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 3 The MISC interrupt controller is a secondary controller for lower priority 4 interrupt. 10 - interrupt-parent: phandle of the parent interrupt controller. 11 - interrupts: Interrupt specifier for the controllers interrupt. 12 - interrupt-controller : Identifies the node as an interrupt controller 13 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 24 interrupt-controller@18060010 { 28 interrupt-parent = <&cpuintc>; 31 interrupt-controller; [all …]
D	brcm,bcm2835-armctrl-ic.txt	3 The BCM2835 contains a custom top-level interrupt controller, which supports 4 72 interrupt sources using a 2-level register scheme. The interrupt 8 The BCM2836 contains the same interrupt controller with the same 9 interrupts, but the per-CPU interrupt controller is the root, and an 10 interrupt there indicates that the ARMCTRL has an interrupt to handle. 17 - interrupt-controller : Identifies the node as an interrupt controller 18 - #interrupt-cells : Specifies the number of cells needed to encode an 19 interrupt source. The value shall be 2. 21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic 25 The 2nd cell contains the interrupt number within the bank. Valid values [all …]
D	snps,dw-apb-ictl.txt	1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl) 3 Synopsys DesignWare provides interrupt controller IP for APB known as 4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with 11 - interrupt-controller: identifies the node as an interrupt controller 12 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 13 - interrupts: interrupt reference to primary interrupt controller 14 - interrupt-parent: (optional) reference specific primary interrupt controller 16 The interrupt sources map to the corresponding bits in the interrupt 25 aic: interrupt-controller@3000 { 28 interrupt-controller; [all …]
D	img,meta-intc.txt	8 - compatible: Specifies the compatibility list for the interrupt controller. 11 - num-banks: Specifies the number of interrupt banks (each of which can 12 handle 32 interrupt sources). 14 - interrupt-controller: The presence of this property identifies the node 15 as an interrupt controller. No property value shall be defined. 17 - #interrupt-cells: Specifies the number of cells needed to encode an 18 interrupt source. The type shall be a <u32> and the value shall be 2. 22 'interrupt-map' nodes do not have to specify a parent unit address. 32 - <1st-cell>: The interrupt-number that identifies the interrupt source. 34 - <2nd-cell>: The Linux interrupt flags containing level-sense information, [all …]
D	brcm,bcm3380-l2-intc.txt	1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller 3 This interrupt controller shows up in various forms on many BCM338x/BCM63xx 6 - outputs a single interrupt signal to its interrupt controller parent 18 - interrupt-controller: identifies the node as an interrupt controller 19 - #interrupt-cells: specifies the number of cells needed to encode an interrupt 21 - interrupt-parent: specifies the phandle to the parent interrupt controller 23 - interrupts: specifies the interrupt line in the interrupt-parent controller 24 node, valid values depend on the type of parent interrupt controller 33 irq0_intc: interrupt-controller@10000020 { 37 interrupt-controller; [all …]
D	brcm,l2-intc.txt	`7 - interrupt-controller: identifies the node as an interrupt controller 8 - #interrupt-cells: specifies the number of cells needed to encode an 9 interrupt source. Should be 1. 10 - interrupt-parent: specifies the phandle to the parent interrupt controller 12 - interrupts: specifies the interrupt line in the interrupt-parent irq space 22 hif_intr2_intc: interrupt-controller@f0441000 { 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 interrupt-parent = <&intc>;`
D	ingenic,intc.txt	`11 - interrupt-controller : Identifies the node as an interrupt controller 12 - #interrupt-cells : Specifies the number of cells needed to encode an 13 interrupt source. The value shall be 1. 14 - interrupt-parent : phandle of the CPU interrupt controller. 15 - interrupts : Specifies the CPU interrupt the controller is connected to. 19 intc: interrupt-controller@10001000 { 23 interrupt-controller; 24 #interrupt-cells = <1>; 26 interrupt-parent = <&cpuintc>;`
D	snps,archs-idu-intc.txt	`3 This optional 2nd level interrupt controller can be used in SMP configurations for 9 - interrupt-controller: This is an interrupt controller. 10 - interrupt-parent: <reference to parent core intc> 11 - #interrupt-cells: Must be <2>. 22 core_intc: core-interrupt-controller { 24 interrupt-controller; 25 #interrupt-cells = <1>; 28 idu_intc: idu-interrupt-controller { 30 interrupt-controller; 31 interrupt-parent = <&core_intc>; [all …]`
D	allwinner,sun67i-sc-nmi.txt	9 - interrupt-controller : Identifies the node as an interrupt controller 10 - #interrupt-cells : Specifies the number of cells needed to encode an 11 interrupt source. The value shall be 2. The first cell is the IRQ number, the 12 second cell the trigger type as defined in interrupt.txt in this directory. 13 - interrupt-parent: Specifies the parent interrupt controller. 14 - interrupts: Specifies the interrupt line (NMI) which is handled by 15 the interrupt controller in the parent controller's notation. This value 22 interrupt-controller; 23 #interrupt-cells = <2>; 25 interrupt-parent = <&gic>;
D	img,pdc-intc.txt	4 representation of a PDC IRQ controller. This has a number of input interrupt 5 lines which can wake the system, and are passed on through output interrupt 10 - compatible: Specifies the compatibility list for the interrupt controller. 16 - interrupt-controller: The presence of this property identifies the node 17 as an interrupt controller. No property value shall be defined. 19 - #interrupt-cells: Specifies the number of cells needed to encode an 20 interrupt source. The type shall be a <u32> and the value shall be 2. 26 - interrupts: List of interrupt specifiers. The first specifier shall be the 27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral 34 - <1st-cell>: The interrupt-number that identifies the interrupt source. [all …]
D	st,spear3xx-shirq.txt	4 of devices. The multiplexor provides a single interrupt to parent 5 interrupt controller (VIC) on behalf of a group of devices. 14 interrupt multiplexor (one node for all groups). A group in the 15 interrupt controller shares config/control registers with other groups. 16 For example, a 32-bit interrupt enable/disable config register can 17 accommodate up to 4 interrupt groups. 24 - interrupt-controller: Identifies the node as an interrupt controller. 25 - #interrupt-cells: should be <1> which basically contains the offset 29 then connected to a parent interrupt controller. Each group is 31 parent) is equal to number of groups. The format of the interrupt [all …]
D	brcm,bcm7038-l1-intc.txt	1 Broadcom BCM7038-style Level 1 interrupt controller 3 This block is a first level interrupt controller that is typically connected 28 - interrupt-controller: identifies the node as an interrupt controller 29 - #interrupt-cells: specifies the number of cells needed to encode an interrupt 31 - interrupt-parent: specifies the phandle to the parent interrupt controller(s) 33 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller 34 node; valid values depend on the type of parent interrupt controller 36 If multiple reg ranges and interrupt-parent entries are present on an SMP 39 reg range and one interrupt-parent is needed. 47 interrupt-controller; [all …]
D	ti,omap4-wugen-mpu	3 All TI OMAP4/5 (and their derivatives) an interrupt controller that 12 - interrupt-controller : Identifies the node as an interrupt controller. 13 - #interrupt-cells : Specifies the number of cells needed to encode an 14 interrupt source. The value must be 3. 15 - interrupt-parent : a phandle to the GIC these interrupts are routed 21 interrupt specifier must be that of the GIC. 22 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs 27 wakeupgen: interrupt-controller@48281000 { 29 interrupt-controller; 30 #interrupt-cells = <3>; [all …]
D	ti,omap2-intc.txt	3 OMAP2/3 are using a TI interrupt controller that can support several 10 - interrupt-controller : Identifies the node as an interrupt controller 11 - #interrupt-cells : Specifies the number of cells needed to encode an 12 interrupt source. The type shall be a <u32> and the value shall be 1. 14 The cell contains the interrupt number in the range [0-128]. 15 - ti,intc-size: Number of interrupts handled by the interrupt controller. 20 intc: interrupt-controller@1 { 22 interrupt-controller; 23 #interrupt-cells = <1>;
D	brcm,bcm2836-l1-intc.txt	`1 BCM2836 per-CPU interrupt controller 3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU 5 peripheral (GPU) events, which chain to the BCM2835-style interrupt 13 - interrupt-controller: Identifies the node as an interrupt controller 14 - #interrupt-cells: Specifies the number of cells needed to encode an 15 interrupt source. The value shall be 1 20 The interrupt sources are as follows: 34 interrupt-controller; 35 #interrupt-cells = <1>; 36 interrupt-parent = <&local_intc>;`
D	nvidia,tegra-ictlr.txt	3 All Tegra SoCs contain a legacy interrupt controller that routes 7 The HW block exposes a number of interrupt controllers, each 19 - interrupt-controller : Identifies the node as an interrupt controller. 20 - #interrupt-cells : Specifies the number of cells needed to encode an 21 interrupt source. The value must be 3. 22 - interrupt-parent : a phandle to the GIC these interrupts are routed 28 interrupt specifier must be that of the GIC. 29 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs 34 ictlr: interrupt-controller@60004000 { 40 interrupt-controller; [all …]
D	samsung,s3c24xx-irq.txt	3 The S3C24XX SoCs contain a custom set of interrupt controllers providing a 4 varying number of interrupt sources. The set consists of a main- and sub- 14 - interrupt-controller : Identifies the node as an interrupt controller 16 - #interrupt-cells : Specifies the number of cells needed to encode an 17 interrupt source. The value shall be 4 and interrupt descriptor shall 27 ctrl_irq contains the interrupt bit of the controller 32 interrupt-controller@4a000000 { 35 interrupt-controller; 36 #interrupt-cells=<4>; 44 interrupt-parent = <&subintc>; [all …]
D	ti,omap-intc-irq.txt	`3 On TI omap2 and 3 the intc interrupt controller can provide 14 - interrupt-controller : Identifies the node as an interrupt controller 15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 17 - interrupts: interrupt reference to primary interrupt controller 23 intc: interrupt-controller@48200000 { 25 interrupt-controller; 26 #interrupt-cells = <1>;`
D	marvell,armada-370-xp-mpic.txt	6 - interrupt-controller: Identifies the node as an interrupt controller. 9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1. 13 for the main interrupt registers, second pair for the per-CPU 14 interrupt registers. For this last pair, to be compliant with SMP 16 automatically map to the interrupt controller registers of the 22 connected as a slave to another interrupt controller. This is 24 connected as a slave to the Cortex-A9 GIC. The provided interrupt 25 indicate to which GIC interrupt the MPIC output is connected. 29 mpic: interrupt-controller@d0020000 { 31 #interrupt-cells = <1>; [all …]
D	arm,vic.txt	4 system for interrupt routing. For multiple controllers they can either be 12 - interrupt-controller : Identifies the node as an interrupt controller 13 - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as 14 the VIC has no configuration options for interrupt sources. The cell is a u32 15 and defines the interrupt number. 21 - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit 22 represents single interrupt source, starting from source 0 at LSb and ending 25 - valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be 27 valid-mask property. A set bit means that this interrupt source can be 29 interrupt sources configurable as wake up sources. [all …]
D	open-pic.txt	4 representation of an Open PIC compliant interrupt controller. This binding is 19 - interrupt-controller: The presence of this property identifies the node 22 - #interrupt-cells: Specifies the number of cells needed to encode an 23 interrupt source. The type shall be a <u32> and the value shall be 2. 27 'interrupt-map' nodes do not have to specify a parent unit address. 34 initialization related to interrupt sources shall be limited to sources 42 - <1st-cell>: The interrupt-number that identifies the interrupt source. 55 * An Open PIC interrupt controller 58 // This is an interrupt controller node. 59 interrupt-controller; [all …]
D	mediatek,sysirq.txt	`4 interrupt. 17 - interrupt-controller : Identifies the node as an interrupt controller 18 - #interrupt-cells : Use the same format as specified by GIC in 20 - interrupt-parent: phandle of irq parent for sysirq. The parent must 21 use the same interrupt-cells format as GIC. 26 sysirq: interrupt-controller@10200100 { 28 interrupt-controller; 29 #interrupt-cells = <3>; 30 interrupt-parent = <&gic>;`
D	nxp,lpc3220-mic.txt	`6 - interrupt-controller: Identifies the node as an interrupt controller. 7 - interrupt-parent: Empty for the interrupt controller itself 8 - #interrupt-cells: The number of cells to define the interrupts. Should be 2. 22 mic: interrupt-controller@40008000 { 24 interrupt-controller; 25 interrupt-parent; 26 #interrupt-cells = <2>; 36 interrupt-parent = <&mic>;`
D	mips-gic.txt	10 - interrupt-controller : Identifies the node as an interrupt controller 11 - #interrupt-cells : Specifies the number of cells needed to encode an 12 interrupt specifier. Should be 3. 13 - The first cell is the type of interrupt, local or shared. 14 See <include/dt-bindings/interrupt-controller/mips-gic.h>. 15 - The second cell is the GIC interrupt number. 16 - The third cell encodes the interrupt flags. 17 See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid 23 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors 39 gic: interrupt-controller@1bdc0000 { [all …]
D	opencores,or1k-pic.txt	`6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with 7 edge triggered interrupt lines or "opencores,or1200-pic" for machines 13 - interrupt-controller : Identifies the node as an interrupt controller 14 - #interrupt-cells : Specifies the number of cells needed to encode an 15 interrupt source. The value shall be 1. 19 intc: interrupt-controller { 21 interrupt-controller; 22 #interrupt-cells = <1>;`
D	ti,cp-intc.txt	`11 - interrupt-controller : Identifies the node as an interrupt controller 12 - #interrupt-cells : Specifies the number of cells needed to encode an 13 interrupt source. The type shall be a <u32> and the value shall be 1. 15 The cell contains the interrupt number in the range [0-128]. 16 - ti,intc-size: Number of interrupts handled by the interrupt controller. 21 intc: interrupt-controller@1 { 23 interrupt-controller; 24 #interrupt-cells = <1>;`
D	qca,ath79-cpu-intc.txt	`1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller 4 the interrupt handler of some devices. This is configured using the 11 - interrupt-controller : Identifies the node as an interrupt controller 12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt 28 interrupt-controller { 31 interrupt-controller; 32 #interrupt-cells = <1>;`
D	digicolor-ic.txt	`6 - reg : Specifies base physical address and size of the interrupt controller 8 - interrupt-controller : Identifies the node as an interrupt controller 9 - #interrupt-cells : Specifies the number of cells needed to encode an 10 interrupt source. The value shall be 1. 15 intc: interrupt-controller@f0000040 { 17 interrupt-controller; 18 #interrupt-cells = <1>;`
D	allwinner,sun4i-ic.txt	`7 - interrupt-controller : Identifies the node as an interrupt controller 8 - #interrupt-cells : Specifies the number of cells needed to encode an 9 interrupt source. The value shall be 1. 13 intc: interrupt-controller { 16 interrupt-controller; 17 #interrupt-cells = <1>;`
D	snps,arc700-intc.txt	`3 The core interrupt controller provides 32 prioritised interrupts (2 levels) 9 - interrupt-controller: This is an interrupt controller. 10 - #interrupt-cells: Must be <1>. 20 intc: interrupt-controller { 22 interrupt-controller; 23 #interrupt-cells = <1>;`
D	axis,crisv32-intc.txt	`9 - interrupt-controller : Identifies the node as an interrupt controller 10 - #interrupt-cells : Specifies the number of cells needed to encode an 11 interrupt source. The type shall be a <u32> and the value shall be 1. 16 intc: interrupt-controller { 19 interrupt-controller; 20 #interrupt-cells = <1>;`
D	renesas,intc-irqpin.txt	14 IRQ pins driven by the interrupt controller hardware module. The base 16 - interrupt-controller: Identifies the node as an interrupt controller. 17 - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in 19 - interrupts: Must contain a list of interrupt specifiers. For each interrupt 21 referring to the corresponding parent interrupt. 29 - control-parent: disable and enable interrupts on the parent interrupt 42 irqpin1: interrupt-controller@e6900004 { 45 #interrupt-cells = <2>; 46 interrupt-controller;
D	arm,gic.txt	8 Secondary GICs are cascaded into the upward interrupt controller and do not 24 - interrupt-controller : Identifies the node as an interrupt controller 25 - #interrupt-cells : Specifies the number of cells needed to encode an 26 interrupt source. The type shall be a <u32> and the value shall be 3. 28 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI 31 The 2nd cell contains the interrupt number for the interrupt type. 41 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of 43 the interrupt is wired to that CPU. Only valid for PPI interrupts. 54 - interrupts : Interrupt source of the parent interrupt controller on 55 secondary GICs, or VGIC maintenance interrupt on primary GIC (see [all …]
D	ti,keystone-irq.txt	`14 - interrupt-controller : Identifies the node as an interrupt controller 15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 17 - interrupts: interrupt reference to primary interrupt controller 27 interrupt-controller; 28 #interrupt-cells = <1>; 34 interrupt-parent = <&kirq0>;`
D	atmel,aic.txt	`6 - interrupt-controller: Identifies the node as an interrupt controller. 7 - interrupt-parent: For single AIC system, it is an empty property. 8 - #interrupt-cells: The number of cells to define the interrupts. It should be 3. 27 aic: interrupt-controller@fffff000 { 29 interrupt-controller; 30 interrupt-parent; 31 #interrupt-cells = <3>; 36 * An interrupt generating device that is wired to an AIC.`
D	lsi,zevio-intc.txt	`1 TI-NSPIRE interrupt controller 9 - interrupt-controller : Identifies the node as an interrupt controller 13 interrupt-controller { 15 interrupt-controller; 17 #interrupt-cells = <1>;`
/linux-4.4.14/arch/arm64/boot/dts/exynos/
D	exynos7-pinctrl.dtsi	`20 interrupt-controller; 21 interrupt-parent = <&gic>; 22 #interrupt-cells = <2>; 31 interrupt-controller; 32 interrupt-parent = <&gic>; 33 #interrupt-cells = <2>; 42 interrupt-controller; 43 #interrupt-cells = <2>; 50 interrupt-controller; 51 #interrupt-cells = <2>; [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/
D	mpic.txt	6 The Freescale MPIC interrupt controller is found on all PowerQUICC 9 additional cells in the interrupt specifier defining interrupt type 29 - interrupt-controller 32 Definition: Specifies that this node is an interrupt 35 - #interrupt-cells 38 Definition: Shall be 2 or 4. A value of 2 means that interrupt 39 specifiers do not contain the interrupt-type or type-specific 52 the boot program has initialized all interrupt source 57 that any initialization related to interrupt sources shall 73 - last-interrupt-source [all …]
/linux-4.4.14/drivers/of/unittest-data/
D	tests-interrupts.dtsi	`8 interrupt-controller; 9 #interrupt-cells = <1>; 13 interrupt-controller; 14 #interrupt-cells = <3>; 18 interrupt-controller; 19 #interrupt-cells = <2>; 23 #interrupt-cells = <1>; 25 interrupt-map = <1 &test_intc0 9>, 32 #interrupt-cells = <2>; 33 interrupt-map = <0x5000 1 2 &test_intc0 15>; [all …]`
/linux-4.4.14/arch/mips/boot/dts/brcm/
D	bcm7358.dtsi	`27 compatible = "mti,cpu-interrupt-controller"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 52 interrupt-controller; 53 #interrupt-cells = <1>; 55 interrupt-parent = <&cpu_intc>; 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 interrupt-parent = <&periph_intc>; 72 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7360.dtsi	`27 compatible = "mti,cpu-interrupt-controller"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 52 interrupt-controller; 53 #interrupt-cells = <1>; 55 interrupt-parent = <&cpu_intc>; 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 interrupt-parent = <&periph_intc>; 72 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7346.dtsi	`33 compatible = "mti,cpu-interrupt-controller"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 58 interrupt-controller; 59 #interrupt-cells = <1>; 61 interrupt-parent = <&cpu_intc>; 68 interrupt-controller; 69 #interrupt-cells = <1>; 70 interrupt-parent = <&periph_intc>; 78 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7362.dtsi	`33 compatible = "mti,cpu-interrupt-controller"; 35 interrupt-controller; 36 #interrupt-cells = <1>; 58 interrupt-controller; 59 #interrupt-cells = <1>; 61 interrupt-parent = <&cpu_intc>; 68 interrupt-controller; 69 #interrupt-cells = <1>; 70 interrupt-parent = <&periph_intc>; 78 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7435.dtsi	`43 compatible = "mti,cpu-interrupt-controller"; 45 interrupt-controller; 46 #interrupt-cells = <1>; 68 interrupt-controller; 69 #interrupt-cells = <1>; 71 interrupt-parent = <&cpu_intc>; 78 interrupt-controller; 79 #interrupt-cells = <1>; 80 interrupt-parent = <&periph_intc>; 88 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7125.dtsi	`31 compatible = "mti,cpu-interrupt-controller"; 33 interrupt-controller; 34 #interrupt-cells = <1>; 56 interrupt-controller; 57 #interrupt-cells = <1>; 59 interrupt-parent = <&cpu_intc>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 76 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm7420.dtsi	`31 compatible = "mti,cpu-interrupt-controller"; 33 interrupt-controller; 34 #interrupt-cells = <1>; 56 interrupt-controller; 57 #interrupt-cells = <1>; 59 interrupt-parent = <&cpu_intc>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 76 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm3384_zephyr.dtsi	`35 compatible = "mti,cpu-interrupt-controller"; 37 interrupt-controller; 38 #interrupt-cells = <1>; 67 interrupt-controller; 68 #interrupt-cells = <1>; 70 interrupt-parent = <&cpu_intc>; 78 interrupt-controller; 79 #interrupt-cells = <1>; 81 interrupt-parent = <&periph_intc>; 90 interrupt-controller; [all …]`
D	bcm7425.dtsi	`31 compatible = "mti,cpu-interrupt-controller"; 33 interrupt-controller; 34 #interrupt-cells = <1>; 56 interrupt-controller; 57 #interrupt-cells = <1>; 59 interrupt-parent = <&cpu_intc>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 76 interrupt-parent = <&sun_l2_intc>; [all …]`
D	bcm3384_viper.dtsi	`30 compatible = "mti,cpu-interrupt-controller"; 32 interrupt-controller; 33 #interrupt-cells = <1>; 61 interrupt-controller; 62 #interrupt-cells = <1>; 64 interrupt-parent = <&cpu_intc>; 72 interrupt-controller; 73 #interrupt-cells = <1>; 75 interrupt-parent = <&periph_intc>; 83 interrupt-parent = <&periph_intc>; [all …]`
D	bcm6368.dtsi	`40 compatible = "mti,cpu-interrupt-controller"; 42 interrupt-controller; 43 #interrupt-cells = <1>; 58 interrupt-controller; 59 #interrupt-cells = <1>; 61 interrupt-parent = <&cpu_intc>; 68 interrupt-parent = <&periph_intc>; 78 interrupt-parent = <&periph_intc>; 88 interrupt-parent = <&periph_intc>;`
/linux-4.4.14/Documentation/devicetree/bindings/spmi/
D	qcom,spmi-pmic-arb.txt	7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts 13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for 14 generic interrupt controller binding documentation. 20 "intr" - interrupt controller registers 32 - interrupts : interrupt list for the PMIC Arb controller, must contain a 33 single interrupt entry for the peripheral interrupt 34 - interrupt-names : corresponding interrupt names for the interrupts 36 "periph_irq" - summary interrupt for PMIC peripherals 37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller 38 - #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: [all …]
/linux-4.4.14/Documentation/devicetree/bindings/pci/
D	ralink,rt3883-pci.txt	29 interrupt controller and the PCI host bridge. 35 - interrupt-controller: identifies the node as an interrupt controller 38 address. The value must be 0. As such, 'interrupt-map' nodes do not 41 - #interrupt-cells: specifies the number of cells needed to encode an 42 interrupt source. The value must be 1. 44 - interrupt-parent: the phandle for the interrupt controller that 47 - interrupts: specifies the interrupt source of the parent interrupt 48 controller. The format of the interrupt specifier depends on the 49 parent interrupt controller. 61 - #interrupt-cells: specifies the number of cells needed to encode an [all …]
D	xilinx-pcie.txt	6 - #interrupt-cells: specifies the number of cells needed to encode an 7 interrupt source. The value must be 1. 11 - interrupts: Should contain AXI PCIe interrupt 12 - interrupt-map-mask, 13 interrupt-map: standard PCI properties to define the mapping of the 14 PCI interface to interrupt numbers. 26 - interrupt-controller: identifies the node as an interrupt controller 29 - #interrupt-cells: specifies the number of cells needed to encode an 30 interrupt source. The value must be 1. 33 The core provides a single interrupt for both INTx/MSI messages. So, [all …]
D	pci-keystone.txt	`19 interrupt-cells: should be set to 1 20 interrupt-parent: Parent interrupt controller phandle 21 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines 24 pcie_msi_intc: msi-interrupt-controller { 25 interrupt-controller; 26 #interrupt-cells = <1>; 27 interrupt-parent = <&gic>; 39 interrupt-cells: should be set to 1 40 interrupt-parent: Parent interrupt controller phandle 41 interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines [all …]`
D	altera-pcie.txt	9 - interrupt-parent: interrupt source phandle. 10 - interrupts: specifies the interrupt source of the parent interrupt controller. 11 The format of the interrupt specifier depends on the parent interrupt 16 - #interrupt-cells: set to <1> 19 - interrupt-map-mask and interrupt-map: standard PCI properties to define the 20 mapping of the PCIe interface to interrupt numbers. 33 interrupt-parent = <&hps_0_arm_gic_0>; 35 interrupt-controller; 36 #interrupt-cells = <1>; 42 interrupt-map-mask = <0 0 0 7>; [all …]
D	mvebu-pci.txt	`12 - #interrupt-cells, set to <1> 60 - reg: used only for interrupt mapping, so only the first four bytes 70 - #interrupt-cells, set to <1> 73 - interrupt-map-mask and interrupt-map, standard PCI properties to 74 define the mapping of the PCIe interface to interrupt numbers. 137 #interrupt-cells = <1>; 140 interrupt-map-mask = <0 0 0 0>; 141 interrupt-map = <0 0 0 0 &mpic 58>; 158 #interrupt-cells = <1>; 161 interrupt-map-mask = <0 0 0 0>; [all …]`
D	ti-pci.txt	`15 - interrupts : Two interrupt entries must be specified. The first one is for 16 main interrupt line and the second for MSI interrupt line. 19 #interrupt-cells, 23 interrupt-map-mask, 24 interrupt-map : as specified in ../designware-pcie.txt 46 #interrupt-cells = <1>; 51 interrupt-map-mask = <0 0 0 7>; 52 interrupt-map = <0 0 0 1 &pcie_intc 1>, 56 pcie_intc: interrupt-controller { 57 interrupt-controller; [all …]`
D	samsung,exynos5440-pcie.txt	`10 - interrupts: A list of interrupt outputs for level interrupt, 11 pulse interrupt, special interrupt. 31 #interrupt-cells = <1>; 32 interrupt-map-mask = <0 0 0 0>; 33 interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 51 #interrupt-cells = <1>; 52 interrupt-map-mask = <0 0 0 0>; 53 interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;`
/linux-4.4.14/arch/arm/boot/dts/
D	exynos4415-pinctrl.dtsi	`19 interrupt-controller; 20 #interrupt-cells = <2>; 27 interrupt-controller; 28 #interrupt-cells = <2>; 35 interrupt-controller; 36 #interrupt-cells = <2>; 43 interrupt-controller; 44 #interrupt-cells = <2>; 51 interrupt-controller; 52 #interrupt-cells = <2>; [all …]`
D	exynos5260-pinctrl.dtsi	`24 interrupt-controller; 25 #interrupt-cells = <2>; 32 interrupt-controller; 33 #interrupt-cells = <2>; 40 interrupt-controller; 41 #interrupt-cells = <2>; 48 interrupt-controller; 49 #interrupt-cells = <2>; 56 interrupt-controller; 57 #interrupt-cells = <2>; [all …]`
D	exynos5420-pinctrl.dtsi	`20 interrupt-controller; 21 #interrupt-cells = <2>; 28 interrupt-controller; 29 interrupt-parent = <&combiner>; 30 #interrupt-cells = <2>; 39 interrupt-controller; 40 interrupt-parent = <&combiner>; 41 #interrupt-cells = <2>; 50 interrupt-controller; 51 #interrupt-cells = <2>; [all …]`
D	exynos5250-pinctrl.dtsi	`20 interrupt-controller; 21 #interrupt-cells = <2>; 28 interrupt-controller; 29 #interrupt-cells = <2>; 36 interrupt-controller; 37 #interrupt-cells = <2>; 44 interrupt-controller; 45 #interrupt-cells = <2>; 52 interrupt-controller; 53 #interrupt-cells = <2>; [all …]`
D	mmp2.dtsi	`27 interrupt-parent = <&intc>; 42 intc: interrupt-controller@d4282000 { 44 interrupt-controller; 45 #interrupt-cells = <1>; 50 intcmux4: interrupt-controller@d4282150 { 53 interrupt-controller; 54 #interrupt-cells = <1>; 60 intcmux5: interrupt-controller@d4282154 { 63 interrupt-controller; 64 #interrupt-cells = <1>; [all …]`
D	stih415-pinctrl.dtsi	`10 #include <dt-bindings/interrupt-controller/arm-gic.h> 52 interrupt-names = "irqmux"; 58 interrupt-controller; 59 #interrupt-cells = <2>; 66 interrupt-controller; 67 #interrupt-cells = <2>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 82 interrupt-controller; 83 #interrupt-cells = <2>; [all …]`
D	omap2430.dtsi	`97 #interrupt-cells = <2>; 98 interrupt-controller; 109 #interrupt-cells = <2>; 110 interrupt-controller; 121 #interrupt-cells = <2>; 122 interrupt-controller; 133 #interrupt-cells = <2>; 134 interrupt-controller; 144 #interrupt-cells = <2>; 145 interrupt-controller; [all …]`
D	exynos3250-pinctrl.dtsi	`36 interrupt-controller; 37 #interrupt-cells = <2>; 44 interrupt-controller; 45 #interrupt-cells = <2>; 52 interrupt-controller; 53 #interrupt-cells = <2>; 60 interrupt-controller; 61 #interrupt-cells = <2>; 68 interrupt-controller; 69 #interrupt-cells = <2>; [all …]`
D	stih416-pinctrl.dtsi	`11 #include <dt-bindings/interrupt-controller/arm-gic.h> 56 interrupt-names = "irqmux"; 62 interrupt-controller; 63 #interrupt-cells = <2>; 70 interrupt-controller; 71 #interrupt-cells = <2>; 78 interrupt-controller; 79 #interrupt-cells = <2>; 86 interrupt-controller; 87 #interrupt-cells = <2>; [all …]`
D	spear600.dtsi	`38 vic0: interrupt-controller@f1100000 { 40 interrupt-controller; 42 #interrupt-cells = <1>; 45 vic1: interrupt-controller@f1000000 { 47 interrupt-controller; 49 #interrupt-cells = <1>; 55 interrupt-parent = <&vic1>; 63 interrupt-parent = <&vic1>; 71 interrupt-parent = <&vic1>; 73 interrupt-names = "macirq", "eth_wake_irq"; [all …]`
D	bcm7445.dtsi	`1 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 interrupt-parent = <&gic>; 49 gic: interrupt-controller@ffd00000 { 55 interrupt-controller; 56 #interrupt-cells = <3>; 100 irq0_intc: interrupt-controller@40a780 { 102 interrupt-parent = <&gic>; 103 #interrupt-cells = <1>; 105 interrupt-controller; 112 irq0_aon_intc: interrupt-controller@417280 { [all …]`
D	exynos4x12-pinctrl.dtsi	`37 interrupt-controller; 38 #interrupt-cells = <2>; 45 interrupt-controller; 46 #interrupt-cells = <2>; 53 interrupt-controller; 54 #interrupt-cells = <2>; 61 interrupt-controller; 62 #interrupt-cells = <2>; 69 interrupt-controller; 70 #interrupt-cells = <2>; [all …]`
D	s3c64xx.dtsi	`49 vic0: interrupt-controller@71200000 { 51 interrupt-controller; 53 #interrupt-cells = <1>; 56 vic1: interrupt-controller@71300000 { 58 interrupt-controller; 60 #interrupt-cells = <1>; 66 interrupt-parent = <&vic1>; 77 interrupt-parent = <&vic1>; 88 interrupt-parent = <&vic1>; 99 interrupt-parent = <&vic0>; [all …]`
D	hi3620.dtsi	`72 interrupt-parent = <&gic>; 83 gic: interrupt-controller@1000 { 85 #interrupt-cells = <3>; 87 interrupt-controller; 219 interrupt-controller; 220 #interrupt-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; [all …]`
D	exynos4210-pinctrl.dtsi	`23 interrupt-controller; 24 #interrupt-cells = <2>; 31 interrupt-controller; 32 #interrupt-cells = <2>; 39 interrupt-controller; 40 #interrupt-cells = <2>; 47 interrupt-controller; 48 #interrupt-cells = <2>; 55 interrupt-controller; 56 #interrupt-cells = <2>; [all …]`
D	s5pv210.dtsi	`87 interrupt-parent = <&vic1>; 120 interrupt-parent = <&vic0>; 123 wakeup-interrupt-controller { 126 interrupt-parent = <&vic0>; 139 interrupt-parent = <&vic0>; 151 interrupt-parent = <&vic0>; 164 interrupt-parent = <&vic1>; 180 interrupt-parent = <&vic1>; 196 interrupt-parent = <&vic2>; 206 interrupt-parent = <&vic1>; [all …]`
D	hisi-x5hd2.dtsi	`18 gic: interrupt-controller@f8a01000 { 20 #interrupt-cells = <3>; 22 interrupt-controller; 31 interrupt-parent = <&gic>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 156 interrupt-controller; 157 #interrupt-cells = <2>; 169 interrupt-controller; 170 #interrupt-cells = <2>; [all …]`
D	armada-xp-mv78460.dtsi	`159 #interrupt-cells = <1>; 162 interrupt-map-mask = <0 0 0 0>; 163 interrupt-map = <0 0 0 0 &mpic 58>; 176 #interrupt-cells = <1>; 179 interrupt-map-mask = <0 0 0 0>; 180 interrupt-map = <0 0 0 0 &mpic 59>; 193 #interrupt-cells = <1>; 196 interrupt-map-mask = <0 0 0 0>; 197 interrupt-map = <0 0 0 0 &mpic 60>; 210 #interrupt-cells = <1>; [all …]`
D	s5pv210-pinctrl.dtsi	`27 interrupt-controller; 28 #interrupt-cells = <2>; 35 interrupt-controller; 36 #interrupt-cells = <2>; 43 interrupt-controller; 44 #interrupt-cells = <2>; 51 interrupt-controller; 52 #interrupt-cells = <2>; 59 interrupt-controller; 60 #interrupt-cells = <2>; [all …]`
D	versatile-pb.dts	`12 * Valid interrupt lines mask according to 24 interrupt-controller; 25 #interrupt-cells = <2>; 36 interrupt-controller; 37 #interrupt-cells = <2>; 51 #interrupt-cells = <1>; 57 interrupt-map-mask = <0x1800 0 0 7>; 58 interrupt-map = <0x1800 0 0 1 &sic 28 82 * Overrides the interrupt assignment from 90 interrupt-parent = <&sic>; [all …]`
D	armada-xp-mv78260.dtsi	`138 #interrupt-cells = <1>; 141 interrupt-map-mask = <0 0 0 0>; 142 interrupt-map = <0 0 0 0 &mpic 58>; 155 #interrupt-cells = <1>; 158 interrupt-map-mask = <0 0 0 0>; 159 interrupt-map = <0 0 0 0 &mpic 59>; 172 #interrupt-cells = <1>; 175 interrupt-map-mask = <0 0 0 0>; 176 interrupt-map = <0 0 0 0 &mpic 60>; 189 #interrupt-cells = <1>; [all …]`
D	arm-realview-pb1176.dts	`24 #include <dt-bindings/interrupt-controller/irq.h> 182 intc_dc1176: interrupt-controller@10120000 { 184 #interrupt-cells = <3>; 186 interrupt-controller; 194 interrupt-parent = <&intc_dc1176>; 211 interrupt-parent = <&intc_dc1176>; 218 interrupt-parent = <&intc_dc1176>; 227 interrupt-parent = <&intc_dc1176>; 237 interrupt-parent = <&intc_dc1176>; 247 interrupt-parent = <&intc_dc1176>; [all …]`
D	picoxcell-pc3x2.dtsi	`72 vic0: interrupt-controller@60000 { 74 interrupt-controller; 76 #interrupt-cells = <1>; 79 vic1: interrupt-controller@64000 { 81 interrupt-controller; 83 #interrupt-cells = <1>; 94 interrupt-parent = <&vic0>; 101 interrupt-parent = <&vic0>; 109 interrupt-parent = <&vic0>; 116 interrupt-parent = <&vic0>; [all …]`
D	zynq-7000.dtsi	`47 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>; 71 interrupt-parent = <&intc>; 82 interrupt-parent = <&intc>; 94 interrupt-parent = <&intc>; 104 interrupt-parent = <&intc>; 113 interrupt-parent = <&intc>; 124 interrupt-parent = <&intc>; 131 intc: interrupt-controller@f8f01000 { 133 #interrupt-cells = <3>; [all …]`
D	k2e.dtsi	`19 interrupt-parent = <&gic>; 106 #interrupt-cells = <1>; 107 interrupt-map-mask = <0 0 0 7>; 108 interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ 113 pcie_msi_intc1: msi-interrupt-controller { 114 interrupt-controller; 115 #interrupt-cells = <1>; 116 interrupt-parent = <&gic>; 127 pcie_intc1: legacy-interrupt-controller { 128 interrupt-controller; [all …]`
D	omap3.dtsi	`12 #include <dt-bindings/interrupt-controller/irq.h> 19 interrupt-parent = <&intc>; 109 #interrupt-cells = <1>; 110 interrupt-controller; 148 #interrupt-cells = <1>; 149 interrupt-controller; 198 intc: interrupt-controller@48200000 { 200 interrupt-controller; 201 #interrupt-cells = <1>; 225 interrupt-controller; [all …]`
D	qcom-msm8660.dtsi	`5 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 interrupt-parent = <&intc>; 51 intc: interrupt-controller@2080000 { 53 interrupt-controller; 54 #interrupt-cells = <3>; 77 interrupt-controller; 78 #interrupt-cells = <2>; 119 interrupt-parent = <&tlmm>; 121 #interrupt-cells = <2>; 122 interrupt-controller; [all …]`
D	omap2420.dtsi	`84 #interrupt-cells = <2>; 85 interrupt-controller; 96 #interrupt-cells = <2>; 97 interrupt-controller; 108 #interrupt-cells = <2>; 109 interrupt-controller; 120 #interrupt-cells = <2>; 121 interrupt-controller; 139 interrupts = <59>, /* TX interrupt / 140 <60>; / RX interrupt */ [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/arm/freescale/
D	fsl,vf610-mscm-ir.txt	4 block of registers which control the interrupt router. The interrupt router 5 allows to configure the recipient of each peripheral interrupt. Furthermore 15 - interrupt-controller: Identifies the node as an interrupt controller 16 - #interrupt-cells: Two cells, interrupt number and cells. 17 The hardware interrupt number according to interrupt 18 assignment of the interrupt router is required. 21 - interrupt-parent: Should be the phandle for the interrupt controller of 26 mscm_ir: interrupt-controller@40001800 { 30 interrupt-controller; 31 #interrupt-cells = <2>; [all …]
/linux-4.4.14/arch/arc/boot/dts/
D	abilis_tb101.dtsi	`178 interrupt-controller; 179 #interrupt-cells = <1>; 180 interrupt-parent = <&tb10x_ictl>; 191 interrupt-controller; 192 #interrupt-cells = <1>; 193 interrupt-parent = <&tb10x_ictl>; 204 interrupt-controller; 205 #interrupt-cells = <1>; 206 interrupt-parent = <&tb10x_ictl>; 217 interrupt-controller; [all …]`
D	abilis_tb100.dtsi	`169 interrupt-controller; 170 #interrupt-cells = <1>; 171 interrupt-parent = <&tb10x_ictl>; 182 interrupt-controller; 183 #interrupt-cells = <1>; 184 interrupt-parent = <&tb10x_ictl>; 195 interrupt-controller; 196 #interrupt-cells = <1>; 197 interrupt-parent = <&tb10x_ictl>; 208 interrupt-controller; [all …]`
D	nsimosci_hs_idu.dts	`17 interrupt-parent = <&core_intc>; 36 core_intc: core-interrupt-controller { 38 interrupt-controller; 39 #interrupt-cells = <1>; 43 idu_intc: idu-interrupt-controller { 45 interrupt-controller; 46 interrupt-parent = <&core_intc>; 52 #interrupt-cells = <2>; 64 interrupt-parent = <&idu_intc>; 83 interrupt-parent = <&idu_intc>; [all …]`
D	abilis_tb10x.dtsi	`70 intc: interrupt-controller { 72 interrupt-controller; 73 #interrupt-cells = <1>; 78 interrupt-controller; 79 #interrupt-cells = <2>; 80 interrupt-parent = <&intc>; 92 interrupt-parent = <&tb10x_ictl>; 97 interrupt-parent = <&tb10x_ictl>; 99 interrupt-names = "macirq"; 106 interrupt-parent = <&tb10x_ictl>; [all …]`
D	nsim_hs_idu.dts	`14 interrupt-parent = <&core_intc>; 32 core_intc: core-interrupt-controller { 34 interrupt-controller; 35 #interrupt-cells = <1>; 38 idu_intc: idu-interrupt-controller { 40 interrupt-controller; 41 interrupt-parent = <&core_intc>; 47 #interrupt-cells = <2>; 59 interrupt-parent = <&idu_intc>; 68 #interrupt-cells = <1>;`
D	axc003_idu.dtsi	`28 interrupt-controller; 29 #interrupt-cells = <1>; 32 idu_intc: idu-interrupt-controller { 34 interrupt-controller; 35 interrupt-parent = <&cpu_intc>; 41 #interrupt-cells = <2>; 66 interrupt-controller; 67 #interrupt-cells = <2>; 68 interrupt-parent = <&idu_intc>; 82 interrupt-parent = <&ictl_intc>; [all …]`
D	vdk_axc003_idu.dtsi	`29 interrupt-controller; 30 #interrupt-cells = <1>; 33 idu_intc: idu-interrupt-controller { 35 interrupt-controller; 36 interrupt-parent = <&cpu_intc>; 42 #interrupt-cells = <2>; 51 interrupt-parent = <&idu_intc>; 61 #interrupt-cells = <1>; 64 interrupt-controller; 65 interrupt-parent = <&idu_intc>;`
/linux-4.4.14/arch/metag/boot/dts/
D	tz1090.dtsi	`11 #include <dt-bindings/interrupt-controller/irq.h> 16 interrupt-parent = <&intc>; 18 intc: interrupt-controller { 20 interrupt-controller; 21 #interrupt-cells = <2>; 32 interrupt-controller; 33 #interrupt-cells = <2>; 67 interrupt-controller; 69 #interrupt-cells = <2>; 76 interrupt-controller; [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/gpio/
D	8xxx_gpio.txt	11 The GPIO module usually is connected to the SoC's internal interrupt 12 controller, see bindings/interrupt-controller/interrupts.txt (the 13 interrupt client nodes section) for details how to specify this GPIO 14 module's interrupt. 16 The GPIO module may serve as another interrupt controller (cascaded to 17 the SoC's internal interrupt controller). See the interrupt controller 18 nodes section in bindings/interrupt-controller/interrupts.txt for 28 - interrupt-parent: Phandle for the interrupt controller that 34 - interrupt-controller: Empty boolean property which marks the GPIO 36 - #interrupt-cells: Should be two. Defines the number of integer [all …]
D	mrvl-gpio.txt	9 - interrupts : Should be the port interrupt shared by all gpio pins. 11 gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp, 13 - interrupt-names : Should be the names of irq resources. Each interrupt 14 uses its own interrupt name, so there should be as many interrupt names 16 - interrupt-controller : Identifies the node as an interrupt controller. 17 - #interrupt-cells: Specifies the number of cells needed to encode an 18 interrupt source. 28 interrupt-names = "gpio_mux"; 31 interrupt-controller; 32 #interrupt-cells = <1>; [all …]
D	gpio-max732x.txt	24 an interrupt controller. When the expander interrupt line is connected all the 26 interrupt controller device tree bindings documentation available at 27 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. 29 - interrupt-controller: Identifies the node as an interrupt controller. 30 - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2. 33 - interrupt-parent: phandle of the parent interrupt controller. 34 - interrupts: Interrupt specifier for the controllers interrupt. 39 Example 1. MAX7325 with interrupt support enabled (CONFIG_GPIO_MAX732X_IRQ=y): 46 interrupt-controller; 47 #interrupt-cells = <2>; [all …]
D	brcm,brcmstb-gpio.txt	5 interrupt is shared for all of the banks handled by the controller. 31 The interrupt shared by all GPIO lines for this controller. 33 - interrupt-parent: 34 phandle of the parent interrupt controller 39 'interrupt-parent'. Wakeup-capable GPIO controllers often route their 40 wakeup interrupt lines through a different interrupt controller than the 41 primary interrupt line, making this property necessary. 43 - #interrupt-cells: 52 See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 54 - interrupt-controller: [all …]
D	gpio-altera.txt	11 - interrupt-controller: Mark the device node as an interrupt controller 12 - #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware. 14 - interrupts: Specify the interrupt. 15 - altr,interrupt-trigger: Specifies the interrupt trigger type the GPIO 17 used has IRQ enabled as the interrupt type is not software controlled, 18 but hardware synthesized. Required if GPIO is used as an interrupt 19 controller. The value is defined in <dt-bindings/interrupt-controller/irq.h> 38 altr,interrupt-trigger = <IRQ_TYPE_EDGE_RISING>; 41 #interrupt-cells = <1>; 42 interrupt-controller;
D	gpio-sx150x.txt	`12 - interrupt-parent: phandle of the parent interrupt controller. 14 - interrupts: Interrupt specifier for the controllers interrupt. 22 - interrupt-controller: Marks the device as a interrupt controller. 24 The GPIO expander can optionally be used as an interrupt controller, in 26 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. 32 #interrupt-cells = <2>; 35 interrupt-parent = <&gpio_1>; 39 interrupt-controller;`
D	gpio-mxs.txt	`13 - interrupts : Should be the port interrupt shared by all 32 pins. 19 - interrupt-controller: Marks the device node as an interrupt controller. 20 - #interrupt-cells : Should be 2. The first cell is the GPIO number. 49 interrupt-controller; 50 #interrupt-cells = <2>; 58 interrupt-controller; 59 #interrupt-cells = <2>; 67 interrupt-controller; 68 #interrupt-cells = <2>; 76 interrupt-controller; [all …]`
D	abilis,tb10x-gpio.txt	`13 - interrupt-controller: Marks the device node as an interrupt controller. 14 - #interrupt-cells: Should be <1>. Interrupts are triggered on both edges. 15 - interrupts: Defines the interrupt line connecting this GPIO controller to 16 its parent interrupt controller. 17 - interrupt-parent: Defines the parent interrupt controller. 26 interrupt-controller; 27 #interrupt-cells = <1>; 28 interrupt-parent = <&tb10x_ictl>;`
D	gpio-zynq.txt	`12 - interrupts : Interrupt specifier (see interrupt bindings for 14 - interrupt-parent : Must be core interrupt controller 15 - interrupt-controller : Marks the device node as an interrupt controller. 16 - #interrupt-cells : Should be 2. The first cell is the GPIO number. 30 interrupt-parent = <&intc>; 32 interrupt-controller; 33 #interrupt-cells = <2>;`
D	gpio-ath79.txt	`15 - interrupt-parent: phandle of the parent interrupt controller. 16 - interrupts: Interrupt specifier for the controllers interrupt. 17 - interrupt-controller : Identifies the node as an interrupt controller 18 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 36 interrupt-controller; 37 #interrupt-cells = <2>;`
D	snps-dwapb-gpio.txt	`22 - interrupt-controller : The first port may be configured to be an interrupt 24 - #interrupt-cells : Specifies the number of cells needed to encode an 25 interrupt. Shall be set to 2. The first cell defines the interrupt number, 28 - interrupt-parent : The parent interrupt controller. 29 - interrupts : The interrupt to the parent controller raised when GPIOs 47 interrupt-controller; 48 #interrupt-cells = <2>; 49 interrupt-parent = <&vic1>;`
D	gpio-adnp.txt	`6 - interrupt-parent: phandle of the parent interrupt controller. 7 - interrupts: Interrupt specifier for the controllers interrupt. 14 The GPIO expander can optionally be used as an interrupt controller, in 16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. 24 interrupt-parent = <&gpio>; 30 interrupt-controller; 31 #interrupt-cells = <2>;`
D	gpio-davinci.txt	`15 - interrupt-parent: phandle of the parent interrupt controller. 17 - interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are 22 - ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt 25 The GPIO controller also acts as an interrupt controller. It uses the default 27 interrupt-controller/interrupts.txt. 36 interrupt-parent = <&intc>; 44 interrupt-controller; 45 #interrupt-cells = <2>;`
D	sodaville.txt	`13 The interrupt specifier consists of two cells encoded as follows: 14 - <1st cell>: The interrupt-number that identifies the interrupt source. 22 /* two cells for GPIO and interrupt / 24 #interrupt-cells = <2>; 33 / It is an interrupt and GPIO controller itself / 34 interrupt-controller; 42 level interrupt 45 interrupt-parent = <&pcigpio>;`
/linux-4.4.14/arch/mips/boot/dts/ingenic/
D	jz4780.dtsi	`8 cpuintc: interrupt-controller { 10 #interrupt-cells = <1>; 11 interrupt-controller; 12 compatible = "mti,cpu-interrupt-controller"; 15 intc: interrupt-controller@10001000 { 19 interrupt-controller; 20 #interrupt-cells = <1>; 22 interrupt-parent = <&cpuintc>; 51 interrupt-parent = <&intc>; 64 interrupt-parent = <&intc>; [all …]`
D	jz4740.dtsi	`8 cpuintc: interrupt-controller@0 { 10 #interrupt-cells = <1>; 11 interrupt-controller; 12 compatible = "mti,cpu-interrupt-controller"; 15 intc: interrupt-controller@10001000 { 19 interrupt-controller; 20 #interrupt-cells = <1>; 22 interrupt-parent = <&cpuintc>; 51 interrupt-parent = <&intc>; 62 interrupt-parent = <&intc>;`
/linux-4.4.14/arch/powerpc/boot/dts/
D	c2k.dts	`77 interrupt-parent = <&PIC>; 82 interrupt-parent = <&PIC>; 87 interrupt-parent = <&PIC>; 102 interrupt-parent = <&PIC>; 111 interrupt-parent = <&PIC>; 120 interrupt-parent = <&PIC>; 130 interrupt-base = <0>; 132 interrupt-parent = <&PIC>; 139 interrupt-base = <0>; 141 interrupt-parent = <&PIC>; [all …]`
D	mpc8377_wlan.dts	`58 interrupt-parent = <&ipic>; 107 interrupt-parent = <&ipic>; 116 interrupt-parent = <&ipic>; 134 interrupt-parent = <&ipic>; 152 interrupt-parent = <&ipic>; 165 interrupt-parent = <&ipic>; 174 interrupt-parent = <&ipic>; 184 interrupt-parent = <&ipic>; 191 interrupt-parent = <&ipic>; 198 interrupt-parent = <&ipic>; [all …]`
D	tqm8541.dts	`69 interrupt-parent = <&mpic>; 75 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>; 145 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>; [all …]`
D	tqm8555.dts	`69 interrupt-parent = <&mpic>; 75 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>; 95 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>; 145 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>; [all …]`
D	mpc8610_hpcd.dts	`57 interrupt-parent = <&mpic>; 111 interrupt-parent = <&mpic>; 126 #interrupt-cells = <2>; 142 interrupt-parent = <&mpic>; 152 interrupt-parent = <&mpic>; 170 interrupt-parent = <&mpic>; 182 interrupt-parent = <&mpic>; 193 interrupt-parent = <&mpic>; 204 interrupt-parent = <&mpic>; 224 interrupt-parent = <&mpic>; [all …]`
D	icon.dts	`52 UIC0: interrupt-controller0 { 54 interrupt-controller; 59 #interrupt-cells = <2>; 62 UIC1: interrupt-controller1 { 64 interrupt-controller; 69 #interrupt-cells = <2>; 71 interrupt-parent = <&UIC0>; 74 UIC2: interrupt-controller2 { 76 interrupt-controller; 81 #interrupt-cells = <2>; [all …]`
D	rainier.dts	`57 UIC0: interrupt-controller0 { 59 interrupt-controller; 64 #interrupt-cells = <2>; 67 UIC1: interrupt-controller1 { 69 interrupt-controller; 74 #interrupt-cells = <2>; 76 interrupt-parent = <&UIC0>; 79 UIC2: interrupt-controller2 { 81 interrupt-controller; 86 #interrupt-cells = <2>; [all …]`
D	mpc8349emitxgp.dts	`71 interrupt-parent = <&ipic>; 82 interrupt-parent = <&ipic>; 89 interrupt-parent = <&ipic>; 98 interrupt-parent = <&ipic>; 108 interrupt-parent = <&ipic>; 115 interrupt-parent = <&ipic>; 122 interrupt-parent = <&ipic>; 129 interrupt-parent = <&ipic>; 136 interrupt-parent = <&ipic>; 146 interrupt-parent = <&ipic>; [all …]`
D	mpc8315erdb.dts	`57 interrupt-parent = <&ipic>; 119 interrupt-parent = <&ipic>; 140 interrupt-parent = <&ipic>; 150 interrupt-parent = <&ipic>; 157 interrupt-parent = <&ipic>; 164 interrupt-parent = <&ipic>; 171 interrupt-parent = <&ipic>; 178 interrupt-parent = <&ipic>; 188 interrupt-parent = <&ipic>; 204 interrupt-parent = <&ipic>; [all …]`
D	mpc8377_rdb.dts	`57 interrupt-parent = <&ipic>; 117 interrupt-parent = <&ipic>; 126 interrupt-parent = <&ipic>; 144 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>; 189 interrupt-parent = <&ipic>; 198 interrupt-parent = <&ipic>; 208 interrupt-parent = <&ipic>; 215 interrupt-parent = <&ipic>; 222 interrupt-parent = <&ipic>; [all …]`
D	sequoia.dts	`57 UIC0: interrupt-controller0 { 59 interrupt-controller; 64 #interrupt-cells = <2>; 67 UIC1: interrupt-controller1 { 69 interrupt-controller; 74 #interrupt-cells = <2>; 76 interrupt-parent = <&UIC0>; 79 UIC2: interrupt-controller2 { 81 interrupt-controller; 86 #interrupt-cells = <2>; [all …]`
D	socrates.dts	`71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 97 interrupt-parent = <&mpic>; 108 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>; 144 interrupt-parent = <&mpic>; 156 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>; [all …]`
D	sbc8548-post.dtsi	`33 interrupt-parent = <&mpic>; 39 interrupt-parent = <&mpic>; 48 interrupt-parent = <&mpic>; 59 interrupt-parent = <&mpic>; 70 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 94 interrupt-parent = <&mpic>; 102 interrupt-parent = <&mpic>; 110 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>; [all …]`
D	klondike.dts	`62 UIC0: interrupt-controller { 64 interrupt-controller; 69 #interrupt-cells = <2>; 72 UIC1: interrupt-controller1 { 74 interrupt-controller; 79 #interrupt-cells = <2>; 81 interrupt-parent = <&UIC0>; 84 UIC2: interrupt-controller2 { 86 interrupt-controller; 91 #interrupt-cells = <2>; [all …]`
D	stx_gp3_8560.dts	`68 interrupt-parent = <&mpic>; 74 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>; 94 interrupt-parent = <&mpic>; 110 interrupt-parent = <&mpic>; 118 interrupt-parent = <&mpic>; 126 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>; 161 interrupt-parent = <&mpic>; [all …]`
D	katmai.dts	`56 UIC0: interrupt-controller0 { 58 interrupt-controller; 63 #interrupt-cells = <2>; 66 UIC1: interrupt-controller1 { 68 interrupt-controller; 73 #interrupt-cells = <2>; 75 interrupt-parent = <&UIC0>; 78 UIC2: interrupt-controller2 { 80 interrupt-controller; 85 #interrupt-cells = <2>; [all …]`
D	taishan.dts	`54 UICB0: interrupt-controller-base { 56 interrupt-controller; 61 #interrupt-cells = <2>; 65 UIC0: interrupt-controller0 { 67 interrupt-controller; 72 #interrupt-cells = <2>; 74 interrupt-parent = <&UICB0>; 78 UIC1: interrupt-controller1 { 80 interrupt-controller; 85 #interrupt-cells = <2>; [all …]`
D	haleakala.dts	`50 UIC0: interrupt-controller { 52 interrupt-controller; 57 #interrupt-cells = <2>; 60 UIC1: interrupt-controller1 { 62 interrupt-controller; 67 #interrupt-cells = <2>; 69 interrupt-parent = <&UIC0>; 72 UIC2: interrupt-controller2 { 74 interrupt-controller; 79 #interrupt-cells = <2>; [all …]`
D	stxssa8555.dts	`71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 97 interrupt-parent = <&mpic>; 113 interrupt-parent = <&mpic>; 121 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>; 137 interrupt-parent = <&mpic>; 153 interrupt-parent = <&mpic>; 164 interrupt-parent = <&mpic>; [all …]`
D	arches.dts	`72 UIC0: interrupt-controller0 { 74 interrupt-controller; 79 #interrupt-cells = <2>; 82 UIC1: interrupt-controller1 { 84 interrupt-controller; 89 #interrupt-cells = <2>; 91 interrupt-parent = <&UIC0>; 94 UIC2: interrupt-controller2 { 96 interrupt-controller; 101 #interrupt-cells = <2>; [all …]`
D	mpc885ads.dts	`35 interrupts = <15 2>; // decrementer interrupt 36 interrupt-parent = <&PIC>; 107 interrupt-parent = <&PIC>; 119 interrupt-parent = <&PIC>; 124 PIC: interrupt-controller@0 { 125 interrupt-controller; 126 #interrupt-cells = <2>; 133 #interrupt-cells = <1>; 138 interrupt-parent = <&PIC>; 147 interrupts = <0>; // cpm error interrupt [all …]`
D	mvme5100.dts	`62 interrupt-parent = <&mpic>; 73 interrupt-parent = <&mpic>; 76 mpic: interrupt-controller@f3f80000 { 77 #interrupt-cells = <2>; 81 interrupt-controller; 89 #interrupt-cells = <1>; 93 8259-interrupt-acknowledge = <0xfeff0030>; 98 interrupt-parent = <&mpic>; 99 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 100 interrupt-map = < [all …]`
D	ep88xc.dts	`35 interrupts = <15 2>; // decrementer interrupt 36 interrupt-parent = <&PIC>; 102 interrupt-parent = <&PIC>; 114 interrupt-parent = <&PIC>; 119 PIC: interrupt-controller@0 { 120 interrupt-controller; 121 #interrupt-cells = <2>; 128 #interrupt-cells = <1>; 133 interrupt-parent = <&PIC>; 142 interrupts = <0>; // cpm error interrupt [all …]`
D	mpc8349emitx.dts	`71 interrupt-parent = <&ipic>; 80 interrupt-parent = <&ipic>; 91 interrupt-parent = <&ipic>; 108 interrupt-parent = <&ipic>; 115 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>; 161 interrupt-parent = <&ipic>; 168 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>; 182 interrupt-parent = <&ipic>; [all …]`
D	tqm8540.dts	`70 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>; 96 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>; 146 interrupt-parent = <&mpic>; 162 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>; [all …]`
D	tqm8560.dts	`71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 97 interrupt-parent = <&mpic>; 123 interrupt-parent = <&mpic>; 131 interrupt-parent = <&mpic>; 139 interrupt-parent = <&mpic>; 147 interrupt-parent = <&mpic>; 163 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>; [all …]`
D	obs600.dts	`55 UIC0: interrupt-controller { 57 interrupt-controller; 62 #interrupt-cells = <2>; 65 UIC1: interrupt-controller1 { 67 interrupt-controller; 72 #interrupt-cells = <2>; 74 interrupt-parent = <&UIC0>; 77 UIC2: interrupt-controller2 { 79 interrupt-controller; 84 #interrupt-cells = <2>; [all …]`
D	canyonlands.dts	`52 UIC0: interrupt-controller0 { 54 interrupt-controller; 59 #interrupt-cells = <2>; 62 UIC1: interrupt-controller1 { 64 interrupt-controller; 69 #interrupt-cells = <2>; 71 interrupt-parent = <&UIC0>; 74 UIC2: interrupt-controller2 { 76 interrupt-controller; 81 #interrupt-cells = <2>; [all …]`
D	tqm8548-bigflash.dts	`71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 97 interrupt-parent = <&mpic>; 118 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>; 158 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>; [all …]`
D	eiger.dts	`53 UIC0: interrupt-controller0 { 55 interrupt-controller; 60 #interrupt-cells = <2>; 63 UIC1: interrupt-controller1 { 65 interrupt-controller; 70 #interrupt-cells = <2>; 72 interrupt-parent = <&UIC0>; 75 UIC2: interrupt-controller2 { 77 interrupt-controller; 82 #interrupt-cells = <2>; [all …]`
D	mpc8378_rdb.dts	`57 interrupt-parent = <&ipic>; 117 interrupt-parent = <&ipic>; 126 interrupt-parent = <&ipic>; 144 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>; 189 interrupt-parent = <&ipic>; 198 interrupt-parent = <&ipic>; 208 interrupt-parent = <&ipic>; 215 interrupt-parent = <&ipic>; 222 interrupt-parent = <&ipic>; [all …]`
D	tqm8548.dts	`71 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 86 interrupt-parent = <&mpic>; 97 interrupt-parent = <&mpic>; 118 interrupt-parent = <&mpic>; 134 interrupt-parent = <&mpic>; 142 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>; 158 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>; [all …]`
D	bluestone.dts	`64 UIC0: interrupt-controller0 { 66 interrupt-controller; 71 #interrupt-cells = <2>; 74 UIC1: interrupt-controller1 { 76 interrupt-controller; 81 #interrupt-cells = <2>; 83 interrupt-parent = <&UIC0>; 86 UIC2: interrupt-controller2 { 88 interrupt-controller; 93 #interrupt-cells = <2>; [all …]`
D	makalu.dts	`51 UIC0: interrupt-controller { 53 interrupt-controller; 58 #interrupt-cells = <2>; 61 UIC1: interrupt-controller1 { 63 interrupt-controller; 68 #interrupt-cells = <2>; 70 interrupt-parent = <&UIC0>; 73 UIC2: interrupt-controller2 { 75 interrupt-controller; 80 #interrupt-cells = <2>; [all …]`
D	mpc832x_rdb.dts	`69 interrupt-parent = <&ipic>; 79 interrupt-parent = <&ipic>; 90 interrupt-parent = <&ipic>; 100 interrupt-parent = <&ipic>; 109 interrupt-parent = <&ipic>; 116 interrupt-parent = <&ipic>; 123 interrupt-parent = <&ipic>; 130 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>; 146 interrupt-parent = <&ipic>; [all …]`
D	mpc8379_rdb.dts	`55 interrupt-parent = <&ipic>; 115 interrupt-parent = <&ipic>; 124 interrupt-parent = <&ipic>; 142 interrupt-parent = <&ipic>; 173 interrupt-parent = <&ipic>; 187 interrupt-parent = <&ipic>; 196 interrupt-parent = <&ipic>; 206 interrupt-parent = <&ipic>; 213 interrupt-parent = <&ipic>; 220 interrupt-parent = <&ipic>; [all …]`
D	mpc8641_hpcn_36b.dts	`70 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>; 143 interrupt-parent = <&mpic>; 159 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>; 175 interrupt-parent = <&mpic>; 183 interrupt-parent = <&mpic>; 199 interrupt-parent = <&mpic>; 211 interrupt-parent = <&mpic>; [all …]`
D	mpc836x_rdk.dts	`78 interrupt-parent = <&ipic>; 88 interrupt-parent = <&ipic>; 99 interrupt-parent = <&ipic>; 108 interrupt-parent = <&ipic>; 118 interrupt-parent = <&ipic>; 129 interrupt-parent = <&ipic>; 136 interrupt-parent = <&ipic>; 143 interrupt-parent = <&ipic>; 150 interrupt-parent = <&ipic>; 157 interrupt-parent = <&ipic>; [all …]`
D	mpc8378_mds.dts	`58 interrupt-parent = <&ipic>; 146 interrupt-parent = <&ipic>; 153 interrupt-parent = <&ipic>; 161 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>; 184 interrupt-parent = <&ipic>; 194 interrupt-parent = <&ipic>; 201 interrupt-parent = <&ipic>; 208 interrupt-parent = <&ipic>; 215 interrupt-parent = <&ipic>; [all …]`
D	glacier.dts	`54 UIC0: interrupt-controller0 { 56 interrupt-controller; 61 #interrupt-cells = <2>; 64 UIC1: interrupt-controller1 { 66 interrupt-controller; 71 #interrupt-cells = <2>; 73 interrupt-parent = <&UIC0>; 76 UIC2: interrupt-controller2 { 78 interrupt-controller; 83 #interrupt-cells = <2>; [all …]`
D	kilauea.dts	`51 UIC0: interrupt-controller { 53 interrupt-controller; 58 #interrupt-cells = <2>; 61 UIC1: interrupt-controller1 { 63 interrupt-controller; 68 #interrupt-cells = <2>; 70 interrupt-parent = <&UIC0>; 73 UIC2: interrupt-controller2 { 75 interrupt-controller; 80 #interrupt-cells = <2>; [all …]`
D	gef_sbc310.dts	`77 interrupt-parent = <&mpic>; 135 interrupt-parent = <&gef_pic>; 143 interrupt-parent = <&gef_pic>; 147 #interrupt-cells = <1>; 148 interrupt-controller; 153 interrupt-parent = <&mpic>; 167 #interrupt-cells = <2>; 183 interrupt-parent = <&mpic>; 192 interrupt-parent = <&mpic>; 207 interrupt-parent = <&mpic>; [all …]`
D	sbc8349.dts	`74 interrupt-parent = <&ipic>; 85 interrupt-parent = <&ipic>; 94 interrupt-parent = <&ipic>; 104 interrupt-parent = <&ipic>; 111 interrupt-parent = <&ipic>; 118 interrupt-parent = <&ipic>; 125 interrupt-parent = <&ipic>; 132 interrupt-parent = <&ipic>; 144 interrupt-parent = <&ipic>; 161 interrupt-parent = <&ipic>; [all …]`
D	redwood.dts	`49 UIC0: interrupt-controller0 { 51 interrupt-controller; 56 #interrupt-cells = <2>; 59 UIC1: interrupt-controller1 { 61 interrupt-controller; 66 #interrupt-cells = <2>; 68 interrupt-parent = <&UIC0>; 71 UIC2: interrupt-controller2 { 73 interrupt-controller; 78 #interrupt-cells = <2>; [all …]`
D	mpc8377_mds.dts	`58 interrupt-parent = <&ipic>; 146 interrupt-parent = <&ipic>; 153 interrupt-parent = <&ipic>; 161 interrupt-parent = <&ipic>; 175 interrupt-parent = <&ipic>; 184 interrupt-parent = <&ipic>; 193 interrupt-parent = <&ipic>; 212 interrupt-parent = <&ipic>; 225 interrupt-parent = <&ipic>; 231 interrupt-parent = <&ipic>; [all …]`
D	mpc8641_hpcn.dts	`70 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>; 143 interrupt-parent = <&mpic>; 159 interrupt-parent = <&mpic>; 167 interrupt-parent = <&mpic>; 175 interrupt-parent = <&mpic>; 183 interrupt-parent = <&mpic>; 199 interrupt-parent = <&mpic>; 211 interrupt-parent = <&mpic>; [all …]`
D	adder875-redboot.dts	`40 interrupts = <15 2>; // decrementer interrupt 41 interrupt-parent = <&PIC>; 104 interrupt-parent = <&PIC>; 116 interrupt-parent = <&PIC>; 121 PIC: interrupt-controller@0 { 122 interrupt-controller; 123 #interrupt-cells = <2>; 132 interrupts = <0>; // cpm error interrupt 133 interrupt-parent = <&CPM_PIC>; 156 CPM_PIC: interrupt-controller@930 { [all …]`
D	adder875-uboot.dts	`40 interrupts = <15 2>; // decrementer interrupt 41 interrupt-parent = <&PIC>; 103 interrupt-parent = <&PIC>; 115 interrupt-parent = <&PIC>; 120 PIC: interrupt-controller@0 { 121 interrupt-controller; 122 #interrupt-cells = <2>; 131 interrupts = <0>; // cpm error interrupt 132 interrupt-parent = <&CPM_PIC>; 155 CPM_PIC: interrupt-controller@930 { [all …]`
D	mpc8308_p1m.dts	`55 interrupt-parent = <&ipic>; 123 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>; 162 interrupt-parent = <&ipic>; 180 interrupt-parent = <&ipic>; 189 interrupt-parent = <&ipic>; 194 interrupt-parent = <&ipic>; 216 interrupt-parent = <&ipic>; 238 interrupt-parent = <&ipic>; 248 interrupt-parent = <&ipic>; [all …]`
D	bamboo.dts	`56 UIC0: interrupt-controller0 { 58 interrupt-controller; 63 #interrupt-cells = <2>; 66 UIC1: interrupt-controller1 { 68 interrupt-controller; 73 #interrupt-cells = <2>; 75 interrupt-parent = <&UIC0>; 110 interrupt-parent = <&MAL0>; 112 #interrupt-cells = <1>; 115 interrupt-map = </TXEOB/ 0x0 &UIC0 0xa 0x4 [all …]`
D	gef_sbc610.dts	`76 interrupt-parent = <&mpic>; 136 interrupt-parent = <&gef_pic>; 143 interrupt-parent = <&gef_pic>; 147 #interrupt-cells = <1>; 148 interrupt-controller; 153 interrupt-parent = <&mpic>; 167 #interrupt-cells = <2>; 183 interrupt-parent = <&mpic>; 192 interrupt-parent = <&mpic>; 222 interrupt-parent = <&mpic>; [all …]`
D	xpedite5200_xmon.dts	`73 interrupt-parent = <&mpic>; 79 interrupt-parent = <&mpic>; 88 interrupt-parent = <&mpic>; 100 interrupt-parent = <&mpic>; 156 interrupt-parent = <&mpic>; 172 interrupt-parent = <&mpic>; 180 interrupt-parent = <&mpic>; 188 interrupt-parent = <&mpic>; 196 interrupt-parent = <&mpic>; 213 interrupt-parent = <&mpic>; [all …]`
D	mpc8379_mds.dts	`56 interrupt-parent = <&ipic>; 144 interrupt-parent = <&ipic>; 151 interrupt-parent = <&ipic>; 159 interrupt-parent = <&ipic>; 173 interrupt-parent = <&ipic>; 182 interrupt-parent = <&ipic>; 192 interrupt-parent = <&ipic>; 199 interrupt-parent = <&ipic>; 206 interrupt-parent = <&ipic>; 213 interrupt-parent = <&ipic>; [all …]`
D	mpc7448hpc2.dts	`63 interrupt-parent = <&mpic>; 77 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>; 112 interrupt-parent = <&mpic>; 123 interrupt-parent = <&mpic>; 132 interrupt-parent = <&mpic>; 136 interrupt-controller; 138 #interrupt-cells = <2>; 146 #interrupt-cells = <1>; [all …]`
D	sam440ep.dts	`57 UIC0: interrupt-controller0 { 59 interrupt-controller; 64 #interrupt-cells = <2>; 67 UIC1: interrupt-controller1 { 69 interrupt-controller; 74 #interrupt-cells = <2>; 76 interrupt-parent = <&UIC0>; 111 interrupt-parent = <&MAL0>; 113 #interrupt-cells = <1>; 116 interrupt-map = </TXEOB/ 0 &UIC0 10 4 [all …]`
D	yosemite.dts	`54 UIC0: interrupt-controller0 { 56 interrupt-controller; 61 #interrupt-cells = <2>; 64 UIC1: interrupt-controller1 { 66 interrupt-controller; 71 #interrupt-cells = <2>; 73 interrupt-parent = <&UIC0>; 108 interrupt-parent = <&MAL0>; 110 #interrupt-cells = <1>; 113 interrupt-map = </TXEOB/ 0x0 &UIC0 0xa 0x4 [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/mips/
D	cpu_irq.txt	`1 MIPS CPU interrupt controller 7 platforms internal interrupt controller cascade. 13 - compatible : Should be "mti,cpu-interrupt-controller" 19 interrupt-controller; 20 #interrupt-cells = <1>; 22 compatible = "mti,cpu-interrupt-controller"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 32 interrupt-parent = <&cpu-irq>; 39 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },`
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
D	tc3589x.txt	18 - interrupt-parent : specifies which IRQ controller we're connected to 19 - interrupts : the interrupt on the parent the controller is connected to 20 - interrupt-controller : marks the device node as an interrupt controller 21 - #interrupt-cells : should be <1>, the first cell is the IRQ offset on this 22 TC3589x interrupt controller. 30 - interrupts : interrupt on the parent, which must be the tc3589x MFD device 31 - interrupt-controller : marks the device node as an interrupt controller 32 - #interrupt-cells : should be <2>, the first cell is the IRQ offset on this 33 TC3589x GPIO interrupt controller, the second cell is the interrupt flags 34 in accordance with <dt-bindings/interrupt-controller/irq.h>. The following [all …]
D	bfticu.txt	`9 - interrupt-controller: the bfticu FPGA is an interrupt controller 11 - #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant 12 of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 13 - interrupt-parent: the parent IRQ ctrl the main IRQ is connected to 20 interrupt-controller; 21 #interrupt-cells = <2>; 23 interrupt-parent = <&mpic>;`
D	qcom-pm8xxx.txt	`28 Definition: specifies the interrupt that indicates a subdevice 29 has generated an interrupt (summary interrupt). The 31 describing the node's interrupt parent. 33 - #interrupt-cells: 37 an interrupt source. The 1st cell contains the interrupt 46 - interrupt-controller: 49 Definition: identifies this node as an interrupt controller 74 Definition: single entry specifying the RTC's alarm interrupt 87 #interrupt-cells = <2>; 88 interrupt-controller;`
/linux-4.4.14/Documentation/virtual/kvm/devices/
D	xics.txt	1 XICS interrupt controller 7 Attributes: One per interrupt source, indexed by the source number. 10 Specification) defined in PAPR. The XICS has a set of interrupt 17 the interrupt server number (i.e. the vcpu number from the XICS's 26 * Pending interrupt priority, 8 bits 27 Zero is the highest priority, 255 means no interrupt is pending. 29 * Pending IPI (inter-processor interrupt) priority, 8 bits 32 * Pending interrupt source number, 24 bits 33 Zero means no interrupt pending, 2 means an IPI is pending 42 the interrupt source number. The 64 bit state word has the following [all …]
/linux-4.4.14/arch/arm64/boot/dts/xilinx/
D	zynqmp.dtsi	`67 interrupt-parent = <&gic>; 80 gic: interrupt-controller@f9010000 { 82 #interrupt-cells = <3>; 87 interrupt-controller; 88 interrupt-parent = <&gic>; 106 interrupt-parent = <&gic>; 118 interrupt-parent = <&gic>; 134 interrupt-parent = <&gic>; 142 interrupt-parent = <&gic>; 154 interrupt-parent = <&gic>; [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/usb/
D	spear-usb.txt	`9 - interrupt-parent: Should be the phandle for the interrupt controller 11 - interrupts: Should contain the EHCI interrupt 18 interrupt-parent = <&vic1>; 28 - interrupt-parent: Should be the phandle for the interrupt controller 30 - interrupts: Should contain the OHCI interrupt 37 interrupt-parent = <&vic1>;`
/linux-4.4.14/Documentation/devicetree/bindings/power_supply/
D	lp8727_charger.txt	`8 - interrupt-parent: interrupt controller node (see interrupt binding[0]) 9 - interrupts: interrupt specifier (see interrupt binding[0]) 10 - debounce-ms: interrupt debounce time. (u32) 17 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 25 /* GPIO 134 is used for LP8728 interrupt pin / 26 interrupt-parent = <&gpio5>; / base = 128 */`
/linux-4.4.14/Documentation/devicetree/bindings/sound/
D	omap-mcbsp.txt	`13 McBSP IP have more interrupt lines: 17 - interrupt-names: Array of strings associated with the interrupt numbers 18 - interrupt-parent: The parent interrupt controller 29 interrupts = <0 17 0x4>, /* OCP compliant interrupt / 30 <0 62 0x4>, / TX interrupt / 31 <0 63 0x4>, / RX interrupt */ 33 interrupt-names = "common", "tx", "rx", "sidetone"; 34 interrupt-parent = <&intc>;`
/linux-4.4.14/arch/powerpc/boot/dts/fsl/
D	mpc8541cds.dts	`72 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>; [all …]`
D	mpc8555cds.dts	`72 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>; 87 interrupt-parent = <&mpic>; 98 interrupt-parent = <&mpic>; 114 interrupt-parent = <&mpic>; 122 interrupt-parent = <&mpic>; 130 interrupt-parent = <&mpic>; 138 interrupt-parent = <&mpic>; 154 interrupt-parent = <&mpic>; 165 interrupt-parent = <&mpic>; [all …]`
/linux-4.4.14/Documentation/virtual/kvm/arm/
D	vgic-mapped-irqs.txt	13 interrupt at some point in time. When such an interrupt is raised, the 14 host OS initially handles the interrupt and must somehow signal this 15 event as a virtual interrupt to the guest. Another example could be a 18 and KVM must therefore somehow inject a virtual interrupt on behalf of 21 These virtual interrupts corresponding to a physical interrupt on the 33 with the virtual IRQ number and the state of the interrupt (Pending, 35 interrupt, the LR state moves from Pending to Active, and finally to 46 interrupt on the physical distributor when the guest deactivates the 47 corresponding virtual interrupt. 55 - The physical interrupt is acked by the host, and becomes active on [all …]
/linux-4.4.14/arch/c6x/boot/dts/
D	evmc6678.dts	`35 megamod_pic: interrupt-controller@1800000 { 40 interrupt-parent = <&megamod_pic>; 45 interrupt-parent = <&megamod_pic>; 50 interrupt-parent = <&megamod_pic>; 55 interrupt-parent = <&megamod_pic>; 60 interrupt-parent = <&megamod_pic>; 65 interrupt-parent = <&megamod_pic>; 70 interrupt-parent = <&megamod_pic>; 75 interrupt-parent = <&megamod_pic>;`
/linux-4.4.14/arch/arm64/boot/dts/marvell/
D	berlin4ct.dtsi	`45 #include <dt-bindings/interrupt-controller/arm-gic.h> 49 interrupt-parent = <&gic>; 107 interrupt-affinity = <&cpu0>, 127 gic: interrupt-controller@901000 { 129 #interrupt-cells = <3>; 130 interrupt-controller; 144 interrupt-parent = <&aic>; 158 interrupt-controller; 159 #interrupt-cells = <2>; 176 interrupt-controller; [all …]`
/linux-4.4.14/arch/mips/boot/dts/qca/
D	ar9132.dtsi	`18 cpuintc: interrupt-controller { 21 interrupt-controller; 22 #interrupt-cells = <1>; 36 interrupt-parent = <&cpuintc>; 45 interrupt-parent = <&miscintc>; 81 interrupt-controller; 82 #interrupt-cells = <2>; 107 miscintc: interrupt-controller@18060010 { 112 interrupt-parent = <&cpuintc>; 115 interrupt-controller; [all …]`
/linux-4.4.14/Documentation/devicetree/bindings/spi/
D	spi-rspi.txt	`19 - interrupts : A list of interrupt-specifiers, one for each entry in 20 interrupt-names. 21 If interrupt-names is not present, an interrupt specifier 22 for a single muxed interrupt. 23 - interrupt-names : A list of interrupt names. Should contain (if present): 27 - "mux" for a single muxed interrupt. 28 - interrupt-parent : The phandle for the interrupt controller that 51 interrupt-names = "error", "rx", "tx"; 52 interrupt-parent = <&gic>; 61 interrupt-parent = <&gic>;`
/linux-4.4.14/arch/mips/boot/dts/ralink/
D	rt3050.dtsi	`14 #interrupt-cells = <1>; 15 interrupt-controller; 16 compatible = "mti,cpu-interrupt-controller"; 36 interrupt-controller; 37 #interrupt-cells = <1>; 39 interrupt-parent = <&cpuintc>; 52 interrupt-parent = <&intc>; 63 interrupt-parent = <&intc>;`
D	rt2880.dtsi	`14 #interrupt-cells = <1>; 15 interrupt-controller; 16 compatible = "mti,cpu-interrupt-controller"; 36 interrupt-controller; 37 #interrupt-cells = <1>; 39 interrupt-parent = <&cpuintc>; 52 interrupt-parent = <&intc>;`
D	mt7620a.dtsi	`14 #interrupt-cells = <1>; 15 interrupt-controller; 16 compatible = "mti,cpu-interrupt-controller"; 36 interrupt-controller; 37 #interrupt-cells = <1>; 39 interrupt-parent = <&cpuintc>; 52 interrupt-parent = <&intc>;`
D	rt3883.dtsi	`14 #interrupt-cells = <1>; 15 interrupt-controller; 16 compatible = "mti,cpu-interrupt-controller"; 36 interrupt-controller; 37 #interrupt-cells = <1>; 39 interrupt-parent = <&cpuintc>; 52 interrupt-parent = <&intc>;`
/linux-4.4.14/Documentation/devicetree/bindings/net/
D	amd-xgbe.txt	11 - interrupt-parent: Should be the phandle for the interrupt controller 13 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt 14 listed is required and is the general device interrupt. If the optional 15 amd,per-channel-interrupt property is specified, then one additional 16 interrupt for each DMA channel supported by the device should be specified. 17 The last interrupt listed should be the PCS auto-negotiation interrupt. 20 correct Rx interrupt watchdog timer value on a DMA channel 32 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate 33 a unique interrupt for each DMA channel - this requires an additional 34 interrupt be configured for each DMA channel [all …]
/linux-4.4.14/Documentation/devicetree/bindings/input/
D	cypress,cyapa.txt	`6 - interrupt-parent: a phandle for the interrupt controller (see interrupt 8 - interrupts: interrupt to which the chip is connected (see interrupt 18 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 29 interrupt-parent = <&gpio>; 38 interrupt-parent = <&gpio>;`
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
D	pinctrl-st.txt	14 GPIO bank can have one of the two possible types of interrupt-wirings. 16 First type is via irqmux, single interrupt is used by multiple gpio banks. This 26 Second type has a dedicated interrupt per gpio bank. 44 - interrupts : Interrupt number of the irqmux. If the interrupt is shared 59 interrupt wired up for this gpio bank. 61 - interrupt-controller : Indicates this device is a interrupt controller. GPIO 62 bank can be an interrupt controller iff one of the interrupt type either via 63 irqmux or a dedicated interrupt per bank is specified. 65 - #interrupt-cells: the value of this property should be 2. 66 - First Cell: represents the external gpio interrupt number local to the [all …]
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/nintendo/
D	wii.txt	32 - interrupts : should contain the VI interrupt 44 1.b.i) The "Flipper" interrupt controller node 46 Represents the "Flipper" interrupt controller within the "Hollywood" chip. 47 The node for the "Flipper" interrupt controller must be placed under 52 - #interrupt-cells : <1> 54 - interrupt-controller 65 - interrupts : should contain the DSP interrupt 77 - interrupts : should contain the SI interrupt 88 - interrupts : should contain the AI interrupt 98 - interrupts : should contain the EXI interrupt [all …]
/linux-4.4.14/Documentation/devicetree/bindings/serial/
D	qca,ar9330-uart.txt	`10 - interrupt-parent: The phandle for the interrupt controller that 13 - interrupts: Specifies the interrupt source of the parent interrupt 14 controller. The format of the interrupt specifier depends on the 15 parent interrupt controller. 32 interrupt-parent = <&intc>;`
/linux-4.4.14/Documentation/devicetree/bindings/mips/cavium/
D	cib.txt	`8 - interrupt-controller: This is an interrupt controller. 16 - interrupt-parent: Always the CIU on the SoC. 20 - #interrupt-cells: Must be <2>. The first cell is the bit within the 26 interrupt-controller@107000000e000 { 32 interrupt-controller; 33 interrupt-parent = <&ciu>; 42 #interrupt-cells = <2>;`

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