Lines Matching refs:interrupt

1 XICS interrupt controller
7   Attributes: One per interrupt source, indexed by the source number.
10 Specification) defined in PAPR.  The XICS has a set of interrupt
17 the interrupt server number (i.e. the vcpu number from the XICS's
26 * Pending interrupt priority, 8 bits
27   Zero is the highest priority, 255 means no interrupt is pending.
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
32 * Pending interrupt source number, 24 bits
33   Zero means no interrupt pending, 2 means an IPI is pending
42 the interrupt source number.  The 64 bit state word has the following
46   This specifies where the interrupt should be sent, and is the
47   interrupt server number specified for the destination vcpu.
50   This is the priority specified for this interrupt source, where 0 is
51   the highest priority and 255 is the lowest.  An interrupt with a
55   This bit is 1 for a level-sensitive interrupt source, or 0 for
59   This bit is set to 1 if the interrupt is masked (cannot be delivered
64   This bit is 1 if the source has a pending interrupt, otherwise 0.