Lines Matching refs:interrupt

8 Secondary GICs are cascaded into the upward interrupt controller and do not
24 - interrupt-controller : Identifies the node as an interrupt controller
25 - #interrupt-cells : Specifies the number of cells needed to encode an
26   interrupt source.  The type shall be a <u32> and the value shall be 3.
28   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
31   The 2nd cell contains the interrupt number for the interrupt type.
41 	bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
43 	the interrupt is wired to that CPU.  Only valid for PPI interrupts.
54 - interrupts	: Interrupt source of the parent interrupt controller on
55   secondary GICs, or VGIC maintenance interrupt on primary GIC (see
79 	intc: interrupt-controller@fff11000 {
81 		#interrupt-cells = <3>;
83 		interrupt-controller;
93 primary interrupt controller).
102 - interrupts : VGIC maintenance interrupt.
106 	interrupt-controller@2c001000 {
108 		#interrupt-cells = <3>;
109 		interrupt-controller;
143 	interrupt-controller@e1101000 {
145 		#interrupt-cells = <3>;
148 		interrupt-controller;