1/*
2 * MPC8377E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "fsl,mpc8377emds";
16	compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26		pci1 = &pci1;
27		pci2 = &pci2;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		PowerPC,8377@0 {
35			device_type = "cpu";
36			reg = <0x0>;
37			d-cache-line-size = <32>;
38			i-cache-line-size = <32>;
39			d-cache-size = <32768>;
40			i-cache-size = <32768>;
41			timebase-frequency = <0>;
42			bus-frequency = <0>;
43			clock-frequency = <0>;
44		};
45	};
46
47	memory {
48		device_type = "memory";
49		reg = <0x00000000 0x20000000>;	// 512MB at 0
50	};
51
52	localbus@e0005000 {
53		#address-cells = <2>;
54		#size-cells = <1>;
55		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56		reg = <0xe0005000 0x1000>;
57		interrupts = <77 0x8>;
58		interrupt-parent = <&ipic>;
59
60		// booting from NOR flash
61		ranges = <0 0x0 0xfe000000 0x02000000
62		          1 0x0 0xf8000000 0x00008000
63		          3 0x0 0xe0600000 0x00008000>;
64
65		flash@0,0 {
66			#address-cells = <1>;
67			#size-cells = <1>;
68			compatible = "cfi-flash";
69			reg = <0 0x0 0x2000000>;
70			bank-width = <2>;
71			device-width = <1>;
72
73			u-boot@0 {
74				reg = <0x0 0x100000>;
75				read-only;
76			};
77
78			fs@100000 {
79				reg = <0x100000 0x800000>;
80			};
81
82			kernel@1d00000 {
83				reg = <0x1d00000 0x200000>;
84			};
85
86			dtb@1f00000 {
87				reg = <0x1f00000 0x100000>;
88			};
89		};
90
91		bcsr@1,0 {
92			reg = <1 0x0 0x8000>;
93			compatible = "fsl,mpc837xmds-bcsr";
94		};
95
96		nand@3,0 {
97			#address-cells = <1>;
98			#size-cells = <1>;
99			compatible = "fsl,mpc8377-fcm-nand",
100			             "fsl,elbc-fcm-nand";
101			reg = <3 0x0 0x8000>;
102
103			u-boot@0 {
104				reg = <0x0 0x100000>;
105				read-only;
106			};
107
108			kernel@100000 {
109				reg = <0x100000 0x300000>;
110			};
111
112			fs@400000 {
113				reg = <0x400000 0x1c00000>;
114			};
115		};
116	};
117
118	soc@e0000000 {
119		#address-cells = <1>;
120		#size-cells = <1>;
121		device_type = "soc";
122		compatible = "simple-bus";
123		ranges = <0x0 0xe0000000 0x00100000>;
124		reg = <0xe0000000 0x00000200>;
125		bus-frequency = <0>;
126
127		wdt@200 {
128			compatible = "mpc83xx_wdt";
129			reg = <0x200 0x100>;
130		};
131
132		sleep-nexus {
133			#address-cells = <1>;
134			#size-cells = <1>;
135			compatible = "simple-bus";
136			sleep = <&pmc 0x0c000000>;
137			ranges;
138
139			i2c@3000 {
140				#address-cells = <1>;
141				#size-cells = <0>;
142				cell-index = <0>;
143				compatible = "fsl-i2c";
144				reg = <0x3000 0x100>;
145				interrupts = <14 0x8>;
146				interrupt-parent = <&ipic>;
147				dfsrr;
148
149				rtc@68 {
150					compatible = "dallas,ds1374";
151					reg = <0x68>;
152					interrupts = <19 0x8>;
153					interrupt-parent = <&ipic>;
154				};
155			};
156
157			sdhci@2e000 {
158				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
159				reg = <0x2e000 0x1000>;
160				interrupts = <42 0x8>;
161				interrupt-parent = <&ipic>;
162				sdhci,wp-inverted;
163				/* Filled in by U-Boot */
164				clock-frequency = <0>;
165			};
166		};
167
168		i2c@3100 {
169			#address-cells = <1>;
170			#size-cells = <0>;
171			cell-index = <1>;
172			compatible = "fsl-i2c";
173			reg = <0x3100 0x100>;
174			interrupts = <15 0x8>;
175			interrupt-parent = <&ipic>;
176			dfsrr;
177		};
178
179		spi@7000 {
180			cell-index = <0>;
181			compatible = "fsl,spi";
182			reg = <0x7000 0x1000>;
183			interrupts = <16 0x8>;
184			interrupt-parent = <&ipic>;
185			mode = "cpu";
186		};
187
188		usb@23000 {
189			compatible = "fsl-usb2-dr";
190			reg = <0x23000 0x1000>;
191			#address-cells = <1>;
192			#size-cells = <0>;
193			interrupt-parent = <&ipic>;
194			interrupts = <38 0x8>;
195			dr_mode = "host";
196			phy_type = "ulpi";
197			sleep = <&pmc 0x00c00000>;
198		};
199
200		enet0: ethernet@24000 {
201			#address-cells = <1>;
202			#size-cells = <1>;
203			cell-index = <0>;
204			device_type = "network";
205			model = "eTSEC";
206			compatible = "gianfar";
207			reg = <0x24000 0x1000>;
208			ranges = <0x0 0x24000 0x1000>;
209			local-mac-address = [ 00 00 00 00 00 00 ];
210			interrupts = <32 0x8 33 0x8 34 0x8>;
211			phy-connection-type = "mii";
212			interrupt-parent = <&ipic>;
213			tbi-handle = <&tbi0>;
214			phy-handle = <&phy2>;
215			sleep = <&pmc 0xc0000000>;
216			fsl,magic-packet;
217
218			mdio@520 {
219				#address-cells = <1>;
220				#size-cells = <0>;
221				compatible = "fsl,gianfar-mdio";
222				reg = <0x520 0x20>;
223
224				phy2: ethernet-phy@2 {
225					interrupt-parent = <&ipic>;
226					interrupts = <17 0x8>;
227					reg = <0x2>;
228				};
229
230				phy3: ethernet-phy@3 {
231					interrupt-parent = <&ipic>;
232					interrupts = <18 0x8>;
233					reg = <0x3>;
234				};
235
236				tbi0: tbi-phy@11 {
237					reg = <0x11>;
238					device_type = "tbi-phy";
239				};
240			};
241		};
242
243		enet1: ethernet@25000 {
244			#address-cells = <1>;
245			#size-cells = <1>;
246			cell-index = <1>;
247			device_type = "network";
248			model = "eTSEC";
249			compatible = "gianfar";
250			reg = <0x25000 0x1000>;
251			ranges = <0x0 0x25000 0x1000>;
252			local-mac-address = [ 00 00 00 00 00 00 ];
253			interrupts = <35 0x8 36 0x8 37 0x8>;
254			phy-connection-type = "mii";
255			interrupt-parent = <&ipic>;
256			tbi-handle = <&tbi1>;
257			phy-handle = <&phy3>;
258			sleep = <&pmc 0x30000000>;
259			fsl,magic-packet;
260
261			mdio@520 {
262				#address-cells = <1>;
263				#size-cells = <0>;
264				compatible = "fsl,gianfar-tbi";
265				reg = <0x520 0x20>;
266
267				tbi1: tbi-phy@11 {
268					reg = <0x11>;
269					device_type = "tbi-phy";
270				};
271			};
272		};
273
274		serial0: serial@4500 {
275			cell-index = <0>;
276			device_type = "serial";
277			compatible = "fsl,ns16550", "ns16550";
278			reg = <0x4500 0x100>;
279			clock-frequency = <0>;
280			interrupts = <9 0x8>;
281			interrupt-parent = <&ipic>;
282		};
283
284		serial1: serial@4600 {
285			cell-index = <1>;
286			device_type = "serial";
287			compatible = "fsl,ns16550", "ns16550";
288			reg = <0x4600 0x100>;
289			clock-frequency = <0>;
290			interrupts = <10 0x8>;
291			interrupt-parent = <&ipic>;
292		};
293
294		dma@82a8 {
295			#address-cells = <1>;
296			#size-cells = <1>;
297			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
298			reg = <0x82a8 4>;
299			ranges = <0 0x8100 0x1a8>;
300			interrupt-parent = <&ipic>;
301			interrupts = <0x47 8>;
302			cell-index = <0>;
303			dma-channel@0 {
304				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
305				reg = <0 0x80>;
306				cell-index = <0>;
307				interrupt-parent = <&ipic>;
308				interrupts = <0x47 8>;
309			};
310			dma-channel@80 {
311				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
312				reg = <0x80 0x80>;
313				cell-index = <1>;
314				interrupt-parent = <&ipic>;
315				interrupts = <0x47 8>;
316			};
317			dma-channel@100 {
318				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
319				reg = <0x100 0x80>;
320				cell-index = <2>;
321				interrupt-parent = <&ipic>;
322				interrupts = <0x47 8>;
323			};
324			dma-channel@180 {
325				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
326				reg = <0x180 0x28>;
327				cell-index = <3>;
328				interrupt-parent = <&ipic>;
329				interrupts = <0x47 8>;
330			};
331		};
332
333		crypto@30000 {
334			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335				     "fsl,sec2.1", "fsl,sec2.0";
336			reg = <0x30000 0x10000>;
337			interrupts = <11 0x8>;
338			interrupt-parent = <&ipic>;
339			fsl,num-channels = <4>;
340			fsl,channel-fifo-len = <24>;
341			fsl,exec-units-mask = <0x9fe>;
342			fsl,descriptor-types-mask = <0x3ab0ebf>;
343			sleep = <&pmc 0x03000000>;
344		};
345
346		sata@18000 {
347			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
348			reg = <0x18000 0x1000>;
349			interrupts = <44 0x8>;
350			interrupt-parent = <&ipic>;
351			sleep = <&pmc 0x000000c0>;
352		};
353
354		sata@19000 {
355			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
356			reg = <0x19000 0x1000>;
357			interrupts = <45 0x8>;
358			interrupt-parent = <&ipic>;
359			sleep = <&pmc 0x00000030>;
360		};
361
362		/* IPIC
363		 * interrupts cell = <intr #, sense>
364		 * sense values match linux IORESOURCE_IRQ_* defines:
365		 * sense == 8: Level, low assertion
366		 * sense == 2: Edge, high-to-low change
367		 */
368		ipic: pic@700 {
369			compatible = "fsl,ipic";
370			interrupt-controller;
371			#address-cells = <0>;
372			#interrupt-cells = <2>;
373			reg = <0x700 0x100>;
374		};
375
376		pmc: power@b00 {
377			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
378			reg = <0xb00 0x100 0xa00 0x100>;
379			interrupts = <80 0x8>;
380			interrupt-parent = <&ipic>;
381		};
382	};
383
384	pci0: pci@e0008500 {
385		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
386		interrupt-map = <
387
388				/* IDSEL 0x11 */
389				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
390				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
391				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
392				 0x8800 0x0 0x0 0x4 &ipic 23 0x8
393
394				/* IDSEL 0x12 */
395				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
396				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
397				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
398				 0x9000 0x0 0x0 0x4 &ipic 21 0x8
399
400				/* IDSEL 0x13 */
401				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
402				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
403				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
404				 0x9800 0x0 0x0 0x4 &ipic 22 0x8
405
406				/* IDSEL 0x15 */
407				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
408				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
409				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
410				 0xa800 0x0 0x0 0x4 &ipic 23 0x8
411
412				/* IDSEL 0x16 */
413				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
414				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
415				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
416				 0xb000 0x0 0x0 0x4 &ipic 22 0x8
417
418				/* IDSEL 0x17 */
419				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
420				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
421				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
422				 0xb800 0x0 0x0 0x4 &ipic 21 0x8
423
424				/* IDSEL 0x18 */
425				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
426				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
427				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
428				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
429		interrupt-parent = <&ipic>;
430		interrupts = <66 0x8>;
431		bus-range = <0x0 0x0>;
432		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
433		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
434		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
435		sleep = <&pmc 0x00010000>;
436		clock-frequency = <0>;
437		#interrupt-cells = <1>;
438		#size-cells = <2>;
439		#address-cells = <3>;
440		reg = <0xe0008500 0x100		/* internal registers */
441		       0xe0008300 0x8>;		/* config space access registers */
442		compatible = "fsl,mpc8349-pci";
443		device_type = "pci";
444	};
445
446	pci1: pcie@e0009000 {
447		#address-cells = <3>;
448		#size-cells = <2>;
449		#interrupt-cells = <1>;
450		device_type = "pci";
451		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
452		reg = <0xe0009000 0x00001000>;
453		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
454		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
455		bus-range = <0 255>;
456		interrupt-map-mask = <0xf800 0 0 7>;
457		interrupt-map = <0 0 0 1 &ipic 1 8
458				 0 0 0 2 &ipic 1 8
459				 0 0 0 3 &ipic 1 8
460				 0 0 0 4 &ipic 1 8>;
461		sleep = <&pmc 0x00300000>;
462		clock-frequency = <0>;
463
464		pcie@0 {
465			#address-cells = <3>;
466			#size-cells = <2>;
467			device_type = "pci";
468			reg = <0 0 0 0 0>;
469			ranges = <0x02000000 0 0xa8000000
470				  0x02000000 0 0xa8000000
471				  0 0x10000000
472				  0x01000000 0 0x00000000
473				  0x01000000 0 0x00000000
474				  0 0x00800000>;
475		};
476	};
477
478	pci2: pcie@e000a000 {
479		#address-cells = <3>;
480		#size-cells = <2>;
481		#interrupt-cells = <1>;
482		device_type = "pci";
483		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
484		reg = <0xe000a000 0x00001000>;
485		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
486			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
487		bus-range = <0 255>;
488		interrupt-map-mask = <0xf800 0 0 7>;
489		interrupt-map = <0 0 0 1 &ipic 2 8
490				 0 0 0 2 &ipic 2 8
491				 0 0 0 3 &ipic 2 8
492				 0 0 0 4 &ipic 2 8>;
493		sleep = <&pmc 0x000c0000>;
494		clock-frequency = <0>;
495
496		pcie@0 {
497			#address-cells = <3>;
498			#size-cells = <2>;
499			device_type = "pci";
500			reg = <0 0 0 0 0>;
501			ranges = <0x02000000 0 0xc8000000
502				  0x02000000 0 0xc8000000
503				  0 0x10000000
504				  0x01000000 0 0x00000000
505				  0x01000000 0 0x00000000
506				  0 0x00800000>;
507		};
508	};
509};
510