Lines Matching refs:interrupt

1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
4 interrupt.
10 - interrupt-parent: phandle of the parent interrupt controller.
11 - interrupts: Interrupt specifier for the controllers interrupt.
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
24 	interrupt-controller@18060010 {
28 		interrupt-parent = <&cpuintc>;
31 		interrupt-controller;
32 		#interrupt-cells = <1>;
37 	interrupt-controller@18060010 {
41 		interrupt-parent = <&cpuintc>;
44 		interrupt-controller;
45 		#interrupt-cells = <1>;