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Searched refs:dpll (Results 1 – 48 of 48) sorted by relevance

/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
[all …]
Dapll.txt14 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
/linux-4.4.14/drivers/gpu/drm/gma500/
Dpsb_intel_display.c116 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
165 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
166 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
172 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
173 dpll |= in psb_intel_crtc_mode_set()
178 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
Dmdfld_intel_display.c275 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
282 REG_READ(map->dpll); in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
331 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
338 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
344 REG_READ(map->dpll); in mdfld_crtc_dpms()
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
349 REG_READ(map->dpll); in mdfld_crtc_dpms()
[all …]
Doaktrail_crtc.c250 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
252 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
261 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
263 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
322 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
324 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
326 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
[all …]
Dmdfld_device.c197 pipe->dpll = PSB_RVDC32(map->dpll); in mdfld_save_display_registers()
251 u32 dpll; in mdfld_restore_display_registers() local
258 u32 dpll_val = pipe->dpll; in mdfld_restore_display_registers()
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll); in mdfld_restore_display_registers()
284 PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
289 dpll = PSB_RVDC32(map->dpll); in mdfld_restore_display_registers()
291 if (!(dpll & DPLL_VCO_ENABLE)) { in mdfld_restore_display_registers()
295 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_restore_display_registers()
296 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_restore_display_registers()
297 PSB_WVDC32(dpll, map->dpll); in mdfld_restore_display_registers()
[all …]
Dcdv_intel_display.c591 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
673 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= 3; in cdv_intel_crtc_mode_set()
690 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
737 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
772 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
781 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
783 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
[all …]
Dgma_display.c226 temp = REG_READ(map->dpll); in gma_crtc_dpms()
228 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
229 REG_READ(map->dpll); in gma_crtc_dpms()
232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_READ(map->dpll); in gma_crtc_dpms()
236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
237 REG_READ(map->dpll); in gma_crtc_dpms()
312 temp = REG_READ(map->dpll); in gma_crtc_dpms()
314 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
315 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
Doaktrail_hdmi.c281 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
291 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
292 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
307 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
308 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
309 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
313 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
Doaktrail_device.c212 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers()
329 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers()
470 .dpll = MRST_DPLL_A,
494 .dpll = DPLL_B,
Dpsb_device.c269 .dpll = DPLL_A,
293 .dpll = DPLL_B,
Dcdv_device.c531 .dpll = DPLL_A,
556 .dpll = DPLL_B,
Dpsb_drv.h283 u32 dpll; member
317 u32 dpll; member
Dmdfld_dsi_pkg_sender.c625 pkg_sender->dpll_reg = map->dpll; in mdfld_dsi_pkg_sender_init()
/linux-4.4.14/drivers/clk/ti/
Ddpll.c200 struct ti_clk_dpll *dpll; in ti_clk_register_dpll() local
205 dpll = setup->data; in ti_clk_register_dpll()
207 if (dpll->num_parents < 2) in ti_clk_register_dpll()
210 clk_ref = clk_get_sys(NULL, dpll->parents[0]); in ti_clk_register_dpll()
211 clk_bypass = clk_get_sys(NULL, dpll->parents[1]); in ti_clk_register_dpll()
231 init.num_parents = dpll->num_parents; in ti_clk_register_dpll()
232 init.parent_names = dpll->parents; in ti_clk_register_dpll()
234 dd->control_reg = _get_reg(dpll->module, dpll->control_reg); in ti_clk_register_dpll()
235 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg); in ti_clk_register_dpll()
236 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg); in ti_clk_register_dpll()
[all …]
DMakefile2 clk-common = dpll.o composite.o divider.o gate.o \
/linux-4.4.14/arch/arm/mach-omap1/
Dsram.S39 strh r0, [r2] @ set dpll into bypass mode
44 strh r0, [r2] @ write new dpll value
52 lock: ldrh r4, [r2], #0 @ read back dpll value
55 tst r4, #1 << 0 @ dpll rate locked?
/linux-4.4.14/drivers/ata/
Dpata_hpt3x2n.c316 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
323 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
332 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
334 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
336 flags |= dpll; in hpt3x2n_qc_issue()
339 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
Dpata_hpt37x.c982 int dpll, adjust; in hpt37x_init_one() local
985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1015 if (dpll == 3) in hpt37x_init_one()
1021 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ddi.c976 uint32_t dpll) in skl_calc_wrpll_link() argument
982 cfgcr1_reg = DPLL_CFGCR1(dpll); in skl_calc_wrpll_link()
983 cfgcr2_reg = DPLL_CFGCR2(dpll); in skl_calc_wrpll_link()
1061 uint32_t dpll_ctl1, dpll; in skl_ddi_clock_get() local
1063 dpll = pipe_config->ddi_pll_sel; in skl_ddi_clock_get()
1067 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { in skl_ddi_clock_get()
1068 link_clock = skl_calc_wrpll_link(dev_priv, dpll); in skl_ddi_clock_get()
1070 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); in skl_ddi_clock_get()
1071 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); in skl_ddi_clock_get()
1152 enum intel_dpll_id dpll) in bxt_calc_pll_link() argument
[all …]
Dintel_display.c657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
1604 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll() local
1615 I915_WRITE(reg, dpll); in vlv_enable_pll()
1626 I915_WRITE(reg, dpll); in vlv_enable_pll()
1629 I915_WRITE(reg, dpll); in vlv_enable_pll()
1632 I915_WRITE(reg, dpll); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1693 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll() local
1712 dpll |= DPLL_DVO_2X_MODE; in i9xx_enable_pll()
[all …]
Dintel_dvo.c456 uint32_t dpll[I915_MAX_PIPES]; in intel_dvo_init() local
488 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
489 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
496 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_drv.h235 typedef struct dpll { struct
408 struct dpll dpll; member
1121 const struct dpll *dpll);
Di915_drv.h366 uint32_t dpll; member
611 struct dpll;
632 struct dpll *match_clock,
633 struct dpll *best_clock);
Dintel_dp.c52 struct dpll dpll; member
344 &chv_dpll[0].dpll : &vlv_dpll[0].dpll); in vlv_power_sequencer_kick()
1250 pipe_config->dpll = divisor[i].dpll; in intel_dp_set_clock()
Dintel_dsi.c489 intel_crtc->config->dpll_hw_state.dpll = in intel_dsi_pre_enable()
Dintel_sdvo.c1105 struct dpll *clock = &pipe_config->dpll; in i9xx_adjust_sdvo_tv_clock()
Di915_debugfs.c3087 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); in i915_shared_dplls_info()
/linux-4.4.14/drivers/video/fbdev/intelfb/
Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1048 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1063 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1075 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Dam43xx-clocks.dtsi200 compatible = "ti,am3-dpll-core-clock";
207 compatible = "ti,am3-dpll-x2-clock";
246 compatible = "ti,am3-dpll-clock";
272 compatible = "ti,am3-dpll-clock";
290 compatible = "ti,am3-dpll-clock";
309 compatible = "ti,am3-dpll-j-type-clock";
601 compatible = "ti,am3-dpll-clock";
678 compatible = "ti,am3-dpll-x2-clock";
Dam33xx-clocks.dtsi168 compatible = "ti,am3-dpll-core-clock";
175 compatible = "ti,am3-dpll-x2-clock";
208 compatible = "ti,am3-dpll-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
Domap54xx-clocks.dtsi107 compatible = "ti,omap4-dpll-m4xen-clock";
114 compatible = "ti,omap4-dpll-x2-clock";
180 compatible = "ti,omap4-dpll-core-clock";
187 compatible = "ti,omap4-dpll-x2-clock";
315 compatible = "ti,omap4-dpll-clock";
322 compatible = "ti,omap4-dpll-x2-clock";
354 compatible = "ti,omap5-mpu-dpll-clock";
629 compatible = "ti,omap4-dpll-clock";
636 compatible = "ti,omap4-dpll-x2-clock";
696 compatible = "ti,omap4-dpll-clock";
[all …]
Ddra7xx-clocks.dtsi193 compatible = "ti,omap4-dpll-m4xen-clock";
200 compatible = "ti,omap4-dpll-x2-clock";
256 compatible = "ti,omap4-dpll-core-clock";
263 compatible = "ti,omap4-dpll-x2-clock";
288 compatible = "ti,omap5-mpu-dpll-clock";
330 compatible = "ti,omap4-dpll-clock";
364 compatible = "ti,omap4-dpll-clock";
398 compatible = "ti,omap4-dpll-clock";
443 compatible = "ti,omap4-dpll-clock";
469 compatible = "ti,omap4-dpll-clock";
[all …]
Domap44xx-clocks.dtsi137 compatible = "ti,omap4-dpll-m4xen-clock";
144 compatible = "ti,omap4-dpll-x2-clock";
207 compatible = "ti,omap4-dpll-core-clock";
214 compatible = "ti,omap4-dpll-x2-clock";
357 compatible = "ti,omap4-dpll-clock";
364 compatible = "ti,omap4-dpll-x2-clock";
392 compatible = "ti,omap4-dpll-clock";
765 compatible = "ti,omap4-dpll-clock";
781 compatible = "ti,omap4-dpll-x2-clock";
866 compatible = "ti,omap4-dpll-j-type-clock";
Domap36xx-clocks.dtsi13 compatible = "ti,omap3-dpll-per-j-type-clock";
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi30 compatible = "ti,omap3-dpll-clock";
Domap34xx-omap36xx-clocks.dtsi168 compatible = "ti,omap3-dpll-clock";
Domap3xxx-clocks.dtsi198 compatible = "ti,omap3-dpll-per-clock";
239 compatible = "ti,omap3-dpll-core-clock";
321 compatible = "ti,omap3-dpll-clock";
Domap24xx-clocks.dtsi126 compatible = "ti,omap2-dpll-core-clock";
/linux-4.4.14/Documentation/devicetree/bindings/phy/
Dti-phy.txt74 * "dpll_ref" - external dpll ref clk
75 * "dpll_ref_m2" - external dpll ref clk
/linux-4.4.14/arch/arm/mach-omap2/
Dsram242x.S268 str r0, [r4] @ set dpll ctrl val
281 beq pend @ jump over dpll relock
286 orr r8, r7, #0x3 @ val for lock dpll
Dsram243x.S268 str r0, [r4] @ set dpll ctrl val
281 beq pend @ jump over dpll relock
286 orr r8, r7, #0x3 @ val for lock dpll
/linux-4.4.14/drivers/ide/
Dhpt366.c853 u32 dpll = (f_high << 16) | f_low | 0x100; in hpt37x_calibrate_dpll() local
857 pci_write_config_dword(dev, 0x5c, dpll); in hpt37x_calibrate_dpll()
874 pci_read_config_dword (dev, 0x5c, &dpll); in hpt37x_calibrate_dpll()
875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); in hpt37x_calibrate_dpll()
/linux-4.4.14/drivers/clk/rockchip/
Dclk-rk3188.c27 apll, cpll, dpll, gpll, enumerator
217 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
228 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
Dclk-rk3368.c25 apllb, aplll, dpll, cpll, gpll, npll, enumerator
142 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
Dclk-rk3288.c27 apll, dpll, cpll, gpll, npll, enumerator
206 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
/linux-4.4.14/Documentation/networking/
Dz8530drv.txt212 cards. Use "mode dpll" for clock source (see below).
251 clock dpll # clock source:
252 # dpll = normal half duplex operation
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5420.c146 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1229 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,