250 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
252 				REG_WRITE_WITH_AUX(map->dpll, temp, i);  in oaktrail_crtc_dpms()
253 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
256 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
258 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
261 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
263 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
322 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
324 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
326 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
378 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in oaktrail_crtc_mode_set()  local
507 	dpll = 0;		/*BIT16 = 0 for 100MHz reference */  in oaktrail_crtc_mode_set()
531 	dpll |= DPLL_VGA_MODE_DIS;  in oaktrail_crtc_mode_set()
534 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
537 		dpll |= DPLLA_MODE_LVDS;  in oaktrail_crtc_mode_set()
539 		dpll |= DPLLB_MODE_DAC_SERIAL;  in oaktrail_crtc_mode_set()
545 		dpll |= DPLL_DVO_HIGH_SPEED;  in oaktrail_crtc_mode_set()
546 		dpll |=  in oaktrail_crtc_mode_set()
554 		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;  in oaktrail_crtc_mode_set()
556 		dpll |= (1 << (clock.p1 - 2)) << 17;  in oaktrail_crtc_mode_set()
558 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
560 	if (dpll & DPLL_VCO_ENABLE) {  in oaktrail_crtc_mode_set()
563 			REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);  in oaktrail_crtc_mode_set()
564 			REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
572 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
573 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
578 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
579 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()