976 			       uint32_t dpll)  in skl_calc_wrpll_link()  argument
982 	cfgcr1_reg = DPLL_CFGCR1(dpll);  in skl_calc_wrpll_link()
983 	cfgcr2_reg = DPLL_CFGCR2(dpll);  in skl_calc_wrpll_link()
1061 	uint32_t dpll_ctl1, dpll;  in skl_ddi_clock_get()  local
1063 	dpll = pipe_config->ddi_pll_sel;  in skl_ddi_clock_get()
1067 	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {  in skl_ddi_clock_get()
1068 		link_clock = skl_calc_wrpll_link(dev_priv, dpll);  in skl_ddi_clock_get()
1070 		link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);  in skl_ddi_clock_get()
1071 		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);  in skl_ddi_clock_get()
1152 				enum intel_dpll_id dpll)  in bxt_calc_pll_link()  argument
1159 	if (WARN_ON(dpll == DPLL_ID_PRIVATE))  in bxt_calc_pll_link()
1162 	pll = &dev_priv->shared_dplls[dpll];  in bxt_calc_pll_link()
1181 	uint32_t dpll = port;  in bxt_ddi_clock_get()  local
1183 	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);  in bxt_ddi_clock_get()
2299 		uint32_t dpll = crtc->config->ddi_pll_sel;  in intel_ddi_pre_enable()  local
2307 			WARN_ON(dpll != SKL_DPLL0);  in intel_ddi_pre_enable()
2311 			val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |  in intel_ddi_pre_enable()
2312 				 DPLL_CTRL1_SSC(dpll) |  in intel_ddi_pre_enable()
2313 				 DPLL_CTRL1_LINK_RATE_MASK(dpll));  in intel_ddi_pre_enable()
2314 			val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);  in intel_ddi_pre_enable()
2325 		val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |  in intel_ddi_pre_enable()
2594 	unsigned int dpll;  in skl_ddi_pll_enable()  local
2598 	dpll = pll->id + 1;  in skl_ddi_pll_enable()
2602 	val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |  in skl_ddi_pll_enable()
2603 		 DPLL_CTRL1_LINK_RATE_MASK(dpll));  in skl_ddi_pll_enable()
2604 	val |= pll->config.hw_state.ctrl1 << (dpll * 6);  in skl_ddi_pll_enable()
2618 	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))  in skl_ddi_pll_enable()
2619 		DRM_ERROR("DPLL %d not locked\n", dpll);  in skl_ddi_pll_enable()
2638 	unsigned int dpll;  in skl_ddi_pll_get_hw_state()  local
2645 	dpll = pll->id + 1;  in skl_ddi_pll_get_hw_state()
2652 	hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;  in skl_ddi_pll_get_hw_state()
2655 	if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {  in skl_ddi_pll_get_hw_state()