Lines Matching refs:dpll
116 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
163 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
165 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
166 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
172 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
173 dpll |= in psb_intel_crtc_mode_set()
178 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in psb_intel_crtc_mode_set()
190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in psb_intel_crtc_mode_set()
197 dpll |= 3; in psb_intel_crtc_mode_set()
199 dpll |= PLL_REF_INPUT_DREFCLK; in psb_intel_crtc_mode_set()
214 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
223 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
226 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
260 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
261 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
266 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
268 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
315 u32 dpll; in psb_intel_crtc_clock_get() local
322 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
323 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in psb_intel_crtc_clock_get()
330 dpll = p->dpll; in psb_intel_crtc_clock_get()
332 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in psb_intel_crtc_clock_get()
347 ffs((dpll & in psb_intel_crtc_clock_get()
352 if ((dpll & PLL_REF_INPUT_MASK) == in psb_intel_crtc_clock_get()
359 if (dpll & PLL_P1_DIVIDE_BY_TWO) in psb_intel_crtc_clock_get()
363 ((dpll & in psb_intel_crtc_clock_get()
367 if (dpll & PLL_P2_DIVIDE_BY_4) in psb_intel_crtc_clock_get()