Lines Matching refs:dpll
275 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
282 REG_READ(map->dpll); in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
331 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
338 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
344 REG_READ(map->dpll); in mdfld_crtc_dpms()
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
349 REG_READ(map->dpll); in mdfld_crtc_dpms()
461 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
467 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
468 REG_READ(map->dpll); in mdfld_crtc_dpms()
681 u32 dpll = 0, fp = 0; in mdfld_crtc_mode_set() local
928 dpll = REG_READ(map->dpll); in mdfld_crtc_mode_set()
930 if (dpll & DPLL_VCO_ENABLE) { in mdfld_crtc_mode_set()
931 dpll &= ~DPLL_VCO_ENABLE; in mdfld_crtc_mode_set()
932 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
933 REG_READ(map->dpll); in mdfld_crtc_mode_set()
941 dpll &= ~MDFLD_P1_MASK; in mdfld_crtc_mode_set()
942 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
949 if (dpll & MDFLD_PWR_GATE_EN) { in mdfld_crtc_mode_set()
950 dpll &= ~MDFLD_PWR_GATE_EN; in mdfld_crtc_mode_set()
951 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
955 dpll = 0; in mdfld_crtc_mode_set()
960 dpll &= ~MDFLD_INPUT_REF_SEL; in mdfld_crtc_mode_set()
962 dpll |= MDFLD_INPUT_REF_SEL; in mdfld_crtc_mode_set()
966 dpll |= MDFLD_VCO_SEL; in mdfld_crtc_mode_set()
972 dpll |= (1 << (clock.p1 - 2)) << 17; in mdfld_crtc_mode_set()
975 dpll = 0x00050000; in mdfld_crtc_mode_set()
979 dpll = 0x02010000; in mdfld_crtc_mode_set()
984 dpll = 0x00020000; in mdfld_crtc_mode_set()
988 dpll = 0x00800000; in mdfld_crtc_mode_set()
993 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
997 dpll |= DPLL_VCO_ENABLE; in mdfld_crtc_mode_set()
998 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
999 REG_READ(map->dpll); in mdfld_crtc_mode_set()