Lines Matching refs:dpll
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
1604 u32 dpll = pipe_config->dpll_hw_state.dpll; in vlv_enable_pll() local
1615 I915_WRITE(reg, dpll); in vlv_enable_pll()
1626 I915_WRITE(reg, dpll); in vlv_enable_pll()
1629 I915_WRITE(reg, dpll); in vlv_enable_pll()
1632 I915_WRITE(reg, dpll); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1693 u32 dpll = crtc->config->dpll_hw_state.dpll; in i9xx_enable_pll() local
1712 dpll |= DPLL_DVO_2X_MODE; in i9xx_enable_pll()
1724 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1739 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1743 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1746 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1749 I915_WRITE(reg, dpll); in i9xx_enable_pll()
7162 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
7164 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
7167 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
7169 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
7180 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7184 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7305 u32 dpll, dpll_md; in vlv_compute_dpll() local
7312 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | in vlv_compute_dpll()
7316 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
7317 dpll |= DPLL_VCO_ENABLE; in vlv_compute_dpll()
7318 pipe_config->dpll_hw_state.dpll = dpll; in vlv_compute_dpll()
7337 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
7338 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
7339 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
7340 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
7341 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
7419 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
7423 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
7442 bestn = pipe_config->dpll.n; in chv_prepare_pll()
7443 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
7444 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
7445 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
7446 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
7447 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
7448 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7456 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7544 const struct dpll *dpll) in vlv_force_pll_on() argument
7551 .dpll = *dpll, in vlv_force_pll_on()
7588 u32 dpll; in i9xx_compute_dpll() local
7590 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
7597 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
7600 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
7602 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
7605 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
7610 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
7613 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
7617 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
7619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
7621 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
7625 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
7628 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
7631 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
7634 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
7638 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
7641 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
7644 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
7646 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
7648 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
7649 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
7665 u32 dpll; in i8xx_compute_dpll() local
7666 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
7670 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
7673 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
7676 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
7678 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
7680 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
7684 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
7688 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
7690 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
7692 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
7693 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
7951 crtc_state->dpll.n = clock.n; in i9xx_crtc_compute_clock()
7952 crtc_state->dpll.m1 = clock.m1; in i9xx_crtc_compute_clock()
7953 crtc_state->dpll.m2 = clock.m2; in i9xx_crtc_compute_clock()
7954 crtc_state->dpll.p1 = clock.p1; in i9xx_crtc_compute_clock()
7955 crtc_state->dpll.p2 = clock.p2; in i9xx_crtc_compute_clock()
8014 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) in vlv_crtc_clock_get()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8198 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; in i9xx_get_pipe_config()
8204 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
8810 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) in ironlake_needs_fb_cb_tune() argument
8812 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ironlake_needs_fb_cb_tune()
8827 uint32_t dpll; in ironlake_compute_dpll() local
8862 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
8868 dpll = 0; in ironlake_compute_dpll()
8871 dpll |= DPLLB_MODE_LVDS; in ironlake_compute_dpll()
8873 dpll |= DPLLB_MODE_DAC_SERIAL; in ironlake_compute_dpll()
8875 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
8879 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
8881 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
8884 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8886 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
8888 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
8890 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ironlake_compute_dpll()
8893 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ironlake_compute_dpll()
8896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ironlake_compute_dpll()
8899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ironlake_compute_dpll()
8904 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ironlake_compute_dpll()
8906 dpll |= PLL_REF_INPUT_DREFCLK; in ironlake_compute_dpll()
8908 return dpll | DPLL_VCO_ENABLE; in ironlake_compute_dpll()
8916 u32 dpll = 0, fp = 0, fp2 = 0; in ironlake_crtc_compute_clock() local
8937 crtc_state->dpll.n = clock.n; in ironlake_crtc_compute_clock()
8938 crtc_state->dpll.m1 = clock.m1; in ironlake_crtc_compute_clock()
8939 crtc_state->dpll.m2 = clock.m2; in ironlake_crtc_compute_clock()
8940 crtc_state->dpll.p1 = clock.p1; in ironlake_crtc_compute_clock()
8941 crtc_state->dpll.p2 = clock.p2; in ironlake_crtc_compute_clock()
8946 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_crtc_compute_clock()
8950 dpll = ironlake_compute_dpll(crtc, crtc_state, in ironlake_crtc_compute_clock()
8954 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_crtc_compute_clock()
9325 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
10530 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
10532 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
10549 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
10555 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
10571 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
10574 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
10577 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
10579 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
10583 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
10588 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
10601 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
10609 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
10612 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
10615 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
10698 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
12092 pipe_config->dpll_hw_state.dpll, in intel_dump_pipe_config()
12609 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
12946 int dpll; in intel_modeset_clear_plls() local
12950 dpll = intel_crtc_state->shared_dpll; in intel_modeset_clear_plls()
12952 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) in intel_modeset_clear_plls()
12960 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); in intel_modeset_clear_plls()
13348 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state()
13368 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()
13379 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); in ibx_pch_dpll_enable()