Lines Matching refs:dpll
591 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
673 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= 3; in cdv_intel_crtc_mode_set()
690 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
736 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
737 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
772 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
781 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
783 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
787 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
856 u32 dpll; in cdv_intel_crtc_clock_get() local
863 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
864 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
871 dpll = p->dpll; in cdv_intel_crtc_clock_get()
872 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in cdv_intel_crtc_clock_get()
887 ffs((dpll & in cdv_intel_crtc_clock_get()
892 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
896 if ((dpll & PLL_REF_INPUT_MASK) == in cdv_intel_crtc_clock_get()
903 if (dpll & PLL_P1_DIVIDE_BY_TWO) in cdv_intel_crtc_clock_get()
907 ((dpll & in cdv_intel_crtc_clock_get()
911 if (dpll & PLL_P2_DIVIDE_BY_4) in cdv_intel_crtc_clock_get()