| /linux-4.4.14/drivers/usb/musb/ |
| D | musbhsdma.c | 42 static void dma_controller_stop(struct musb_dma_controller *controller) in dma_controller_stop() argument
44 struct musb *musb = controller->private_data; in dma_controller_stop()
48 if (controller->used_channels != 0) { in dma_controller_stop()
49 dev_err(musb->controller, in dma_controller_stop()
53 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
54 channel = &controller->channel[bit].channel; in dma_controller_stop()
57 if (!controller->used_channels) in dma_controller_stop()
67 struct musb_dma_controller *controller = container_of(c, in dma_channel_allocate() local
68 struct musb_dma_controller, controller); in dma_channel_allocate()
74 if (!(controller->used_channels & (1 << bit))) { in dma_channel_allocate()
[all …]
|
| D | ux500_dma.c | 44 struct ux500_dma_controller *controller; member
55 struct dma_controller controller; member
71 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
94 struct musb *musb = ux500_channel->controller->private_data; in ux500_configure_channel()
96 ux500_channel->controller->phy_base); in ux500_configure_channel()
98 dev_dbg(musb->controller, in ux500_configure_channel()
143 struct ux500_dma_controller *controller = container_of(c, in ux500_dma_channel_allocate() local
144 struct ux500_dma_controller, controller); in ux500_dma_channel_allocate()
146 struct musb *musb = controller->private_data; in ux500_dma_channel_allocate()
159 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : in ux500_dma_channel_allocate()
[all …]
|
| D | musb_cppi41.c | 27 struct cppi41_dma_controller *controller; member
48 struct dma_controller controller; member
66 if (!is_host_active(cppi41_channel->controller->musb)) in save_rx_toggle()
99 dev_dbg(cppi41_channel->controller->musb->controller, in update_rx_toggle()
189 struct cppi41_dma_controller *controller; in cppi41_recheck_tx_req() local
195 controller = container_of(timer, struct cppi41_dma_controller, in cppi41_recheck_tx_req()
197 musb = controller->musb; in cppi41_recheck_tx_req()
200 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list, in cppi41_recheck_tx_req()
212 if (!list_empty(&controller->early_tx_list) && in cppi41_recheck_tx_req()
213 !hrtimer_is_queued(&controller->early_tx)) { in cppi41_recheck_tx_req()
[all …]
|
| D | cppi_dma.c | 117 c->controller = cppi; in cppi_pool_init()
136 struct cppi *cppi = c->controller; in cppi_pool_free()
141 c->controller = NULL; in cppi_pool_free()
153 static void cppi_controller_start(struct cppi *controller) in cppi_controller_start() argument
159 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { in cppi_controller_start()
160 controller->tx[i].transmit = true; in cppi_controller_start()
161 controller->tx[i].index = i; in cppi_controller_start()
163 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { in cppi_controller_start()
164 controller->rx[i].transmit = false; in cppi_controller_start()
165 controller->rx[i].index = i; in cppi_controller_start()
[all …]
|
| D | tusb6010_omap.c | 58 struct dma_controller controller; member
76 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", in tusb_omap_use_shared_dmareq()
113 struct device *dev = musb->controller; in tusb_omap_dma_cb()
130 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", in tusb_omap_dma_cb()
143 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", in tusb_omap_dma_cb()
152 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); in tusb_omap_dma_cb()
158 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); in tusb_omap_dma_cb()
196 dev_dbg(musb->controller, "terminating short tx packet\n"); in tusb_omap_dma_cb()
214 struct device *dev = musb->controller; in tusb_omap_dma_program()
251 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", in tusb_omap_dma_program()
[all …]
|
| D | musb_gadget.c | 83 musb->controller, in map_dma_buffer()
89 ret = dma_mapping_error(musb->controller, dma_addr); in map_dma_buffer()
96 dma_sync_single_for_device(musb->controller, in map_dma_buffer()
116 dev_vdbg(musb->controller, in unmap_dma_buffer()
121 dma_unmap_single(musb->controller, in unmap_dma_buffer()
129 dma_sync_single_for_cpu(musb->controller, in unmap_dma_buffer()
171 dev_dbg(musb->controller, "%s done request %p, %d/%d\n", in musb_g_giveback()
175 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", in musb_g_giveback()
220 dev_dbg(musb->controller, "%s: abort DMA --> %d\n", in nuke()
269 dev_dbg(musb->controller, "ep:%s disabled - ignore request\n", in txstate()
[all …]
|
| /linux-4.4.14/drivers/spi/ |
| D | spi-qup.c | 158 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
160 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
165 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
171 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
180 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
183 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
190 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
191 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
195 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
199 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
[all …]
|
| D | Kconfig | 15 controller and a chipselect. Most SPI slaves don't support
19 eeprom and flash memory, codecs and various other controller
36 sysfs, and debugfs support in SPI controller and protocol drivers.
47 If your system has an master-capable SPI controller (which
49 controller and the protocol drivers for the SPI slave chips
63 tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
67 This enables support for the SPI controller present on the
79 tristate "BCM2835 SPI controller"
86 The BCM2835 contains two types of SPI master controller; the
87 "universal SPI master", and the regular SPI controller. This driver
[all …]
|
| /linux-4.4.14/drivers/gpio/ |
| D | gpio-zevio.c | 83 struct zevio_gpio *controller = to_zevio_gpio(chip); in zevio_gpio_get() local
86 spin_lock(&controller->lock); in zevio_gpio_get()
87 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
89 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
91 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
92 spin_unlock(&controller->lock); in zevio_gpio_get()
99 struct zevio_gpio *controller = to_zevio_gpio(chip); in zevio_gpio_set() local
102 spin_lock(&controller->lock); in zevio_gpio_set()
103 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_set()
109 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); in zevio_gpio_set()
[all …]
|
| /linux-4.4.14/arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 17 gpio-controller;
20 interrupt-controller;
28 gpio-controller;
31 interrupt-controller;
39 gpio-controller;
42 interrupt-controller;
47 gpio-controller;
50 interrupt-controller;
57 gpio-controller;
60 interrupt-controller;
[all …]
|
| /linux-4.4.14/arch/tile/kernel/ |
| D | pci_gx.c | 309 struct pci_controller *controller = irq_desc_get_handler_data(desc); in trio_handle_level_irq() local
310 gxio_trio_context_t *trio_context = controller->trio; in trio_handle_level_irq()
312 int mac = controller->mac; in trio_handle_level_irq()
337 static int tile_init_irqs(struct pci_controller *controller) in tile_init_irqs() argument
348 gxio_trio_context_t *context = controller->trio; in tile_init_irqs()
357 controller->irq_intx_table[i] = irq; in tile_init_irqs()
365 irq, controller->mac, i); in tile_init_irqs()
376 irq_set_handler_data(irq, controller); in tile_init_irqs()
383 irq_free_hwirq(controller->irq_intx_table[j]); in tile_init_irqs()
507 struct pci_controller *controller = &pci_controllers[i]; in tile_pci_init() local
[all …]
|
| D | pci.c | 101 static int tile_init_irqs(int controller_id, struct pci_controller *controller) in tile_init_irqs() argument
124 controller->irq_base = rc_config.intr; in tile_init_irqs()
131 controller->plx_gen1 = 1; in tile_init_irqs()
170 struct pci_controller *controller; in tile_pci_init() local
195 controller = &controllers[i]; in tile_pci_init()
197 controller->index = i; in tile_pci_init()
198 controller->hv_cfg_fd[0] = hv_cfg_fd0; in tile_pci_init()
199 controller->hv_cfg_fd[1] = hv_cfg_fd1; in tile_pci_init()
200 controller->hv_mem_fd = hv_mem_fd; in tile_pci_init()
201 controller->last_busno = 0xff; in tile_pci_init()
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
|
| D | exynos5260-clock.txt | 29 These clocks are fed into the clock controller and then routed to
66 - reg: physical base address of the controller and the length of
72 the given clock controller. Please refer the next section to find
73 the input clocks for a given controller.
76 to the given clock controller.
78 Input clocks for top clock controller:
84 Input clocks for peri clock controller:
100 Input clocks for egl clock controller:
104 Input clocks for kfc clock controller:
108 Input clocks for g2d clock controller:
[all …]
|
| D | exynos7-clock.txt | 3 Exynos7 clock controller has various blocks which are instantiated
25 compatible strings to indicate the clock controller
40 - reg: physical base address of the controller and the length of
46 the given clock controller. Please refer the next section to
47 find the input clocks for a given controller.
50 to the given clock controller.
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
67 Input clocks for ccore clock controller:
71 Input clocks for peric0 clock controller:
[all …]
|
| D | exynos3250-clock.txt | 3 The Exynos3250 clock controller generates and supplies clock to various
9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10 - "samsung,exynos3250-cmu-dmc" - controller compatible with
12 - "samsung,exynos3250-cmu-isp" - ISP block clock controller compatible
15 - reg: physical base address of the controller and length of memory mapped
27 Example 1: Examples of clock controller nodes are listed below.
29 cmu: clock-controller@10030000 {
35 cmu_dmc: clock-controller@105C0000 {
41 cmu_isp: clock-controller@10048000 {
47 Example 2: UART controller node that consumes the clock generated by the clock
[all …]
|
| D | exynos5420-clock.txt | 3 The Exynos5420 clock controller generates and supplies clock to various
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
12 - reg: physical base address of the controller and length of memory mapped
24 Example 1: An example of a clock controller node is listed below.
26 clock: clock-controller@0x10010000 {
32 Example 2: UART controller node that consumes the clock generated by the clock
33 controller. Refer to the standard clock bindings for information
|
| D | exynos4-clock.txt | 3 The Exynos4 clock controller generates and supplies clock to various controllers
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
25 Example 1: An example of a clock controller node is listed below.
27 clock: clock-controller@0x10030000 {
33 Example 2: UART controller node that consumes the clock generated by the clock
34 controller. Refer to the standard clock bindings for information
|
| D | samsung,s3c2410-clock.txt | 3 The S3C2410 clock controller generates and supplies clock to various controllers
10 - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
11 - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
12 - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
13 - reg: physical base address of the controller and length of memory mapped
31 Example: Clock controller node:
33 clocks: clock-controller@4c000000 {
39 Example: UART controller node that consumes the clock generated by the clock
40 controller (refer to the standard clock bindings for information about
|
| D | clk-exynos-audss.txt | 3 The Samsung Audio Subsystem clock controller generates and supplies clocks
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
15 - reg: physical base address and length of the controller's register set.
34 The following is the list of clocks generated by the controller. Each clock is
56 Example 1: An example of a clock controller node using the default input
59 clock_audss: audss-clock-controller@3810000 {
65 Example 2: An example of a clock controller node with the input clocks
68 clock_audss: audss-clock-controller@3810000 {
[all …]
|
| D | samsung,s3c2443-clock.txt | 3 The S3C2443 clock controller generates and supplies clock to various controllers
10 - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
11 - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
12 - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
13 - reg: physical base address of the controller and length of memory mapped
35 Example: Clock controller node:
37 clocks: clock-controller@4c000000 {
43 Example: UART controller node that consumes the clock generated by the clock
44 controller (refer to the standard clock bindings for information about
|
| D | exynos5250-clock.txt | 3 The Exynos5250 clock controller generates and supplies clock to various
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
11 - reg: physical base address of the controller and length of memory mapped
23 Example 1: An example of a clock controller node is listed below.
25 clock: clock-controller@0x10010000 {
31 Example 2: UART controller node that consumes the clock generated by the clock
32 controller. Refer to the standard clock bindings for information
|
| D | exynos4415-clock.txt | 3 The Exynos4415 clock controller generates and supplies clock to various
9 - "samsung,exynos4415-cmu" - for the main system clocks controller
12 Controller (DMC) domain clock controller.
14 - reg: physical base address of the controller and length of memory mapped
26 Example 1: An example of a clock controller node is listed below.
28 cmu: clock-controller@10030000 {
34 cmu-dmc: clock-controller@105C0000 {
|
| D | pistachio-clock.txt | 17 Core clock controller:
20 The core clock controller generates clocks for the CPU, RPU (WiFi + BT
25 - reg: Must contain the base address and length of the core clock controller.
34 clk_core: clock-controller@18144000 {
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
49 clock controller is the input clock to the peripheral clock controller.
54 controller.
59 by the core clock controller.
62 clk_periph: clock-controller@18144800 {
[all …]
|
| D | marvell,pxa1928.txt | 4 controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
10 - "marvell,pxa1928-apmu" - APMU controller compatible
11 - "marvell,pxa1928-mpmu" - MPMU controller compatible
12 - "marvell,pxa1928-apbc" - APBC controller compatible
13 - reg: physical base address of the clock controller and length of memory mapped
18 Each clock is assigned an identifier and client nodes use the clock controller
|
| D | amlogic,meson8b-clkc.txt | 3 The Amlogic Meson8b clock controller generates and supplies clock to various
12 1) physical base address of the clock controller and length of memory
22 Example: Clock controller node:
24 clkc: clock-controller@c1104000 {
31 Example: UART controller node that consumes the clock generated by the clock
32 controller:
|
| D | samsung,s5pv210-clock.txt | 4 controller, which generates and supplies clock to various controllers
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
40 Example: Clock controller node:
42 clock: clock-controller@7e00f000 {
64 Example: UART controller node that consumes the clock generated by the clock
65 controller (refer to the standard clock bindings for information about
|
| /linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mrvl,intc.txt | 1 * Marvell MMP Interrupt controller
6 - reg : Address and length of the register set of the interrupt controller.
7 If the interrupt controller is intc, address and length means the range
8 of the whold interrupt controller. If the interrupt controller is mux-intc,
10 range of intc. mux-intc is secondary interrupt controller.
11 - reg-names : Name of the register set of the interrupt controller. It's
12 only required in mux-intc interrupt controller.
14 only required in mux-intc interrupt controller.
15 - interrupt-controller : Identifies the node as an interrupt controller.
19 controller.
[all …]
|
| D | brcm,bcm7120-l2-intc.txt | 1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12 directly output an interrupt signal towards the interrupt controller parent,
14 controller, in particular for UARTs
20 - not all bits within the interrupt controller actually map to an interrupt
22 The typical hardware layout for this controller is represented below:
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
[all …]
|
| D | samsung,s3c24xx-irq.txt | 5 controller and on newer SoCs even a second main controller.
11 - reg: Physical base address of the controller and length of memory mapped
14 - interrupt-controller : Identifies the node as an interrupt controller
21 ctrl_num contains the controller to use:
22 - 0 ... main controller
23 - 1 ... sub controller
24 - 2 ... second main controller on s3c2416 and s3c2450
25 parent_irq contains the parent bit in the main controller and will be
27 ctrl_irq contains the interrupt bit of the controller
32 interrupt-controller@4a000000 {
[all …]
|
| D | abilis,tb10x-ictl.txt | 4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
13 - interrupt-congroller: Identifies the node as an interrupt controller.
15 source connected to this controller. The value shall be 2.
16 - interrupt-parent: Specifies the parent interrupt controller.
18 the interrupt controller in the parent controller's notation. Interrupts
24 intc: interrupt-controller { /* Parent interrupt controller */
25 interrupt-controller;
30 tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
33 interrupt-controller;
|
| D | marvell,orion-intc.txt | 3 * Main interrupt controller
8 - interrupt-controller: identifies the node as an interrupt controller
18 intc: interrupt-controller {
20 interrupt-controller;
26 * Bridge interrupt controller
31 - interrupts: bridge interrupt of the main interrupt controller
32 - interrupt-controller: identifies the node as an interrupt controller
37 controller, defaults to 32 if not set
40 bridge_intc: interrupt-controller {
42 interrupt-controller;
|
| D | brcm,bcm3380-l2-intc.txt | 1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
3 This interrupt controller shows up in various forms on many BCM338x/BCM63xx
6 - outputs a single interrupt signal to its interrupt controller parent
18 - interrupt-controller: identifies the node as an interrupt controller
21 - interrupt-parent: specifies the phandle to the parent interrupt controller
23 - interrupts: specifies the interrupt line in the interrupt-parent controller
24 node, valid values depend on the type of parent interrupt controller
28 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
33 irq0_intc: interrupt-controller@10000020 {
37 interrupt-controller;
|
| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
9 - reg: physical base address of the controller and length of memory mapped
11 - interrupt-controller: identifies the node as an interrupt controller
13 - interrupts: interrupt reference to primary interrupt controller
14 - interrupt-parent: (optional) reference specific primary interrupt controller
25 aic: interrupt-controller@3000 {
28 interrupt-controller;
|
| D | qca,ath79-misc-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
10 - interrupt-parent: phandle of the parent interrupt controller.
12 - interrupt-controller : Identifies the node as an interrupt controller
24 interrupt-controller@18060010 {
31 interrupt-controller;
37 interrupt-controller@18060010 {
44 interrupt-controller;
|
| D | samsung,exynos4210-combiner.txt | 3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
11 is usually connected to a parent interrupt controller.
14 controller module (which includes multiple combiners). A combiner in the
15 interrupt controller module shares config/control registers with other
22 - interrupt-controller: Identifies the node as an interrupt controller.
28 connected to a parent interrupt controller. The format of the interrupt
29 specifier depends in the interrupt parent controller.
35 - interrupt-parent: pHandle of the parent interrupt controller, if not
[all …]
|
| D | brcm,bcm2835-armctrl-ic.txt | 3 The BCM2835 contains a custom top-level interrupt controller, which supports
5 controller, or the HW block containing it, is referred to occasionally
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
17 - interrupt-controller : Identifies the node as an interrupt controller
29 - interrupt-parent : Specifies the parent interrupt controller when this
30 controller is the second level.
32 controller to handle.
117 intc: interrupt-controller {
120 interrupt-controller;
[all …]
|
| D | msi.txt | 17 they can address. An MSI controller may feature a number of doorbells.
28 MSI controller and device rather than a property of either in isolation).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
51 the specific MSI controller.
65 controller which the device is capable of using.
85 msi_a: msi-controller@a {
87 compatible = "vendor-a,some-controller";
88 msi-controller;
[all …]
|
| D | lsi,zevio-intc.txt | 1 TI-NSPIRE interrupt controller
6 - reg: Physical base address of the controller and length of memory mapped
9 - interrupt-controller : Identifies the node as an interrupt controller
13 interrupt-controller {
15 interrupt-controller;
|
| D | marvell,armada-370-xp-mpic.txt | 6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
8 Interrupt controller.
16 automatically map to the interrupt controller registers of the
22 connected as a slave to another interrupt controller. This is
29 mpic: interrupt-controller@d0020000 {
34 interrupt-controller;
35 msi-controller;
|
| D | ti,c64x+megamod-pic.txt | 6 The core interrupt controller provides 16 prioritized interrupts to the
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
39 the core interrupt controller. When an individual interrupt is cascaded,
41 considered to have the core interrupt controller as the parent.
46 - interrupt-controller
49 - interrupt-parent: must be core interrupt controller
70 use the core interrupt controller as their parent and the specifier will
[all …]
|
| D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
14 - interrupt-controller : Identifies the node as an interrupt controller
17 - interrupts: interrupt reference to primary interrupt controller
23 intc: interrupt-controller@48200000 {
25 interrupt-controller;
|
| D | brcm,l2-intc.txt | 7 - interrupt-controller: identifies the node as an interrupt controller
10 - interrupt-parent: specifies the phandle to the parent interrupt controller
11 this controller is cacaded from
17 - brcm,irq-can-wake: If present, this means the L2 controller can be used as a
22 hif_intr2_intc: interrupt-controller@f0441000 {
25 interrupt-controller;
|
| D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
10 - interrupt-controller: Identifies the node as an interrupt controller
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
16 on the controller at boot for example.
27 interrupt-controller;
34 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
35 output is simply connected to the input of another IRQ controller,
|
| D | interrupts.txt | 12 format of the interrupt specifier is determined by the interrupt controller to
19 The "interrupt-parent" property is used to specify the controller to which
21 controller node. This property is inherited, so it may be specified in an
33 2) Interrupt controller nodes
36 A device is marked as an interrupt controller with the "interrupt-controller"
40 It is the responsibility of the interrupt controller's binding to define the
47 index of the interrupt within the controller.
53 interrupt-controller;
60 interrupt-controller;
70 index of the interrupt within the controller, while the second cell is used
[all …]
|
| D | renesas,intc-irqpin.txt | 1 DT bindings for the R-/SH-Mobile irqpin controller
14 IRQ pins driven by the interrupt controller hardware module. The base
16 - interrupt-controller: Identifies the node as an interrupt controller.
20 provided by this irqpin controller instance, there must be one entry,
30 controller, needed for some broken implementations
33 the irqpin controller instance.
35 mandatory if the irqpin controller instance is part of a controllable power
42 irqpin1: interrupt-controller@e6900004 {
46 interrupt-controller;
|
| D | ingenic,intc.txt | 11 - interrupt-controller : Identifies the node as an interrupt controller
14 - interrupt-parent : phandle of the CPU interrupt controller.
15 - interrupts : Specifies the CPU interrupt the controller is connected to.
19 intc: interrupt-controller@10001000 {
23 interrupt-controller;
|
| D | snps,archs-idu-intc.txt | 3 This optional 2nd level interrupt controller can be used in SMP configurations for
9 - interrupt-controller: This is an interrupt controller.
22 core_intc: core-interrupt-controller {
24 interrupt-controller;
28 idu_intc: idu-interrupt-controller {
30 interrupt-controller;
|
| D | ti,omap2-intc.txt | 3 OMAP2/3 are using a TI interrupt controller that can support several
10 - interrupt-controller : Identifies the node as an interrupt controller
15 - ti,intc-size: Number of interrupts handled by the interrupt controller.
20 intc: interrupt-controller@1 {
22 interrupt-controller;
|
| D | st,spear3xx-shirq.txt | 5 interrupt controller (VIC) on behalf of a group of devices.
15 interrupt controller shares config/control registers with other groups.
24 - interrupt-controller: Identifies the node as an interrupt controller.
29 then connected to a parent interrupt controller. Each group is
32 specifier depends in the interrupt parent controller.
35 - interrupt-parent: pHandle of the parent interrupt controller, if not
42 shirq: interrupt-controller@0xb3000000 {
47 interrupt-controller;
|
| D | snps,arc700-intc.txt | 3 The core interrupt controller provides 32 prioritised interrupts (2 levels)
9 - interrupt-controller: This is an interrupt controller.
20 intc: interrupt-controller {
22 interrupt-controller;
|
| D | allwinner,sun67i-sc-nmi.txt | 9 - interrupt-controller : Identifies the node as an interrupt controller
13 - interrupt-parent: Specifies the parent interrupt controller.
15 the interrupt controller in the parent controller's notation. This value
22 interrupt-controller;
|
| D | qca,ath79-cpu-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
3 On most SoC the IRQ controller need to flush the DDR FIFO before running
11 - interrupt-controller : Identifies the node as an interrupt controller
28 interrupt-controller {
31 interrupt-controller;
41 ddr_ctrl: memory-controller@18000000 {
|
| D | axis,crisv32-intc.txt | 3 Interrupt controller for the CRISv32 SoCs.
9 - interrupt-controller : Identifies the node as an interrupt controller
16 intc: interrupt-controller {
19 interrupt-controller;
|
| D | digicolor-ic.txt | 6 - reg : Specifies base physical address and size of the interrupt controller
8 - interrupt-controller : Identifies the node as an interrupt controller
15 intc: interrupt-controller@f0000040 {
17 interrupt-controller;
|
| D | brcm,bcm2836-l1-intc.txt | 1 BCM2836 per-CPU interrupt controller
3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
6 controller.
13 - interrupt-controller: Identifies the node as an interrupt controller
34 interrupt-controller;
|
| D | img,meta-intc.txt | 4 representation of a Meta external trigger controller.
8 - compatible: Specifies the compatibility list for the interrupt controller.
14 - interrupt-controller: The presence of this property identifies the node
15 as an interrupt controller. No property value shall be defined.
26 - no-mask: The controller doesn't have any mask registers.
47 // This is an interrupt controller node.
48 interrupt-controller;
51 // reference this interrupt controller node do not need a parent
80 // The interrupt controller that this device is wired to.
|
| D | brcm,bcm7038-l1-intc.txt | 1 Broadcom BCM7038-style Level 1 interrupt controller
3 This block is a first level interrupt controller that is typically connected
28 - interrupt-controller: identifies the node as an interrupt controller
31 - interrupt-parent: specifies the phandle to the parent interrupt controller(s)
33 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
34 node; valid values depend on the type of parent interrupt controller
47 interrupt-controller;
|
| D | arm,gic.txt | 8 Secondary GICs are cascaded into the upward interrupt controller and do not
24 - interrupt-controller : Identifies the node as an interrupt controller
54 - interrupts : Interrupt source of the parent interrupt controller on
73 the power controller specified by phandle, used when the GIC
79 intc: interrupt-controller@fff11000 {
83 interrupt-controller;
93 primary interrupt controller).
106 interrupt-controller@2c001000 {
109 interrupt-controller;
127 - msi-controller : Identifies the node as an MSI controller.
[all …]
|
| /linux-4.4.14/arch/arm/boot/dts/ |
| D | exynos5420-pinctrl.dtsi | 17 gpio-controller;
20 interrupt-controller;
25 gpio-controller;
28 interrupt-controller;
36 gpio-controller;
39 interrupt-controller;
47 gpio-controller;
50 interrupt-controller;
55 gpio-controller;
58 interrupt-controller;
[all …]
|
| D | exynos5250-pinctrl.dtsi | 17 gpio-controller;
20 interrupt-controller;
25 gpio-controller;
28 interrupt-controller;
33 gpio-controller;
36 interrupt-controller;
41 gpio-controller;
44 interrupt-controller;
49 gpio-controller;
52 interrupt-controller;
[all …]
|
| D | exynos5260-pinctrl.dtsi | 21 gpio-controller;
24 interrupt-controller;
29 gpio-controller;
32 interrupt-controller;
37 gpio-controller;
40 interrupt-controller;
45 gpio-controller;
48 interrupt-controller;
53 gpio-controller;
56 interrupt-controller;
[all …]
|
| D | exynos4415-pinctrl.dtsi | 16 gpio-controller;
19 interrupt-controller;
24 gpio-controller;
27 interrupt-controller;
32 gpio-controller;
35 interrupt-controller;
40 gpio-controller;
43 interrupt-controller;
48 gpio-controller;
51 interrupt-controller;
[all …]
|
| D | stih415-pinctrl.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 pin-controller-sbc {
56 gpio-controller;
58 interrupt-controller;
64 gpio-controller;
66 interrupt-controller;
72 gpio-controller;
74 interrupt-controller;
80 gpio-controller;
82 interrupt-controller;
[all …]
|
| D | exynos3250-pinctrl.dtsi | 33 gpio-controller;
36 interrupt-controller;
41 gpio-controller;
44 interrupt-controller;
49 gpio-controller;
52 interrupt-controller;
57 gpio-controller;
60 interrupt-controller;
65 gpio-controller;
68 interrupt-controller;
[all …]
|
| D | exynos4x12-pinctrl.dtsi | 34 gpio-controller;
37 interrupt-controller;
42 gpio-controller;
45 interrupt-controller;
50 gpio-controller;
53 interrupt-controller;
58 gpio-controller;
61 interrupt-controller;
66 gpio-controller;
69 interrupt-controller;
[all …]
|
| D | stih416-pinctrl.dtsi | 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 pin-controller-sbc {
60 gpio-controller;
62 interrupt-controller;
68 gpio-controller;
70 interrupt-controller;
76 gpio-controller;
78 interrupt-controller;
84 gpio-controller;
86 interrupt-controller;
[all …]
|
| D | exynos4210-pinctrl.dtsi | 20 gpio-controller;
23 interrupt-controller;
28 gpio-controller;
31 interrupt-controller;
36 gpio-controller;
39 interrupt-controller;
44 gpio-controller;
47 interrupt-controller;
52 gpio-controller;
55 interrupt-controller;
[all …]
|
| D | hi3620.dtsi | 83 gic: interrupt-controller@1000 {
87 interrupt-controller;
92 sysctrl: system-controller@802000 {
215 gpio-controller;
219 interrupt-controller;
229 gpio-controller;
234 interrupt-controller;
244 gpio-controller;
249 interrupt-controller;
259 gpio-controller;
[all …]
|
| D | s5pv210-pinctrl.dtsi | 24 gpio-controller;
27 interrupt-controller;
32 gpio-controller;
35 interrupt-controller;
40 gpio-controller;
43 interrupt-controller;
48 gpio-controller;
51 interrupt-controller;
56 gpio-controller;
59 interrupt-controller;
[all …]
|
| D | s3c2416-pinctrl.dtsi | 17 gpio-controller;
22 gpio-controller;
27 gpio-controller;
32 gpio-controller;
37 gpio-controller;
42 gpio-controller;
44 interrupt-controller;
49 gpio-controller;
51 interrupt-controller;
56 gpio-controller;
[all …]
|
| D | hisi-x5hd2.dtsi | 18 gic: interrupt-controller@f8a01000 {
22 interrupt-controller;
139 gpio-controller;
143 interrupt-controller;
152 gpio-controller;
156 interrupt-controller;
165 gpio-controller;
169 interrupt-controller;
178 gpio-controller;
182 interrupt-controller;
[all …]
|
| D | mmp2.dtsi | 42 intc: interrupt-controller@d4282000 {
44 interrupt-controller;
50 intcmux4: interrupt-controller@d4282150 {
53 interrupt-controller;
60 intcmux5: interrupt-controller@d4282154 {
63 interrupt-controller;
71 intcmux9: interrupt-controller@d4282180 {
74 interrupt-controller;
81 intcmux17: interrupt-controller@d4282158 {
84 interrupt-controller;
[all …]
|
| D | exynos5260.dtsi | 83 clock_top: clock-controller@10010000 {
89 clock_peri: clock-controller@10200000 {
95 clock_egl: clock-controller@10600000 {
101 clock_kfc: clock-controller@10700000 {
107 clock_g2d: clock-controller@10A00000 {
113 clock_mif: clock-controller@10CE0000 {
119 clock_mfc: clock-controller@11090000 {
125 clock_g3d: clock-controller@11830000 {
131 clock_fsys: clock-controller@122E0000 {
137 clock_aud: clock-controller@128C0000 {
[all …]
|
| D | stih407-pinctrl.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 pin-controller-sbc {
60 gpio-controller;
62 interrupt-controller;
68 gpio-controller;
70 interrupt-controller;
76 gpio-controller;
78 interrupt-controller;
84 gpio-controller;
86 interrupt-controller;
[all …]
|
| D | qcom-apq8084.dtsi | 98 intc: interrupt-controller@f9000000 {
100 interrupt-controller;
165 saw0: power-controller@f9089000 {
170 saw1: power-controller@f9099000 {
175 saw2: power-controller@f90a9000 {
180 saw3: power-controller@f90b9000 {
185 saw_l2: power-controller@f9012000 {
191 acc0: clock-controller@f9088000 {
197 acc1: clock-controller@f9098000 {
203 acc2: clock-controller@f90a8000 {
[all …]
|
| D | s3c64xx-pinctrl.dtsi | 25 gpio-controller;
27 interrupt-controller;
32 gpio-controller;
34 interrupt-controller;
39 gpio-controller;
41 interrupt-controller;
46 gpio-controller;
48 interrupt-controller;
53 gpio-controller;
58 gpio-controller;
[all …]
|
| D | k2hk.dtsi | 51 gpio-controller;
58 gpio-controller;
65 gpio-controller;
72 gpio-controller;
79 gpio-controller;
86 gpio-controller;
93 gpio-controller;
100 gpio-controller;
|
| D | bcm7445.dtsi | 1 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 gic: interrupt-controller@ffd00000 {
55 interrupt-controller;
100 irq0_intc: interrupt-controller@40a780 {
105 interrupt-controller;
112 irq0_aon_intc: interrupt-controller@417280 {
117 interrupt-controller;
126 hif_intr2_intc: interrupt-controller@3e1000 {
129 interrupt-controller;
136 aon_pm_l2_intc: interrupt-controller@410640 {
[all …]
|
| D | berlin2cd.dtsi | 44 #include <dt-bindings/interrupt-controller/arm-gic.h>
103 l2: l2-cache-controller@ac0000 {
110 gic: interrupt-controller@ad1000 {
113 interrupt-controller;
192 gpio-controller;
196 interrupt-controller;
210 gpio-controller;
214 interrupt-controller;
228 gpio-controller;
232 interrupt-controller;
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/gpio/ |
| D | gpio-mxs.txt | 1 * Freescale MXS GPIO controller
3 The Freescale MXS GPIO controller is part of MXS PIN controller. The
6 As the GPIO controller is embedded in the PIN controller and all the
7 GPIO ports share the same IO space with PIN controller, the GPIO node
14 - gpio-controller : Marks the device node as a gpio controller.
19 - interrupt-controller: Marks the device node as an interrupt controller.
47 gpio-controller;
49 interrupt-controller;
56 gpio-controller;
58 interrupt-controller;
[all …]
|
| D | renesas,gpio-rcar.txt | 6 - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
7 - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
8 - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
9 - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
10 - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
11 - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
12 - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
13 - "renesas,gpio-rcar": for generic R-Car GPIO controller.
16 controller hardware module.
18 - interrupt-parent: phandle of the parent interrupt controller.
[all …]
|
| D | 8xxx_gpio.txt | 6 Every GPIO controller node must have #gpio-cells property defined,
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
28 - interrupt-parent: Phandle for the interrupt controller that
31 - gpio-controller: Marks the port as GPIO controller.
34 - interrupt-controller: Empty boolean property which marks the GPIO
35 module as an IRQ controller.
38 this interrupt controller. The first cell
[all …]
|
| D | brcm,brcmstb-gpio.txt | 1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
14 the brcmstb GPIO controller registers
17 Should be <2>. The first cell is the pin number (within the controller's
21 - gpio-controller:
22 Specifies that the node is a GPIO controller.
31 The interrupt shared by all GPIO lines for this controller.
34 phandle of the parent interrupt controller
40 wakeup interrupt lines through a different interrupt controller than the
[all …]
|
| D | gpio-nmk.txt | 1 Nomadik GPIO controller
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - interrupt-controller : Marks the device node as an interrupt controller.
17 - gpio-bank : Specifies which bank a controller owns.
18 - st,supports-sleepmode : Specifies whether controller can sleep or not
27 gpio-controller;
28 interrupt-controller;
|
| D | gpio-atlas7.txt | 1 CSR SiRFatlas7 GPIO controller bindings
7 - gpio-banks : How many gpio banks on this controller
8 - gpio-controller : Indicates this device is a GPIO controller
9 - interrupt-controller : Marks the device node as an interrupt controller
11 The GPIO controller also acts as an interrupt controller. It uses the default
13 interrupt-controller/interrupts.txt.
25 gpio-controller;
26 interrupt-controller;
|
| D | mrvl-gpio.txt | 1 * Marvell PXA GPIO controller
16 - interrupt-controller : Identifies the node as an interrupt controller.
19 - gpio-controller : Marks the device node as a gpio controller.
29 gpio-controller;
31 interrupt-controller;
42 gpio-controller;
44 interrupt-controller;
52 - reg : Address and length of the register set for controller.
53 - gpio-controller : So we know this is a gpio controller.
54 - ngpio : How many gpios this controller has.
[all …]
|
| D | gpio-xgene.txt | 1 APM X-Gene SoC GPIO controller bindings
3 This is a gpio controller that is part of the flash controller.
4 This gpio controller controls a total of 48 gpios.
7 - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8 - reg: Physical base address and size of the controller's registers
14 - gpio-controller: Marks the device node as a GPIO controller.
20 gpio-controller;
|
| D | gpio-altera.txt | 1 Altera GPIO controller bindings
6 - reg: Physical base address and length of the controller's registers.
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
13 - The first cell is the GPIO offset number within the GPIO controller.
16 hardware is synthesized. This field is required if the Altera GPIO controller
19 controller. The value is defined in <dt-bindings/interrupt-controller/irq.h>
40 gpio-controller;
42 interrupt-controller;
|
| D | snps-dwapb-gpio.txt | 1 * Synopsys DesignWare APB GPIO controller
9 The GPIO controller has a configurable number of ports, each of which are
14 - gpio-controller : Marks the device node as a gpio controller.
22 - interrupt-controller : The first port may be configured to be an interrupt
23 controller.
28 - interrupt-parent : The parent interrupt controller.
29 - interrupts : The interrupt to the parent controller raised when GPIOs
41 porta: gpio-controller@0 {
43 gpio-controller;
47 interrupt-controller;
[all …]
|
| D | abilis,tb10x-gpio.txt | 1 * Abilis TB10x GPIO controller
6 - gpio-controller: Marks the device node as a gpio controller.
13 - interrupt-controller: Marks the device node as an interrupt controller.
15 - interrupts: Defines the interrupt line connecting this GPIO controller to
16 its parent interrupt controller.
17 - interrupt-parent: Defines the parent interrupt controller.
26 interrupt-controller;
31 gpio-controller;
|
| D | gpio-sx150x.txt | 12 - interrupt-parent: phandle of the parent interrupt controller.
20 - gpio-controller: Marks the device as a GPIO controller.
22 - interrupt-controller: Marks the device as a interrupt controller.
24 The GPIO expander can optionally be used as an interrupt controller, in
26 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
38 gpio-controller;
39 interrupt-controller;
|
| D | gpio-tz1090.txt | 6 - reg: Physical base address of the controller and length of memory mapped
18 - gpio-controller: Specifies that the node is a gpio controller.
22 <[phandle of the gpio controller node]
34 - gpio-ranges: Mapping to pin controller pins (as described in
39 - interrupt-controller: Specifies that the node is an interrupt controller
43 <[phandle of the interurupt controller]
50 <dt-bindings/interrupt-controller/irq.h>. Only the following flags are
62 gpios: gpio-controller@02005800 {
74 gpio-controller;
76 interrupt-controller;
[all …]
|
| D | gpio-adnp.txt | 6 - interrupt-parent: phandle of the parent interrupt controller.
11 - gpio-controller: Marks the device as a GPIO controller
12 - nr-gpios: The number of pins supported by the controller.
14 The GPIO expander can optionally be used as an interrupt controller, in
16 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
20 gpioext: gpio-controller@41 {
27 gpio-controller;
30 interrupt-controller;
|
| D | gpio-davinci.txt | 1 Davinci/Keystone GPIO controller bindings
6 - reg: Physical base address of the controller and the size of memory mapped
9 - gpio-controller : Marks the device node as a gpio controller.
15 - interrupt-parent: phandle of the parent interrupt controller.
25 The GPIO controller also acts as an interrupt controller. It uses the default
27 interrupt-controller/interrupts.txt.
33 gpio-controller;
44 interrupt-controller;
|
| D | nvidia,tegra20-gpio.txt | 1 NVIDIA Tegra GPIO controller
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
12 - gpio-controller : Marks the device node as a GPIO controller.
22 - interrupt-controller : Marks the device node as an interrupt controller.
37 gpio-controller;
39 interrupt-controller;
|
| D | gpio.txt | 12 gpio-phandle : phandle to gpio controller node
14 (controller specific)
36 gpio-controller
40 gpio-controller
51 Note that gpio-specifier length is controller dependent. In the
58 Exact meaning of each specifier cell is controller specific, and must
72 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
91 GPIO controller that achieves (or represents, for inputs) a logically asserted
94 the GPIO controller and the device, then the gpio-specifier will represent the
121 (at the GPIO controller) assuming that the device is configured for this
[all …]
|
| D | gpio-max732x.txt | 15 - gpio-controller: Marks the device node as a GPIO controller.
24 an interrupt controller. When the expander interrupt line is connected all the
26 interrupt controller device tree bindings documentation available at
27 Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
29 - interrupt-controller: Identifies the node as an interrupt controller.
33 - interrupt-parent: phandle of the parent interrupt controller.
44 gpio-controller;
46 interrupt-controller;
57 gpio-controller;
|
| D | gpio-zynq.txt | 1 Xilinx Zynq GPIO controller Device Tree Bindings
11 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupt-parent : Must be core interrupt controller
15 - interrupt-controller : Marks the device node as an interrupt controller.
29 gpio-controller;
32 interrupt-controller;
|
| D | gpio-ath79.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller
9 - gpio-controller : Marks the device node as a GPIO controller.
15 - interrupt-parent: phandle of the parent interrupt controller.
17 - interrupt-controller : Identifies the node as an interrupt controller
33 gpio-controller;
36 interrupt-controller;
|
| D | gpio-twl4030.txt | 1 twl4030 GPIO controller bindings
5 - "ti,twl4030-gpio" for twl4030 GPIO controller
9 - gpio-controller : Marks the device node as a GPIO controller.
11 - interrupt-controller: Mark the device node as an interrupt controller
25 gpio-controller;
27 interrupt-controller;
|
| D | gpio-xlp.txt | 16 - reg: Physical base address and length of the controller's registers.
19 - gpio-controller: Marks the device node as a GPIO controller.
20 - nr-gpios: Number of GPIO pins supported by the controller.
30 - interrupt-parent: phandle of the parent interrupt controller.
31 - interrupt-controller: Identifies the node as an interrupt controller.
40 gpio-controller;
46 interrupt-controller;
|
| D | cavium-octeon-gpio.txt | 10 - gpio-controller: This is a GPIO controller.
14 - interrupt-controller: The GPIO controller is also an interrupt
15 controller, many of its pins may be configured as an interrupt
30 gpio-controller@1070000000800 {
34 gpio-controller;
42 interrupt-controller;
|
| D | brcm,kona-gpio.txt | 9 GPIO controller only supports edge, not level, triggering of interrupts.
15 - reg: Physical base address and length of the controller's registers.
16 - interrupts: The interrupt outputs from the controller. There is one GPIO
33 See also .../devicetree/bindings/interrupt-controller/interrupts.txt.
34 - gpio-controller: Marks the device node as a GPIO controller.
35 - interrupt-controller: Marks the device node as an interrupt controller.
50 gpio-controller;
51 interrupt-controller;
|
| D | gpio-xgene-sb.txt | 1 APM X-Gene Standby GPIO controller bindings
3 This is a gpio controller in the standby domain.
10 - compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
11 - reg: Physical base address and size of the controller's registers
17 - gpio-controller: Marks the device node as a GPIO controller.
25 gpio-controller;
|
| D | gpio-samsung.txt | 6 - reg: Physical base address of the controller and length of memory mapped
11 <[phandle of the gpio controller node]
12 [pin number within the gpio controller]
28 - gpio-controller: Specifies that the node is a gpio controller.
34 gpa0: gpio-controller@11400000 {
40 gpio-controller;
|
| D | gpio-tz1090-pdc.txt | 6 - reg: Physical base address of the controller and length of memory mapped
9 - gpio-controller: Specifies that the node is a gpio controller.
13 <[phandle of the gpio controller node]
25 - gpio-ranges: Mapping to pin controller pins (as described in
33 pdc_gpios: gpio-controller@02006500 {
34 gpio-controller;
|
| D | fsl-imx-gpio.txt | 1 * Freescale i.MX/MXC GPIO controller
9 - gpio-controller : Marks the device node as a gpio controller.
14 - interrupt-controller: Marks the device node as an interrupt controller.
28 gpio-controller;
30 interrupt-controller;
|
| D | gpio-omap.txt | 1 OMAP GPIO controller bindings
8 - gpio-controller : Marks the device node as a GPIO controller.
12 - interrupt-controller: Mark the device node as an interrupt controller.
35 gpio-controller;
37 interrupt-controller;
|
| D | gpio-vf610.txt | 12 - gpio-controller : Marks the device node as a gpio controller.
17 - interrupt-controller: Marks the device node as an interrupt controller.
39 gpio-controller;
41 interrupt-controller;
50 gpio-controller;
52 interrupt-controller;
|
| D | gpio-lp3943.txt | 1 TI/National Semiconductor LP3943 GPIO controller
5 - gpio-controller: Marks the device node as a GPIO controller.
10 Simple LED controls with LP3943 GPIO controller
19 gpio-controller;
|
| D | gpio-mvebu.txt | 1 * Marvell EBU GPIO controller
22 - interrupt-controller: identifies the node as an interrupt controller
34 - gpio-controller: marks the device node as a gpio controller
36 - ngpios: number of GPIOs this controller has
48 gpio-controller;
50 interrupt-controller;
|
| D | gpio-etraxfs.txt | 1 Axis ETRAX FS General I/O controller bindings
8 - reg: Physical base address and length of the controller's registers.
13 - gpio-controller: Marks the device node as a GPIO controller.
20 gpio-controller;
|
| D | zx296702-gpio.txt | 1 ZTE ZX296702 GPIO controller
8 - gpio-controller : Marks the device node as a GPIO controller.
15 gpio-controller;
20 interrupt-controller;
|
| D | gpio-palmas.txt | 1 Palmas GPIO controller bindings
5 - "ti,palams-gpio" for palma series of the GPIO controller
14 - gpio-controller : Marks the device node as a GPIO controller.
23 gpio-controller;
|
| D | gpio_atmel.txt | 1 * Atmel GPIO controller (PIO)
5 - reg: Should contain GPIO controller registers location and length
10 - gpio-controller: Marks the device node as a GPIO controller.
22 gpio-controller;
|
| /linux-4.4.14/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
66 msi: msi-controller@a {
68 compatible = "vendor,some-controller";
69 msi-controller;
[all …]
|
| D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
5 - reg: specifies the physical base address of the controller and
12 controller. The format of the interrupt specifier depends on the
13 parent interrupt controller.
15 - msi-controller: indicates that this is MSI controller node
26 msi-controller;
|
| D | layerscape-pci.txt | 1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
6 This controller derives its clocks from the Reset Configuration Word (RCW)
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
18 - reg: base addresses and lengths of the PCIe controller
19 - interrupts: A list of interrupt outputs of the controller. Must contain an
22 "intr": The interrupt that is asserted for controller interrupts
25 The second entry must be '0' or '1' based on physical PCIe controller index.
32 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
[all …]
|
| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
16 Each PCIe node needs to have property msi-parent that points to msi controller node
25 msi-controller;
45 + PCIe controller node with msi-parent property pointing to MSI node:
|
| D | pci-keystone.txt | 18 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
20 interrupt-parent: Parent interrupt controller phandle
24 pcie_msi_intc: msi-interrupt-controller {
25 interrupt-controller;
38 pcie_intc: Interrupt controller device node for Legacy IRQ chip
40 interrupt-parent: Parent interrupt controller phandle
44 pcie_intc: legacy-interrupt-controller {
45 interrupt-controller;
|
| /linux-4.4.14/drivers/char/agp/ |
| D | frontend.c | 295 struct agp_controller *controller; in agp_find_controller_by_pid() local
297 controller = agp_fe.controllers; in agp_find_controller_by_pid()
299 while (controller != NULL) { in agp_find_controller_by_pid()
300 if (controller->pid == id) in agp_find_controller_by_pid()
301 return controller; in agp_find_controller_by_pid()
302 controller = controller->next; in agp_find_controller_by_pid()
310 struct agp_controller *controller; in agp_create_controller() local
312 controller = kzalloc(sizeof(struct agp_controller), GFP_KERNEL); in agp_create_controller()
313 if (controller == NULL) in agp_create_controller()
316 controller->pid = id; in agp_create_controller()
[all …]
|
| /linux-4.4.14/drivers/pci/host/ |
| D | Kconfig | 1 menu "PCI host controller drivers"
5 bool "TI DRA7xx PCIe controller"
10 Enables support for the PCIe controller in the DRA7xx SoC. There
11 are two instances of PCIe controller in DRA7xx. This controller can
15 bool "Marvell EBU PCIe controller"
23 bool "Samsung Exynos PCIe controller"
29 bool "Freescale i.MX6 PCIe controller"
35 bool "NVIDIA Tegra PCIe controller"
38 Say Y here if you want support for the PCIe host controller found
42 bool "Renesas R-Car Gen2 Internal PCI controller"
[all …]
|
| /linux-4.4.14/arch/powerpc/boot/dts/ |
| D | mucmc52.dts | 17 &gpt0 { gpio-controller; };
18 &gpt1 { gpio-controller; };
19 &gpt2 { gpio-controller; };
20 &gpt3 { gpio-controller; };
164 simple100: gpio-controller-100@3,600100 {
167 gpio-controller;
170 simple104: gpio-controller-104@3,600104 {
173 gpio-controller;
176 simple200: gpio-controller-200@3,600200 {
179 gpio-controller;
[all …]
|
| D | uc101.dts | 16 &gpt0 { gpio-controller; };
17 &gpt1 { gpio-controller; };
18 &gpt2 { gpio-controller; };
19 &gpt3 { gpio-controller; };
20 &gpt4 { gpio-controller; };
21 &gpt5 { gpio-controller; };
22 &gpt6 { gpio-controller; };
23 &gpt7 { gpio-controller; };
|
| /linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mem-ctrlr.txt | 1 Freescale DDR memory controller
5 - compatible : Should include "fsl,chip-memory-controller" where
7 "fsl,qoriq-memory-controller".
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
13 memory-controller@2000 {
14 compatible = "fsl,bsc9132-memory-controller";
22 ddr1: memory-controller@8000 {
23 compatible = "fsl,qoriq-memory-controller-v4.7",
24 "fsl,qoriq-memory-controller";
|
| D | l2cache.txt | 8 - compatible : Should include "fsl,chip-l2-cache-controller" and "cache"
10 - reg : Address and size of L2 cache controller registers
12 - interrupts : Error interrupt of L2 controller
17 L2: l2-cache-controller@20000 {
18 compatible = "fsl,bsc9132-l2-cache-controller", "cache";
|
| /linux-4.4.14/Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller
4 controller. It controls the input/output settings on the available pads/pins
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
17 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
[all …]
|
| D | brcm,cygnus-gpio.txt | 11 GPIO/PINCONF controller registers
15 controller's pin space) and the second cell is used for the following:
18 - gpio-controller:
19 Specifies that the node is a GPIO controller
26 - interrupt-controller:
27 Specifies that the node is an interrupt controller
30 Specifies the mapping between gpio controller and pin-controllers pins.
32 1. Phandle of pin-controller.
40 The list of pins (within the controller's own pin space) that properties
61 gpio-controller;
[all …]
|
| D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
34 sys_pinctrl: pin-controller {
|
| D | rockchip,pinctrl.txt | 19 defined as gpio sub-nodes of the pinmux controller.
21 Required properties for iomux controller:
28 Optional properties for iomux controller:
30 as some SoCs carry parts of the iomux controller registers there.
34 Deprecated properties for iomux controller:
35 - reg: first element is the general register space of the iomux controller
43 - interrupts: base interrupt of the gpio bank in the interrupt controller
45 - gpio-controller: identifies the node as a gpio controller and pin bank.
49 - interrupt-controller: identifies the controller node as interrupt-parent.
52 bindings/interrupt-controller/interrupts.txt
[all …]
|
| D | atmel,at91-pio4-pinctrl.txt | 3 The Atmel PIO4 controller is used to select the function of a pin and to
8 - reg: base address and length of the PIO controller.
9 - interrupts: interrupt outputs from the controller, one for each bank.
10 - interrupt-controller: mark the device node as an interrupt controller.
12 - gpio-controller: mark the device node as a gpio controller.
15 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
53 interrupt-controller;
55 gpio-controller;
|
| D | renesas,pfc-pinctrl.txt | 3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
4 R8A73A4 and R8A7740 it also acts as a GPIO controller.
13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
17 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
18 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
[all …]
|
| D | img,pistachio-pinctrl.txt | 4 The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
5 interrupt controller, and pinmux + pinconf device. The system ("east") pin
6 controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
8 each. The GPIO banks are represented as sub-nodes of the pad controller node.
11 ../interrupt-controller/interrupts.txt for generic information regarding
12 pin controller, GPIO, and interrupt bindings.
14 Required properties for pin controller node:
22 - gpio-controller: Indicates the device is a GPIO controller.
26 - interrupt-controller: Indicates the device is an interrupt controller.
29 <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.
[all …]
|
| D | brcm,bcm2835-gpio.txt | 1 Broadcom BCM2835 GPIO (and pinmux) controller
3 The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
4 controller, and pinmux/control device.
9 - gpio-controller: Marks the device node as a GPIO controller.
13 - interrupts : The interrupt outputs from the controller. One interrupt per
15 - interrupt-controller: Marks the device node as an interrupt controller.
69 gpio-controller;
72 interrupt-controller;
|
| D | pinctrl-st.txt | 1 *ST pin controller.
31 Pin controller node:
40 - ranges : defines mapping between pin controller node (parent) to gpio-bank
50 GPIO controller/bank node.
52 - gpio-controller : Indicates this device is a GPIO controller
61 - interrupt-controller : Indicates this device is a interrupt controller. GPIO
62 bank can be an interrupt controller iff one of the interrupt type either via
67 gpio interrupt space of the controller.
75 include/dt-bindings/interrupt-controller/irq.h
78 pin-controller-sbc {
[all …]
|
| /linux-4.4.14/drivers/mailbox/ |
| D | bcm2835-mailbox.c | 64 struct mbox_controller controller; member
69 return container_of(link->mbox, struct bcm2835_mbox, controller); in bcm2835_link_mbox()
75 struct device *dev = mbox->controller.dev; in bcm2835_mbox_irq()
76 struct mbox_chan *link = &mbox->controller.chans[0]; in bcm2835_mbox_irq()
93 dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); in bcm2835_send_data()
170 mbox->controller.txdone_poll = true; in bcm2835_mbox_probe()
171 mbox->controller.txpoll_period = 5; in bcm2835_mbox_probe()
172 mbox->controller.ops = &bcm2835_mbox_chan_ops; in bcm2835_mbox_probe()
173 mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; in bcm2835_mbox_probe()
174 mbox->controller.dev = dev; in bcm2835_mbox_probe()
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/ |
| D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the ARxxx and AR9xxx families provides an interface
5 by the IRQ controller to flush the FIFO before running the interrupt handler
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
20 ddr_ctrl: memory-controller@18000000 {
21 compatible = "qca,ar9132-ddr-controller",
22 "qca,ar7240-ddr-controller";
[all …]
|
| D | mvebu-sdram-controller.txt | 3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
12 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
14 include all SDRAM controller registers as per the datasheet.
19 compatible = "marvell,armada-xp-sdram-controller";
|
| /linux-4.4.14/drivers/usb/host/ |
| D | ohci-dbg.c | 100 ohci_dump_status (struct ohci_hcd *controller, char **next, unsigned *size) in ohci_dump_status() argument
102 struct ohci_regs __iomem *regs = controller->regs; in ohci_dump_status()
105 temp = ohci_readl (controller, ®s->revision) & 0xff; in ohci_dump_status()
106 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
110 rh_state_string(controller)); in ohci_dump_status()
112 temp = ohci_readl (controller, ®s->control); in ohci_dump_status()
113 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
127 temp = ohci_readl (controller, ®s->cmdstatus); in ohci_dump_status()
128 ohci_dbg_sw (controller, next, size, in ohci_dump_status()
137 ohci_dump_intr_mask (controller, "intrstatus", in ohci_dump_status()
[all …]
|
| D | Kconfig | 12 Enable this option to support this chip in host controller mode.
22 "SuperSpeed" host controller hardware.
49 Say 'Y' to enable the support for the xHCI host controller
57 Say 'Y' to enable the support for the xHCI host controller
66 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
67 If your USB host controller supports USB 2.0, you will likely want to
73 connect to a companion controller. If you configure EHCI, you should
89 controller is needed. It's safe to say "y" even if your
90 controller doesn't support this feature.
126 tristate "EHCI support for on-chip PMC MSP71xx USB controller"
[all …]
|
| D | ehci-sysfs.c | 164 struct device *controller = ehci_to_hcd(ehci)->self.controller; in create_sysfs_files() local
169 i = device_create_file(controller, &dev_attr_companion); in create_sysfs_files()
173 i = device_create_file(controller, &dev_attr_uframe_periodic_max); in create_sysfs_files()
180 struct device *controller = ehci_to_hcd(ehci)->self.controller; in remove_sysfs_files() local
184 device_remove_file(controller, &dev_attr_companion); in remove_sysfs_files()
186 device_remove_file(controller, &dev_attr_uframe_periodic_max); in remove_sysfs_files()
|
| D | ehci-xilinx-of.c | 52 dev_warn(hcd->self.controller, "port %d cannot be enabled\n", portnum); in ehci_xilinx_port_handed_over()
54 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
57 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
60 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
62 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
65 dev_warn(hcd->self.controller, in ehci_xilinx_port_handed_over()
197 device_wakeup_enable(hcd->self.controller); in ehci_hcd_xilinx_of_probe()
|
| /linux-4.4.14/Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 1 NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
11 controller. This only support master mode of I2C communication. Register
13 controller. Driver of DVC I2C controller is only compatible with
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
17 support master mode of I2C communication. Driver of I2C controller is
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
20 very much similar to Tegra20 I2C controller with additional feature:
22 as per I2C core API transfer flags. Driver of I2C controller is
26 nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
[all …]
|
| D | i2c-pxa-pci-ce4100.txt | 6 controller. So we have a total of three independent I2C-Controllers
12 of the specific I2C controller. This were his exact words:
31 i2c-controller@b,2 {
55 compatible = "intel,ce4100-i2c-controller";
62 /* This I2C controller has no devices */
68 compatible = "intel,ce4100-i2c-controller";
71 /* This I2C controller has one gpio controller */
76 gpio-controller;
83 compatible = "intel,ce4100-i2c-controller";
90 gpio-controller;
|
| D | i2c-pxa.txt | 1 * Marvell MMP I2C controller
14 - interrupt-parent : the phandle for the interrupt controller that
16 interrupt controller in device tree, it could be ignored.
17 - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
18 status register of i2c controller instead.
19 - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
|
| /linux-4.4.14/drivers/pci/hotplug/ |
| D | pciehp_hpc.c | 44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) in ctrl_dev()
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
55 struct controller *ctrl = (struct controller *)data; in int_poll_timeout()
68 static void start_int_poll_timer(struct controller *ctrl, int sec) in start_int_poll_timer()
80 static inline int pciehp_request_irq(struct controller *ctrl) in pciehp_request_irq()
99 static inline void pciehp_free_irq(struct controller *ctrl) in pciehp_free_irq()
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout) in pcie_poll_cmd()
133 static void pcie_wait_cmd(struct controller *ctrl) in pcie_wait_cmd()
181 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, in pcie_do_write_cmd()
225 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) in pcie_write_cmd()
[all …]
|
| D | cpqphp.h | 275 struct controller *ctrl;
291 struct controller { struct
292 struct controller *next; argument
409 void cpqhp_create_debugfs_files(struct controller *ctrl);
410 void cpqhp_remove_debugfs_files(struct controller *ctrl);
415 int cpqhp_find_available_resources(struct controller *ctrl,
422 int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func);
423 int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func);
424 int cpqhp_hardware_test(struct controller *ctrl, int test_num);
431 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num,
[all …]
|
| D | cpci_hotplug_core.c | 61 static struct cpci_hp_controller *controller; variable
111 if (controller->ops->set_power) in enable_slot()
112 retval = controller->ops->set_power(slot, 1); in enable_slot()
145 if (controller->ops->set_power) { in disable_slot()
146 retval = controller->ops->set_power(slot, 0); in disable_slot()
168 if (controller->ops->get_power) in cpci_get_power_status()
169 power = controller->ops->get_power(slot); in cpci_get_power_status()
233 if (!(controller && bus)) in cpci_hp_register_bus()
344 if ((controller->irq_flags & IRQF_SHARED) && in cpci_hp_intr()
345 !controller->ops->check_irq(controller->dev_id)) { in cpci_hp_intr()
[all …]
|
| D | shpchp_hpc.c | 183 static void start_int_poll_timer(struct controller *ctrl, int sec);
184 static int hpc_check_cmd_status(struct controller *ctrl);
186 static inline u8 shpc_readb(struct controller *ctrl, int reg) in shpc_readb()
191 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) in shpc_writeb()
196 static inline u16 shpc_readw(struct controller *ctrl, int reg) in shpc_readw()
201 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) in shpc_writew()
206 static inline u32 shpc_readl(struct controller *ctrl, int reg) in shpc_readl()
211 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) in shpc_writel()
216 static inline int shpc_indirect_read(struct controller *ctrl, int index, in shpc_indirect_read()
234 struct controller *ctrl = (struct controller *)data; in int_poll_timeout()
[all …]
|
| D | shpchp.h | 86 struct controller *ctrl;
102 struct controller { struct
171 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
172 void shpchp_remove_ctrl_files(struct controller *ctrl);
175 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
176 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
177 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
178 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
181 void cleanup_slots(struct controller *ctrl);
183 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
[all …]
|
| D | pciehp.h | 75 struct controller *ctrl;
89 struct controller { struct
133 struct controller *pcie_init(struct pcie_device *dev);
134 int pcie_init_notification(struct controller *ctrl);
137 void pcie_enable_notification(struct controller *ctrl);
150 int pciehp_check_link_status(struct controller *ctrl);
151 bool pciehp_check_link_active(struct controller *ctrl);
152 void pciehp_release_ctrl(struct controller *ctrl);
|
| /linux-4.4.14/arch/metag/boot/dts/ |
| D | tz1090.dtsi | 11 #include <dt-bindings/interrupt-controller/irq.h>
18 intc: interrupt-controller {
20 interrupt-controller;
32 interrupt-controller;
66 gpio-controller;
67 interrupt-controller;
75 gpio-controller;
76 interrupt-controller;
84 gpio-controller;
85 interrupt-controller;
[all …]
|
| /linux-4.4.14/drivers/usb/core/ |
| D | usb.c | 446 dev->dev.dma_mask = bus->controller->dma_mask; in usb_alloc_dev()
447 set_dev_node(&dev->dev, dev_to_node(bus->controller)); in usb_alloc_dev()
471 dev->dev.parent = bus->controller; in usb_alloc_dev()
782 struct device *controller;
787 || !(controller = bus->controller))
790 if (controller->dma_mask) {
791 urb->transfer_dma = dma_map_single(controller,
819 struct device *controller;
825 || !(controller = bus->controller))
828 if (controller->dma_mask) {
[all …]
|
| D | buffer.c | 65 if (!hcd->self.controller->dma_mask && in hcd_buffer_create()
74 hcd->pool[i] = dma_pool_create(name, hcd->self.controller, in hcd_buffer_create()
122 if (!bus->controller->dma_mask && in hcd_buffer_alloc()
132 return dma_alloc_coherent(hcd->self.controller, size, dma, mem_flags); in hcd_buffer_alloc()
148 if (!bus->controller->dma_mask && in hcd_buffer_free()
160 dma_free_coherent(hcd->self.controller, size, addr, dma); in hcd_buffer_free()
|
| /linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
15 - gpio-controller : Marks the port as GPIO controller.
17 Example of three SOC GPIO banks defined as gpio-controller nodes:
19 CPM1_PIO_A: gpio-controller@950 {
23 gpio-controller;
26 CPM1_PIO_B: gpio-controller@ab8 {
30 gpio-controller;
33 CPM1_PIO_E: gpio-controller@ac8 {
37 gpio-controller;
|
| /linux-4.4.14/Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 1 Marvell Orion/Discovery ethernet controller
4 The Marvell Discovery ethernet controller can be found on Marvell Orion SoCs
6 Discovery system controller chips (mv64[345]60).
8 The Discovery ethernet controller is described with two levels of nodes. The
9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
12 set of controller registers. Each port node describes port-specific properties.
15 For Orion SoCs we stick to the separation, although there each controller has
20 * Ethernet controller node
22 Required controller properties:
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/hisilicon/ |
| D | hisilicon.txt | 27 Hisilicon system controller
45 sysctrl: system-controller@fc802000 {
54 Hisilicon Hi6220 system controller
60 under this controller and this property must be present.
62 Hisilicon designs this controller as one of the system controllers,
63 its main functions are the same as Hisilicon system controller, but
75 Hisilicon Hi6220 Power Always ON domain controller
81 under this controller and this property must be present.
83 Hisilicon designs this system controller to control the power always
95 Hisilicon Hi6220 Media domain controller
[all …]
|
| /linux-4.4.14/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 18 cpuintc: interrupt-controller {
21 interrupt-controller;
47 ddr_ctrl: memory-controller@18000000 {
48 compatible = "qca,ar9132-ddr-controller",
49 "qca,ar7240-ddr-controller";
78 gpio-controller;
81 interrupt-controller;
85 pll: pll-controller@18050000 {
107 miscintc: interrupt-controller@18060010 {
115 interrupt-controller;
[all …]
|
| /linux-4.4.14/arch/arc/boot/dts/ |
| D | abilis_tb101.dtsi | 178 interrupt-controller;
183 gpio-controller;
191 interrupt-controller;
196 gpio-controller;
204 interrupt-controller;
209 gpio-controller;
217 interrupt-controller;
222 gpio-controller;
230 interrupt-controller;
235 gpio-controller;
[all …]
|
| D | abilis_tb100.dtsi | 169 interrupt-controller;
174 gpio-controller;
182 interrupt-controller;
187 gpio-controller;
195 interrupt-controller;
200 gpio-controller;
208 interrupt-controller;
213 gpio-controller;
221 interrupt-controller;
226 gpio-controller;
[all …]
|
| D | axs10x_mb.dtsi | 169 gpio0_banka: gpio-controller@0 {
171 gpio-controller;
177 gpio0_bankb: gpio-controller@1 {
179 gpio-controller;
185 gpio0_bankc: gpio-controller@2 {
187 gpio-controller;
200 gpio1_banka: gpio-controller@0 {
202 gpio-controller;
208 gpio1_bankb: gpio-controller@1 {
210 gpio-controller;
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/mfd/ |
| D | tc3589x.txt | 18 - interrupt-parent : specifies which IRQ controller we're connected to
19 - interrupts : the interrupt on the parent the controller is connected to
20 - interrupt-controller : marks the device node as an interrupt controller
22 TC3589x interrupt controller.
31 - interrupt-controller : marks the device node as an interrupt controller
33 TC3589x GPIO interrupt controller, the second cell is the interrupt flags
34 in accordance with <dt-bindings/interrupt-controller/irq.h>. The following
41 - gpio-controller : marks the device node as a GPIO controller
43 GPIO controller, the second cell is the flags.
69 interrupt-controller;
[all …]
|
| /linux-4.4.14/drivers/pinctrl/nomadik/ |
| D | Kconfig | 11 bool "AB8500 pin controller driver"
15 bool "AB8540 pin controller driver"
19 bool "AB9540 pin controller driver"
23 bool "AB8505 pin controller driver"
31 bool "Nomadik pin controller driver"
40 bool "STN8815 pin controller driver"
44 bool "DB8500 pin controller driver"
48 bool "DB8540 pin controller driver"
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/ |
| D | mvebu-system-controller.txt | 8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
|
| /linux-4.4.14/Documentation/devicetree/bindings/mips/ |
| D | cpu_irq.txt | 1 MIPS CPU interrupt controller
4 IRQs from a devicetree file and create a irq_domain for IRQ controller.
7 platforms internal interrupt controller cascade.
13 - compatible : Should be "mti,cpu-interrupt-controller"
19 interrupt-controller;
22 compatible = "mti,cpu-interrupt-controller";
29 interrupt-controller;
39 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
|
| /linux-4.4.14/Documentation/devicetree/bindings/spmi/ |
| D | qcom,spmi-pmic-arb.txt | 4 controller with wrapping arbitration logic to allow for multiple on-chip
7 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
10 See spmi.txt for the generic SPMI controller binding requirements for child
13 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
14 generic interrupt controller binding documentation.
20 "intr" - interrupt controller registers
32 - interrupts : interrupt list for the PMIC Arb controller, must contain a
37 - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
43 dt-bindings/interrupt-controller/irq.h
63 interrupt-controller;
|
| /linux-4.4.14/Documentation/devicetree/bindings/input/ |
| D | samsung-keypad.txt | 3 Samsung's Keypad controller is used to interface a SoC with a matrix-type
4 keypad device. The keypad controller supports multiple row and column lines.
6 The keypad controller can sense a key-press and key-release and report the
12 controller.
14 controller.
16 - reg: physical base address of the controller and length of memory mapped
23 controller.
26 keypad controller.
29 controller is represented as a child node to the keypad controller
36 - pinctrl-0: Should specify pin control groups used for this controller.
|
| D | st-keyscan.txt | 1 * ST Keyscan controller Device Tree bindings
3 The ST keyscan controller Device Tree binding is based on the
9 - reg: Register base address and size of st-keyscan controller.
11 - interrupts: Interrupt number for the st-keyscan controller.
16 - pinctrl: Should specify pin control groups used for this controller.
22 - keypad,num-rows: Number of row lines connected to the keypad controller.
25 controller.
|
| /linux-4.4.14/arch/c6x/boot/dts/ |
| D | tms320c6457.dtsi | 24 core_pic: interrupt-controller {
25 interrupt-controller;
30 megamod_pic: interrupt-controller@1800000 {
32 interrupt-controller;
38 cache-controller@1840000 {
43 device-state-controller@2880800 {
60 clock-controller@29a0000 {
|
| D | tms320c6474.dtsi | 34 core_pic: interrupt-controller {
35 interrupt-controller;
40 megamod_pic: interrupt-controller@1800000 {
42 interrupt-controller;
48 cache-controller@1840000 {
71 device-state-controller@2880800 {
81 clock-controller@29a0000 {
|
| D | tms320c6455.dtsi | 24 core_pic: interrupt-controller {
25 interrupt-controller;
31 * Megamodule interrupt controller
33 megamod_pic: interrupt-controller@1800000 {
35 interrupt-controller;
41 cache-controller@1840000 {
70 clock-controller@029a0000 {
|
| /linux-4.4.14/Documentation/devicetree/bindings/bus/ |
| D | sunxi-rsb.txt | 1 Allwinner Reduced Serial Bus (RSB) controller
3 The RSB controller found on later Allwinner SoCs is an SMBus like 2 wire
5 for the controller itself, and child nodes representing the slave devices.
9 - reg : Offset and length of the register set for the controller.
11 - interrupts : The interrupt line associated to the RSB controller.
12 - clocks : The gate clk associated to the RSB controller.
13 - resets : The reset line associated to the RSB controller.
24 An RSB controller node can contain zero or more child nodes representing
|
| /linux-4.4.14/Documentation/devicetree/bindings/soc/sunxi/ |
| D | sram.txt | 4 The SRAM controller found on most Allwinner devices is represented by
5 a regular node for the SRAM controller itself, with sub-nodes
6 reprensenting the SRAM handled by the SRAM controller.
12 - compatible : "allwinner,sun4i-a10-sram-controller"
13 - reg : sram controller register offset + length
22 SRAM controller as subnodes. These sections are represented following
32 Some devices need to request to the SRAM controller to map an SRAM for
45 sram-controller@01c00000 {
46 compatible = "allwinner,sun4i-a10-sram-controller";
|
| /linux-4.4.14/Documentation/devicetree/bindings/serial/ |
| D | nxp,sc16is7xx.txt | 13 - interrupt-parent: The phandle for the interrupt controller that
19 - gpio-controller: Marks the device node as a GPIO controller.
32 gpio-controller;
47 - interrupt-parent: The phandle for the interrupt controller that
50 controller. The format of the interrupt specifier depends on the
51 parent interrupt controller.
55 - gpio-controller: Marks the device node as a GPIO controller.
68 gpio-controller;
|
| D | maxim,max310x.txt | 10 - interrupt-parent: The phandle for the interrupt controller that
13 controller. The format of the interrupt specifier depends on the
14 parent interrupt controller.
20 - gpio-controller: Marks the device node as a GPIO controller.
34 gpio-controller;
|
| /linux-4.4.14/Documentation/devicetree/bindings/power/ |
| D | power_domain.txt | 24 the power controller specified by phandle.
34 power: power-controller@12340000 {
35 compatible = "foo,power-controller";
40 The node above defines a power controller that is a PM domain provider and
45 parent: power-controller@12340000 {
46 compatible = "foo,power-controller";
51 child: power-controller@12341000 {
52 compatible = "foo,power-controller";
59 Domains created by the 'child' power controller are subdomains of '0' power
60 domain provided by the 'parent' power controller.
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/dma/ |
| D | ste-dma40.txt | 18 dma: dma-controller@801C0000 {
37 1. A phandle pointing to the DMA controller
62 0: SPI controller 0
63 1: SD/MMC controller 0 (unused)
64 2: SD/MMC controller 1 (unused)
65 3: SD/MMC controller 2 (unused)
90 28: SD/MM controller 2
91 29: SD/MM controller 0
94 32: SD/MM controller 1
95 33: SPI controller 2
[all …]
|
| D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
24 * while DMA controller may not able to distinguish the irq channel
29 pdma: dma-controller@d4000000 {
39 * Dmaengine driver (DMA controller) distinguish irq channel via
42 pdma: dma-controller@d4000000 {
65 adma0: dma-controller@d42a0800 {
73 squ: dma-controller@d42a0800 {
|
| D | dma.txt | 5 controller.
8 * DMA controller
11 - #dma-cells: Must be at least 1. Used to provide DMA controller
16 - dma-channels: Number of DMA channels supported by the controller.
18 controller.
37 devices to the DMA controller. Some SoCs (like TI DRA7x) have more peripherals
38 integrated with DMA requests than what the DMA controller can handle directly.
41 - dma-masters: phandle of the DMA controller or list of phandles for
65 Client drivers should specify the DMA property using a phandle to the controller
66 followed by DMA controller specific data.
[all …]
|
| D | sirfsoc-dma.txt | 1 * CSR SiRFSoC DMA controller
17 dmac0: dma-controller@b00b0000 {
28 channel request line is 9 of the 2nd dma controller, while write channel uses
29 4 of the 2nd dma controller; spi1 read channel request line is 12 of the 1st
30 dma controller, while write channel uses 13 of the 1st dma controller:
|
| /linux-4.4.14/Documentation/devicetree/bindings/pwm/ |
| D | renesas,tpu-pwm.txt | 6 - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
7 - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
8 - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
9 - "renesas,tpu-sh7372": for SH7372 (SH-Mobile AP4) compatible PWM controller.
10 - "renesas,tpu": for generic R-Car TPU PWM controller.
13 controller hardware module.
22 Example: R8A7740 (R-Car A1) TPU controller node
|
| /linux-4.4.14/Documentation/devicetree/bindings/ |
| D | marvell.txt | 4 The Marvell mv64[345]60 series of system controller chips contain
7 the system controller chip itself and each of the peripherals
11 1) The /system-controller node
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
19 controller chip.
23 - ranges : Describes the translation of system controller addresses
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,pericfg.txt | 1 Mediatek pericfg controller
4 The Mediatek pericfg controller provides various clocks and reset
15 The pericfg controller uses the common clk binding from
18 Also it uses the common reset controller binding from
21 dt-bindings/reset-controller/mt*-resets.h
25 pericfg: power-controller@10003000 {
|
| D | mediatek,infracfg.txt | 1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
15 The infracfg controller uses the common clk binding from
18 Also it uses the common reset controller binding from
21 dt-bindings/reset-controller/mt*-resets.h
25 infracfg: power-controller@10001000 {
|
| /linux-4.4.14/drivers/i2c/busses/ |
| D | i2c-designware-pcidrv.c | 184 return dev->controller->clk_khz; in i2c_dw_get_clk_rate_khz()
193 struct dw_pci_controller *controller; in i2c_dw_pci_probe() local
202 controller = &dw_pci_controllers[id->driver_data]; in i2c_dw_pci_probe()
222 dev->controller = controller; in i2c_dw_pci_probe()
227 dev->functionality = controller->functionality | in i2c_dw_pci_probe()
230 dev->master_cfg = controller->bus_cfg; in i2c_dw_pci_probe()
231 if (controller->scl_sda_cfg) { in i2c_dw_pci_probe()
232 cfg = controller->scl_sda_cfg; in i2c_dw_pci_probe()
242 dev->tx_fifo_depth = controller->tx_fifo_depth; in i2c_dw_pci_probe()
243 dev->rx_fifo_depth = controller->rx_fifo_depth; in i2c_dw_pci_probe()
[all …]
|
| /linux-4.4.14/Documentation/ABI/testing/ |
| D | sysfs-class-scsi_host | 6 SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
10 with the first controller, but this association is not
12 the controller index: '0' for the first controller,
24 '1' indicates the feature is enabled, and the controller may
26 means the feature is disabled and the controller may not use
28 controller wide, affecting all configured logical drives on the
29 controller. This file is readable and writable.
|
| D | sysfs-bus-pci-devices-cciss | 6 Y of controller X.
13 drive Y of controller X.
20 drive Y of controller X.
27 Y of controller X.
39 Description: Kicks of a rescan of the controller to discover logical
47 drive Y of controller X.
54 controller X.
61 of controller X.
67 Description: Value of 1 indicates the controller can honor the reset_devices
78 Description: Value of "simple" indicates that the controller has been placed
[all …]
|
| D | sysfs-class-led-flash | 58 * led-over-voltage - flash controller voltage to the flash LED
59 has exceeded the limit specific to the flash controller
63 * controller-over-temperature - the flash controller has
65 * controller-short-circuit - the short circuit protection
66 of the flash controller has been triggered
69 controller
70 * indicator-led-fault - the flash controller has detected
72 * led-under-voltage - flash controller voltage to the flash
75 * controller-under-voltage - the input voltage of the flash
76 controller is below the limit under which strobing the
|
| /linux-4.4.14/Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 6 memory controller - Memory controller
8 L3 - L3 cache controller
23 Required properties for memory controller subnode:
25 - reg : First resource shall be the memory controller unit
27 - memory-controller : Instance number of the memory controller.
33 - pmd-controller : Instance number of the PMD controller.
84 memory-controller = <0>;
90 pmd-controller = <0>;
|
| /linux-4.4.14/drivers/video/fbdev/mmp/hw/ |
| D | Kconfig | 4 bool "mmp display controller hw support"
8 Marvell MMP display hw controller support
9 this controller is used on Marvell PXA910 and
13 bool "mmp display controller spi port"
17 Marvell MMP display hw controller spi port support
|
| /linux-4.4.14/arch/arm64/boot/dts/marvell/ |
| D | berlin4ct.dtsi | 45 #include <dt-bindings/interrupt-controller/arm-gic.h>
127 gic: interrupt-controller@901000 {
130 interrupt-controller;
154 gpio-controller;
158 interrupt-controller;
172 gpio-controller;
176 interrupt-controller;
190 gpio-controller;
194 interrupt-controller;
208 gpio-controller;
[all …]
|
| /linux-4.4.14/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 5 - reg: Physical base address and length of the controller's registers.
6 - interrupts: The interrupt outputs from the controller.
26 - reg: Physical base address and length of the controller's registers.
27 - interrupts: The interrupt outputs from the controller.
39 - reg: Physical base address and length of the controller's registers.
40 - interrupts: The interrupt outputs from the controller.
52 - reg: Physical base address and length of the controller's registers.
53 - interrupts: The interrupt outputs from the controller.
65 - reg: Physical base address and length of the controller's registers.
66 - interrupts: The interrupt outputs from the controller.
[all …]
|
| /linux-4.4.14/drivers/isdn/hardware/eicon/ |
| D | diva.c | 195 pdiva->controller = i + 1; in diva_driver_add_card()
196 pdiva->xdi_adapter.ANum = pdiva->controller; in diva_driver_add_card()
204 pdiva->controller)) in diva_driver_add_card()
211 pa->controller = i + 1 + j; in diva_driver_add_card()
212 pa->xdi_adapter.ANum = pa->controller; in diva_driver_add_card()
216 pa->controller)) in diva_driver_add_card()
310 if (a[i]->controller) { in diva_driver_remove_card()
312 a[i]->controller)) IoAdapters[a[i]->controller - 1] = NULL; in diva_driver_remove_card()
377 if (a->controller) { in divasa_xdi_driver_unload()
378 IoAdapters[a->controller - 1] = NULL; in divasa_xdi_driver_unload()
[all …]
|
| /linux-4.4.14/drivers/pinctrl/spear/ |
| D | Kconfig | 20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
31 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
37 bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
43 bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
53 Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
|
| /linux-4.4.14/Documentation/devicetree/bindings/net/can/ |
| D | microchip,mcp251x.txt | 1 * Microchip MCP251X stand-alone CAN controller device tree bindings
8 - clocks: The clock feeding the CAN controller.
9 - interrupt-parent: The parent interrupt controller.
10 - interrupts: Should contain IRQ line for the CAN controller.
13 - vdd-supply: Regulator that powers the CAN controller.
|
| /linux-4.4.14/drivers/pinctrl/qcom/ |
| D | Kconfig | 11 tristate "Qualcomm APQ8064 pin controller driver"
19 tristate "Qualcomm APQ8084 pin controller driver"
27 tristate "Qualcomm IPQ8064 pin controller driver"
35 tristate "Qualcomm 8660 pin controller driver"
43 tristate "Qualcomm 8960 pin controller driver"
51 tristate "Qualcomm 8x74 pin controller driver"
59 tristate "Qualcomm 8916 pin controller driver"
67 tristate "Qualcomm Technologies QDF2xxx pin controller driver"
75 tristate "Qualcomm SPMI PMIC pin controller driver"
88 tristate "Qualcomm SSBI PMIC pin controller driver"
|
| /linux-4.4.14/Documentation/mtd/ |
| D | spi-nor.txt | 8 controller operates agnostic of the specific device attached. However, some
9 controllers (such as Freescale's QuadSPI controller) cannot easily handle
12 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
16 which the controller driver is aware of the opcodes, addressing, and other
23 With this new layer, the SPI NOR controller driver does not depend on the
47 With the SPI NOR controller driver (Freescale QuadSPI), it looks like:
62 when you want to write a new driver for a SPI NOR controller.
|
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_dpm.c | 796 ATOM_PPLIB_THERMALCONTROLLER *controller; in amdgpu_add_thermal_controller() local
806 controller = &power_table->sThermalController; in amdgpu_add_thermal_controller()
809 if (controller->ucType > 0) { in amdgpu_add_thermal_controller()
810 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) in amdgpu_add_thermal_controller()
813 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; in amdgpu_add_thermal_controller()
815 adev->pm.fan_min_rpm = controller->ucFanMinRPM; in amdgpu_add_thermal_controller()
816 adev->pm.fan_max_rpm = controller->ucFanMaxRPM; in amdgpu_add_thermal_controller()
818 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { in amdgpu_add_thermal_controller()
820 (controller->ucFanParameters & in amdgpu_add_thermal_controller()
823 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { in amdgpu_add_thermal_controller()
[all …]
|
| /linux-4.4.14/drivers/media/platform/marvell-ccic/ |
| D | Kconfig | 11 CMOS camera controller. This is the controller found on first-
15 tristate "Marvell Armada 610 integrated camera controller support"
23 controller found on Marvell Armada 610 application
24 processors (and likely beyond). This is the controller found
|