Lines Matching refs:controller

1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12   directly output an interrupt signal towards the interrupt controller parent,
14   controller, in particular for UARTs
20 - not all bits within the interrupt controller actually map to an interrupt
22 The typical hardware layout for this controller is represented below:
24 2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
56 - interrupt-controller: identifies the node as an interrupt controller
59 - interrupt-parent: specifies the phandle to the parent interrupt controller
61 - interrupts: specifies the interrupt line(s) in the interrupt-parent controller
62   node, valid values depend on the type of parent interrupt controller
64   are wired to this 2nd level interrupt controller, and how they match their
70 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
75   respective interrupt outputs bypass this 2nd level interrupt controller
76   completely; it is completely transparent for the interrupt controller
81 irq0_intc: interrupt-controller@f0406800 {
86 	interrupt-controller;