1* Marvell EBU GPIO controller
2
3Required properties:
4
5- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
6  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
7  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
8  370. "marvell,mv78200-gpio" should be used for the Discovery
9  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
10  SoCs (MV78230, MV78260, MV78460).
11
12- reg: Address and length of the register set for the device. Only one
13  entry is expected, except for the "marvell,armadaxp-gpio" variant
14  for which two entries are expected: one for the general registers,
15  one for the per-cpu registers.
16
17- interrupts: The list of interrupts that are used for all the pins
18  managed by this GPIO bank. There can be more than one interrupt
19  (example: 1 interrupt per 8 pins on Armada XP, which means 4
20  interrupts per bank of 32 GPIOs).
21
22- interrupt-controller: identifies the node as an interrupt controller
23
24- #interrupt-cells: specifies the number of cells needed to encode an
25  interrupt source. Should be two.
26  The first cell is the GPIO number.
27  The second cell is used to specify flags:
28    bits[3:0] trigger type and level flags:
29      1 = low-to-high edge triggered.
30      2 = high-to-low edge triggered.
31      4 = active high level-sensitive.
32      8 = active low level-sensitive.
33
34- gpio-controller: marks the device node as a gpio controller
35
36- ngpios: number of GPIOs this controller has
37
38- #gpio-cells: Should be two. The first cell is the pin number. The
39  second cell is reserved for flags, unused at the moment.
40
41Example:
42
43		gpio0: gpio@d0018100 {
44			compatible = "marvell,armadaxp-gpio";
45			reg = <0xd0018100 0x40>,
46			    <0xd0018800 0x30>;
47			ngpios = <32>;
48			gpio-controller;
49			#gpio-cells = <2>;
50			interrupt-controller;
51			#interrupt-cells = <2>;
52			interrupts = <16>, <17>, <18>, <19>;
53		};
54