Lines Matching refs:controller

12 	gpio-phandle : phandle to gpio controller node
14 			 (controller specific)
36 		gpio-controller
40 		gpio-controller
51 Note that gpio-specifier length is controller dependent.  In the
58 Exact meaning of each specifier cell is controller specific, and must
72 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
91 GPIO controller that achieves (or represents, for inputs) a logically asserted
94 the GPIO controller and the device, then the gpio-specifier will represent the
121 (at the GPIO controller) assuming that the device is configured for this
125 controller.
127 2) gpio-controller nodes
130 Every GPIO controller node must contain both an empty "gpio-controller"
134 Optionally, a GPIO controller may have a "ngpios" property. This property
150 gpio-controller@00000000 {
153 	gpio-controller;
160 gpio-controller's driver probe function.
162 Each GPIO hog definition is represented as a child node of the GPIO controller.
166 	      number of cells specified in its parent node (GPIO controller
181 Example of two SOC GPIO banks defined as gpio-controller nodes:
183 	qe_pio_a: gpio-controller@1400 {
186 		gpio-controller;
197 	qe_pio_e: gpio-controller@1460 {
200 		gpio-controller;
204 2.1) gpio- and pin-controller interaction
207 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
208 on the package via a pin controller. This allows muxing those pins between
220 	pinctrl-phandle : phandle to pin controller node
221 	gpio-base : Base GPIO ID in the GPIO controller
222 	pinctrl-base : Base pinctrl pin ID in the pin controller
225 The "pin controller node" mentioned above must conform to the bindings
233 			the respective pin controller.
238 controller. The number of pins/GPIOs in the range is the number of pins in
241 Previous versions of this binding required all pin controller nodes that
250 	qe_pio_e: gpio-controller@1460 {
254 		gpio-controller;
258 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
259 pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
264 	gpio_pio_i: gpio-controller@14B0 {
268 		gpio-controller;