Lines Matching refs:controller

1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
14     the brcmstb GPIO controller registers
17     Should be <2>.  The first cell is the pin number (within the controller's
21 - gpio-controller:
22     Specifies that the node is a GPIO controller.
31     The interrupt shared by all GPIO lines for this controller.
34     phandle of the parent interrupt controller
40     wakeup interrupt lines through a different interrupt controller than the
52     See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
54 - interrupt-controller:
55     Marks the device node as an interrupt controller
58     GPIOs for this controller can be used as a wakeup source
65 		gpio-controller;
66 		interrupt-controller;
77 		gpio-controller;
78 		interrupt-controller;