158 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)  in spi_qup_is_valid_state()  argument
160 	u32 opstate = readl_relaxed(controller->base + QUP_STATE);  in spi_qup_is_valid_state()
165 static int spi_qup_set_state(struct spi_qup *controller, u32 state)  in spi_qup_set_state()  argument
171 	while (!spi_qup_is_valid_state(controller)) {  in spi_qup_set_state()
180 		dev_dbg(controller->dev, "invalid state for %ld,us %d\n",  in spi_qup_set_state()
183 	cur_state = readl_relaxed(controller->base + QUP_STATE);  in spi_qup_set_state()
190 		writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);  in spi_qup_set_state()
191 		writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);  in spi_qup_set_state()
195 		writel_relaxed(cur_state, controller->base + QUP_STATE);  in spi_qup_set_state()
199 	while (!spi_qup_is_valid_state(controller)) {  in spi_qup_set_state()
210 static void spi_qup_fifo_read(struct spi_qup *controller,  in spi_qup_fifo_read()  argument
217 	w_size = controller->w_size;  in spi_qup_fifo_read()
219 	while (controller->rx_bytes < xfer->len) {  in spi_qup_fifo_read()
221 		state = readl_relaxed(controller->base + QUP_OPERATIONAL);  in spi_qup_fifo_read()
225 		word = readl_relaxed(controller->base + QUP_INPUT_FIFO);  in spi_qup_fifo_read()
228 			controller->rx_bytes += w_size;  in spi_qup_fifo_read()
232 		for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) {  in spi_qup_fifo_read()
241 			rx_buf[controller->rx_bytes] = word >> shift;  in spi_qup_fifo_read()
246 static void spi_qup_fifo_write(struct spi_qup *controller,  in spi_qup_fifo_write()  argument
253 	w_size = controller->w_size;  in spi_qup_fifo_write()
255 	while (controller->tx_bytes < xfer->len) {  in spi_qup_fifo_write()
257 		state = readl_relaxed(controller->base + QUP_OPERATIONAL);  in spi_qup_fifo_write()
262 		for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {  in spi_qup_fifo_write()
265 				controller->tx_bytes += w_size;  in spi_qup_fifo_write()
269 			data = tx_buf[controller->tx_bytes];  in spi_qup_fifo_write()
273 		writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);  in spi_qup_fifo_write()
380 	struct spi_qup *controller = dev_id;  in spi_qup_qup_irq()  local
386 	spin_lock_irqsave(&controller->lock, flags);  in spi_qup_qup_irq()
387 	xfer = controller->xfer;  in spi_qup_qup_irq()
388 	controller->xfer = NULL;  in spi_qup_qup_irq()
389 	spin_unlock_irqrestore(&controller->lock, flags);  in spi_qup_qup_irq()
391 	qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);  in spi_qup_qup_irq()
392 	spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);  in spi_qup_qup_irq()
393 	opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);  in spi_qup_qup_irq()
395 	writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);  in spi_qup_qup_irq()
396 	writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);  in spi_qup_qup_irq()
397 	writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);  in spi_qup_qup_irq()
400 		dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",  in spi_qup_qup_irq()
407 			dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");  in spi_qup_qup_irq()
409 			dev_warn(controller->dev, "INPUT_UNDER_RUN\n");  in spi_qup_qup_irq()
411 			dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");  in spi_qup_qup_irq()
413 			dev_warn(controller->dev, "INPUT_OVER_RUN\n");  in spi_qup_qup_irq()
420 			dev_warn(controller->dev, "CLK_OVER_RUN\n");  in spi_qup_qup_irq()
422 			dev_warn(controller->dev, "CLK_UNDER_RUN\n");  in spi_qup_qup_irq()
427 	if (!controller->use_dma) {  in spi_qup_qup_irq()
429 			spi_qup_fifo_read(controller, xfer);  in spi_qup_qup_irq()
432 			spi_qup_fifo_write(controller, xfer);  in spi_qup_qup_irq()
435 	spin_lock_irqsave(&controller->lock, flags);  in spi_qup_qup_irq()
436 	controller->error = error;  in spi_qup_qup_irq()
437 	controller->xfer = xfer;  in spi_qup_qup_irq()
438 	spin_unlock_irqrestore(&controller->lock, flags);  in spi_qup_qup_irq()
440 	if (controller->rx_bytes == xfer->len || error)  in spi_qup_qup_irq()
441 		complete(&controller->done);  in spi_qup_qup_irq()
472 	struct spi_qup *controller = spi_master_get_devdata(spi->master);  in spi_qup_io_config()  local
476 	if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {  in spi_qup_io_config()
477 		dev_err(controller->dev, "too big size for loopback %d > %d\n",  in spi_qup_io_config()
478 			xfer->len, controller->in_fifo_sz);  in spi_qup_io_config()
482 	ret = clk_set_rate(controller->cclk, xfer->speed_hz);  in spi_qup_io_config()
484 		dev_err(controller->dev, "fail to set frequency %d",  in spi_qup_io_config()
489 	if (spi_qup_set_state(controller, QUP_STATE_RESET)) {  in spi_qup_io_config()
490 		dev_err(controller->dev, "cannot set RESET state\n");  in spi_qup_io_config()
495 	n_words = controller->n_words;  in spi_qup_io_config()
498 		writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);  in spi_qup_io_config()
499 		writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);  in spi_qup_io_config()
501 		writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);  in spi_qup_io_config()
502 		writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);  in spi_qup_io_config()
503 	} else if (!controller->use_dma) {  in spi_qup_io_config()
504 		writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);  in spi_qup_io_config()
505 		writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);  in spi_qup_io_config()
507 		writel_relaxed(0, controller->base + QUP_MX_READ_CNT);  in spi_qup_io_config()
508 		writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);  in spi_qup_io_config()
511 		writel_relaxed(0, controller->base + QUP_MX_READ_CNT);  in spi_qup_io_config()
512 		writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);  in spi_qup_io_config()
514 		if (!controller->qup_v1) {  in spi_qup_io_config()
517 			input_cnt = controller->base + QUP_MX_INPUT_CNT;  in spi_qup_io_config()
529 			writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);  in spi_qup_io_config()
533 	iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);  in spi_qup_io_config()
537 	if (!controller->use_dma)  in spi_qup_io_config()
545 	writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);  in spi_qup_io_config()
547 	control = readl_relaxed(controller->base + SPI_IO_CONTROL);  in spi_qup_io_config()
554 	writel_relaxed(control, controller->base + SPI_IO_CONTROL);  in spi_qup_io_config()
556 	config = readl_relaxed(controller->base + SPI_CONFIG);  in spi_qup_io_config()
577 	writel_relaxed(config, controller->base + SPI_CONFIG);  in spi_qup_io_config()
579 	config = readl_relaxed(controller->base + QUP_CONFIG);  in spi_qup_io_config()
584 	if (controller->use_dma) {  in spi_qup_io_config()
591 	writel_relaxed(config, controller->base + QUP_CONFIG);  in spi_qup_io_config()
594 	if (!controller->qup_v1) {  in spi_qup_io_config()
605 		writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);  in spi_qup_io_config()
615 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_transfer_one()  local
627 	reinit_completion(&controller->done);  in spi_qup_transfer_one()
629 	spin_lock_irqsave(&controller->lock, flags);  in spi_qup_transfer_one()
630 	controller->xfer     = xfer;  in spi_qup_transfer_one()
631 	controller->error    = 0;  in spi_qup_transfer_one()
632 	controller->rx_bytes = 0;  in spi_qup_transfer_one()
633 	controller->tx_bytes = 0;  in spi_qup_transfer_one()
634 	spin_unlock_irqrestore(&controller->lock, flags);  in spi_qup_transfer_one()
636 	if (controller->use_dma)  in spi_qup_transfer_one()
644 	if (spi_qup_set_state(controller, QUP_STATE_RUN)) {  in spi_qup_transfer_one()
645 		dev_warn(controller->dev, "cannot set EXECUTE state\n");  in spi_qup_transfer_one()
649 	if (!wait_for_completion_timeout(&controller->done, timeout))  in spi_qup_transfer_one()
653 	spi_qup_set_state(controller, QUP_STATE_RESET);  in spi_qup_transfer_one()
654 	spin_lock_irqsave(&controller->lock, flags);  in spi_qup_transfer_one()
655 	controller->xfer = NULL;  in spi_qup_transfer_one()
657 		ret = controller->error;  in spi_qup_transfer_one()
658 	spin_unlock_irqrestore(&controller->lock, flags);  in spi_qup_transfer_one()
660 	if (ret && controller->use_dma)  in spi_qup_transfer_one()
757 	struct spi_qup *controller;  in spi_qup_probe()  local
831 	controller = spi_master_get_devdata(master);  in spi_qup_probe()
833 	controller->dev = dev;  in spi_qup_probe()
834 	controller->base = base;  in spi_qup_probe()
835 	controller->iclk = iclk;  in spi_qup_probe()
836 	controller->cclk = cclk;  in spi_qup_probe()
837 	controller->irq = irq;  in spi_qup_probe()
847 		controller->qup_v1 = 1;  in spi_qup_probe()
849 	spin_lock_init(&controller->lock);  in spi_qup_probe()
850 	init_completion(&controller->done);  in spi_qup_probe()
856 		controller->out_blk_sz = size * 16;  in spi_qup_probe()
858 		controller->out_blk_sz = 4;  in spi_qup_probe()
862 		controller->in_blk_sz = size * 16;  in spi_qup_probe()
864 		controller->in_blk_sz = 4;  in spi_qup_probe()
867 	controller->out_fifo_sz = controller->out_blk_sz * (2 << size);  in spi_qup_probe()
870 	controller->in_fifo_sz = controller->in_blk_sz * (2 << size);  in spi_qup_probe()
873 		 controller->in_blk_sz, controller->in_fifo_sz,  in spi_qup_probe()
874 		 controller->out_blk_sz, controller->out_fifo_sz);  in spi_qup_probe()
878 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);  in spi_qup_probe()
887 	if (!controller->qup_v1)  in spi_qup_probe()
894 	if (controller->qup_v1)  in spi_qup_probe()
903 			       IRQF_TRIGGER_HIGH, pdev->name, controller);  in spi_qup_probe()
933 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_pm_suspend_runtime()  local
937 	config = readl(controller->base + QUP_CONFIG);  in spi_qup_pm_suspend_runtime()
939 	writel_relaxed(config, controller->base + QUP_CONFIG);  in spi_qup_pm_suspend_runtime()
946 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_pm_resume_runtime()  local
950 	config = readl_relaxed(controller->base + QUP_CONFIG);  in spi_qup_pm_resume_runtime()
952 	writel_relaxed(config, controller->base + QUP_CONFIG);  in spi_qup_pm_resume_runtime()
961 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_suspend()  local
968 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);  in spi_qup_suspend()
972 	clk_disable_unprepare(controller->cclk);  in spi_qup_suspend()
973 	clk_disable_unprepare(controller->iclk);  in spi_qup_suspend()
980 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_resume()  local
983 	ret = clk_prepare_enable(controller->iclk);  in spi_qup_resume()
987 	ret = clk_prepare_enable(controller->cclk);  in spi_qup_resume()
991 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);  in spi_qup_resume()
1002 	struct spi_qup *controller = spi_master_get_devdata(master);  in spi_qup_remove()  local
1009 	ret = spi_qup_set_state(controller, QUP_STATE_RESET);  in spi_qup_remove()
1015 	clk_disable_unprepare(controller->cclk);  in spi_qup_remove()
1016 	clk_disable_unprepare(controller->iclk);  in spi_qup_remove()