Searched refs:WR (Results 1 - 171 of 171) sorted by relevance

/linux-4.4.14/drivers/isdn/hisax/
H A Dipacx.h17 #define IPACX_XFIFOD 0x00 /* WR */
19 #define IPACX_MASKD 0x20 /* WR */
21 #define IPACX_CMDRD 0x21 /* WR */
22 #define IPACX_MODED 0x22 /* RD/WR */
23 #define IPACX_EXMD1 0x23 /* RD/WR */
24 #define IPACX_TIMR1 0x24 /* RD/WR */
25 #define IPACX_SAP1 0x25 /* WR */
26 #define IPACX_SAP2 0x26 /* WR */
29 #define IPACX_TEI1 0x27 /* WR */
30 #define IPACX_TEI2 0x28 /* WR */
32 #define IPACX_TMD 0x29 /* RD/WR */
34 #define IPACX_CIX0 0x2E /* WR */
36 #define IPACX_CIX1 0x2F /* WR */
39 #define IPACX_TR_CONF0 0x30 /* RD/WR */
40 #define IPACX_TR_CONF1 0x31 /* RD/WR */
41 #define IPACX_TR_CONF2 0x32 /* RD/WR */
43 #define IPACX_TR_CMD 0x34 /* RD/WR */
45 #define IPACX_SQXR1 0x35 /* WR */
47 #define IPACX_SQXR2 0x36 /* WR */
49 #define IPACX_SQXR3 0x37 /* WR */
51 #define IPACX_MASKTR 0x39 /* RD/WR */
52 #define IPACX_TR_MODE 0x3A /* RD/WR */
53 #define IPACX_ACFG1 0x3C /* RD/WR */
54 #define IPACX_ACFG2 0x3D /* RD/WR */
55 #define IPACX_AOE 0x3E /* RD/WR */
57 #define IPACX_ATX 0x3F /* WR */
60 #define IPACX_CDA10 0x40 /* RD/WR */
61 #define IPACX_CDA11 0x41 /* RD/WR */
62 #define IPACX_CDA20 0x42 /* RD/WR */
63 #define IPACX_CDA21 0x43 /* RD/WR */
64 #define IPACX_CDA_TSDP10 0x44 /* RD/WR */
65 #define IPACX_CDA_TSDP11 0x45 /* RD/WR */
66 #define IPACX_CDA_TSDP20 0x46 /* RD/WR */
67 #define IPACX_CDA_TSDP21 0x47 /* RD/WR */
68 #define IPACX_BCHA_TSDP_BC1 0x48 /* RD/WR */
69 #define IPACX_BCHA_TSDP_BC2 0x49 /* RD/WR */
70 #define IPACX_BCHB_TSDP_BC1 0x4A /* RD/WR */
71 #define IPACX_BCHB_TSDP_BC2 0x4B /* RD/WR */
72 #define IPACX_TR_TSDP_BC1 0x4C /* RD/WR */
73 #define IPACX_TR_TSDP_BC2 0x4D /* RD/WR */
74 #define IPACX_CDA1_CR 0x4E /* RD/WR */
75 #define IPACX_CDA2_CR 0x4F /* RD/WR */
78 #define IPACX_TR_CR 0x50 /* RD/WR */
79 #define IPACX_TRC_CR 0x50 /* RD/WR */
80 #define IPACX_BCHA_CR 0x51 /* RD/WR */
81 #define IPACX_BCHB_CR 0x52 /* RD/WR */
82 #define IPACX_DCI_CR 0x53 /* RD/WR */
83 #define IPACX_DCIC_CR 0x53 /* RD/WR */
84 #define IPACX_MON_CR 0x54 /* RD/WR */
85 #define IPACX_SDS1_CR 0x55 /* RD/WR */
86 #define IPACX_SDS2_CR 0x56 /* RD/WR */
87 #define IPACX_IOM_CR 0x57 /* RD/WR */
89 #define IPACX_ASTI 0x58 /* WR */
90 #define IPACX_MSTI 0x59 /* RD/WR */
91 #define IPACX_SDS_CONF 0x5A /* RD/WR */
94 #define IPACX_MOX 0x5C /* WR */
96 #define IPACX_MOCR 0x5E /* RD/WR */
98 #define IPACX_MCONF 0x5F /* WR */
102 #define IPACX_MASK 0x60 /* WR */
104 #define IPACX_AUXM 0x61 /* WR */
105 #define IPACX_MODE1 0x62 /* RD/WR */
106 #define IPACX_MODE2 0x63 /* RD/WR */
108 #define IPACX_SRES 0x64 /* WR */
109 #define IPACX_TIMR2 0x65 /* RD/WR */
116 #define IPACX_MASKB 0x00 /* WR */
118 #define IPACX_CMDRB 0x01 /* WR */
119 #define IPACX_MODEB 0x02 /* RD/WR */
120 #define IPACX_EXMB 0x03 /* RD/WR */
121 #define IPACX_RAH1 0x05 /* WR */
122 #define IPACX_RAH2 0x06 /* WR */
125 #define IPACX_RAL1 0x07 /* WR */
126 #define IPACX_RAL2 0x08 /* WR */
128 #define IPACX_TMB 0x09 /* RD/WR */
130 #define IPACX_XFIFOB 0x0A /*- WR */
/linux-4.4.14/drivers/block/paride/
H A Dbpck.c105 #define WR(r,v) bpck_write_regr(pi,2,r,v) macro
114 case 0: WR(4,0x40); bpck_write_block()
117 WR(4,0); bpck_write_block()
120 case 1: WR(4,0x50); bpck_write_block()
123 WR(4,0x10); bpck_write_block()
126 case 2: WR(4,0x48); bpck_write_block()
130 WR(4,8); bpck_write_block()
133 case 3: WR(4,0x48); bpck_write_block()
137 WR(4,8); bpck_write_block()
140 case 4: WR(4,0x48); bpck_write_block()
144 WR(4,8); bpck_write_block()
155 case 0: WR(4,0x40); bpck_read_block()
162 WR(4,0); bpck_read_block()
165 case 1: WR(4,0x50); bpck_read_block()
169 WR(4,0x10); bpck_read_block()
172 case 2: WR(4,0x48); bpck_read_block()
176 WR(4,8); bpck_read_block()
179 case 3: WR(4,0x48); bpck_read_block()
183 WR(4,8); bpck_read_block()
186 case 4: WR(4,0x48); bpck_read_block()
190 WR(4,8); bpck_read_block()
228 case 0: t2(8); WR(4,0); bpck_connect()
231 case 1: t2(8); WR(4,0x10); bpck_connect()
236 case 4: w2(0); WR(4,8); bpck_connect()
241 WR(5,8); bpck_connect()
244 WR(0x46,0x10); /* fiddle with ESS logic ??? */ bpck_connect()
245 WR(0x4c,0x38); bpck_connect()
246 WR(0x4d,0x88); bpck_connect()
247 WR(0x46,0xa0); bpck_connect()
248 WR(0x41,0); bpck_connect()
249 WR(0x4e,8); bpck_connect()
288 WR(0x13,0x7f); bpck_test_proto()
299 WR(0x13,0x7f); bpck_test_proto()
311 WR(7,3); bpck_test_proto()
312 WR(4,8); bpck_test_proto()
329 WR(7,0); bpck_test_proto()
360 WR(4,0); bpck_read_eeprom()
362 WR(6,8); bpck_read_eeprom()
363 WR(6,0xc); bpck_read_eeprom()
367 WR(6,f+0xc); bpck_read_eeprom()
368 WR(6,f+0xd); bpck_read_eeprom()
369 WR(6,f+0xc); bpck_read_eeprom()
375 WR(6,0xc); bpck_read_eeprom()
376 WR(6,0xd); bpck_read_eeprom()
377 WR(6,0xc); bpck_read_eeprom()
384 WR(6,8); bpck_read_eeprom()
385 WR(6,0); bpck_read_eeprom()
386 WR(5,8); bpck_read_eeprom()
392 WR(7,3); bpck_read_eeprom()
393 WR(4,8); bpck_read_eeprom()
H A Depia.c104 #define WR(r,v) epia_write_regr(pi,0,r,v) macro
124 WR(0x86,8); epia_connect()
129 { /* WR(0x84,0x10); */ epia_disconnect()
175 case 3: if (count > 512) WR(0x84,3); epia_read_block()
178 w2(4); WR(0x84,0); epia_read_block()
181 case 4: if (count > 512) WR(0x84,3); epia_read_block()
184 w2(4); WR(0x84,0); epia_read_block()
187 case 5: if (count > 512) WR(0x84,3); epia_read_block()
190 w2(4); WR(0x84,0); epia_read_block()
215 case 3: if (count < 512) WR(0x84,1); epia_write_block()
218 if (count < 512) WR(0x84,0); epia_write_block()
221 case 4: if (count < 512) WR(0x84,1); epia_write_block()
224 if (count < 512) WR(0x84,0); epia_write_block()
227 case 5: if (count < 512) WR(0x84,1); epia_write_block()
230 if (count < 512) WR(0x84,0); epia_write_block()
244 WR(6,0xa0+j*0x10); epia_test_proto()
246 WR(2,k^0xaa); epia_test_proto()
247 WR(3,k^0x55); epia_test_proto()
250 WR(2,1); WR(3,1); epia_test_proto()
256 WR(0x84,8); epia_test_proto()
262 WR(0x84,0); epia_test_proto()
H A Depat.c200 #define WR(r,v) epat_write_regr(pi,2,r,v) macro
224 WR(0x8,0x12);WR(0xc,0x14);WR(0x12,0x10); epat_connect()
225 WR(0xe,0xf);WR(0xf,4); epat_connect()
226 /* WR(0xe,0xa);WR(0xf,4); */ epat_connect()
227 WR(0xe,0xd);WR(0xf,0); epat_connect()
241 WR(8,0x10); WR(0xc,0x14); WR(0xa,0x38); WR(0x12,0x10); epat_connect()
273 WR(0x13,1); WR(0x13,0); WR(0xa,0x11); epat_test_proto()
297 WR(0xa,0x38); /* read the version code */ epat_log_adapter()
/linux-4.4.14/drivers/isdn/hardware/mISDN/
H A Dipac.h135 #define IPAC_MASKB 0x20 /* WR */
137 #define IPAC_CMDRB 0x21 /* WR */
141 #define IPAC_RAH1 0x26 /* WR */
142 #define IPAC_RAH2 0x27 /* WR */
145 #define IPAC_RAL2 0x29 /* WR */
147 #define IPAC_XBCL 0x2A /* WR */
150 #define IPAC_XBCH 0x2D /* WR */
152 #define IPAC_RLCR 0x2E /* WR */
154 #define IPAC_TSAX 0x30 /* WR */
155 #define IPAC_TSAR 0x31 /* WR */
156 #define IPAC_XCCR 0x32 /* WR */
157 #define IPAC_RCCR 0x33 /* WR */
174 #define IPAC_MASK 0xC1 /* WR */
179 #define IPAC_ATX 0xC5 /* WR */
232 #define ISACX_XFIFOD 0x00 /* WR */
234 #define ISACX_MASKD 0x20 /* WR */
236 #define ISACX_CMDRD 0x21 /* WR */
240 #define ISACX_SAP1 0x25 /* WR */
241 #define ISACX_SAP2 0x26 /* WR */
244 #define ISACX_TEI1 0x27 /* WR */
245 #define ISACX_TEI2 0x28 /* WR */
249 #define ISACX_CIX0 0x2E /* WR */
251 #define ISACX_CIX1 0x2F /* WR */
260 #define ISACX_SQXR1 0x35 /* WR */
262 #define ISACX_SQXR2 0x36 /* WR */
264 #define ISACX_SQXR3 0x37 /* WR */
272 #define ISACX_ATX 0x3F /* WR */
304 #define ISACX_ASTI 0x58 /* WR */
309 #define ISACX_MOX 0x5C /* WR */
313 #define ISACX_MCONF 0x5F /* WR */
317 #define ISACX_MASK 0x60 /* WR */
319 #define ISACX_AUXM 0x61 /* WR */
323 #define ISACX_SRES 0x64 /* WR */
377 #define IPACX_MASKB 0x00 /* WR */
379 #define IPACX_CMDRB 0x01 /* WR */
382 #define IPACX_RAH1 0x05 /* WR */
383 #define IPACX_RAH2 0x06 /* WR */
386 #define IPACX_RAL1 0x07 /* WR */
387 #define IPACX_RAL2 0x08 /* WR */
391 #define IPACX_XFIFOB 0x0A /* WR */
/linux-4.4.14/drivers/staging/dgnc/
H A Ddgnc_neo.h31 u8 txrx; /* WR RHR/THR - Holding Reg */
32 u8 ier; /* WR IER - Interrupt Enable Reg */
33 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
34 u8 lcr; /* WR LCR - Line Control Reg */
35 u8 mcr; /* WR MCR - Modem Control Reg */
36 u8 lsr; /* WR LSR - Line Status Reg */
37 u8 msr; /* WR MSR - Modem Status Reg */
38 u8 spr; /* WR SPR - Scratch Pad Reg */
39 u8 fctr; /* WR FCTR - Feature Control Reg */
40 u8 efr; /* WR EFR - Enhanced Function Reg */
41 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
42 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
43 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
44 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
45 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
46 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
H A Ddgnc_cls.h29 * txrx : WR RHR/THR - Holding reg
30 * ier : WR IER - Interrupt Enable Reg
31 * isr_fcr : WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg
32 * lcr : WR LCR - Line Control Reg
33 * mcr : WR MCR - Modem Control Reg
34 * lsr : WR LSR - Line Status Reg
35 * msr : WR MSG - Modem Status Reg
36 * spr : WR SPR - Scratch pad Reg
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-au1550.c53 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) WR() function
114 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); do_address()
117 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); do_address()
133 WR(adap, PSC_SMBTXRX, addr); do_address()
134 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); do_address()
178 WR(adap, PSC_SMBTXRX, 0); i2c_read()
186 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); i2c_read()
206 WR(adap, PSC_SMBTXRX, data); i2c_write()
215 WR(adap, PSC_SMBTXRX, data); i2c_write()
228 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); au1550_xfer()
247 WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); au1550_xfer()
266 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); i2c_au1550_setup()
267 WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); i2c_au1550_setup()
268 WR(priv, PSC_SMBCFG, 0); i2c_au1550_setup()
269 WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); i2c_au1550_setup()
274 WR(priv, PSC_SMBCFG, cfg); i2c_au1550_setup()
280 WR(priv, PSC_SMBCFG, cfg); i2c_au1550_setup()
281 WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); i2c_au1550_setup()
286 WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \ i2c_au1550_setup()
292 WR(priv, PSC_SMBCFG, cfg); i2c_au1550_setup()
296 WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); i2c_au1550_setup()
301 WR(priv, PSC_SMBCFG, 0); i2c_au1550_disable()
302 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); i2c_au1550_disable()
H A Di2c-brcmstb.c102 [CMD_WR] = "WR",
104 [CMD_WR_NOACK] = "WR NOACK",
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; nvkm_gddr3_calc() local
79 WR = ram->next->bios.timing_10_WR; nvkm_gddr3_calc()
87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_gddr3_calc()
103 WR = ramxlat(ramgddr3_wr_lo, WR); nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) nvkm_gddr3_calc()
115 ram->mr[1] |= (WR & 0x03) << 4; nvkm_gddr3_calc()
116 ram->mr[1] |= (WR & 0x04) << 5; nvkm_gddr3_calc()
H A Dsddr2.c62 int CL, WR, DLL = 0, ODT = 0; nvkm_sddr2_calc() local
67 WR = ram->next->bios.timing_10_WR; nvkm_sddr2_calc()
73 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_sddr2_calc()
86 WR = ramxlat(ramddr2_wr, WR); nvkm_sddr2_calc()
87 if (CL < 0 || WR < 0) nvkm_sddr2_calc()
91 ram->mr[0] |= (WR & 0x07) << 9; nvkm_sddr2_calc()
H A Dsddr3.c71 int CWL, CL, WR, DLL = 0, ODT = 0; nvkm_sddr3_calc() local
83 WR = ram->next->bios.timing_10_WR; nvkm_sddr3_calc()
89 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_sddr3_calc()
101 WR = ramxlat(ramddr3_wr, WR); nvkm_sddr3_calc()
102 if (CL < 0 || CWL < 0 || WR < 0) nvkm_sddr3_calc()
106 ram->mr[0] |= (WR & 0x07) << 9; nvkm_sddr3_calc()
H A Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; nvkm_gddr5_calc() local
60 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) nvkm_gddr5_calc()
73 WR -= 4; nvkm_gddr5_calc()
76 ram->mr[0] |= (WR & 0x0f) << 8; nvkm_gddr5_calc()
118 ram->mr[8] |= (WR & 0x10) >> 3; nvkm_gddr5_calc()
H A Dramnv50.c110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | nv50_ram_timing_calc()
177 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); nv50_ram_timing_read()
H A Dramgt215.c375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | gt215_ram_timing_calc()
/linux-4.4.14/include/linux/ceph/
H A Drados.h216 f(WRITE, __CEPH_OSD_OP(WR, DATA, 1), "write") \
217 f(WRITEFULL, __CEPH_OSD_OP(WR, DATA, 2), "writefull") \
218 f(TRUNCATE, __CEPH_OSD_OP(WR, DATA, 3), "truncate") \
219 f(ZERO, __CEPH_OSD_OP(WR, DATA, 4), "zero") \
220 f(DELETE, __CEPH_OSD_OP(WR, DATA, 5), "delete") \
223 f(APPEND, __CEPH_OSD_OP(WR, DATA, 6), "append") \
224 f(STARTSYNC, __CEPH_OSD_OP(WR, DATA, 7), "startsync") \
225 f(SETTRUNC, __CEPH_OSD_OP(WR, DATA, 8), "settrunc") \
226 f(TRIMTRUNC, __CEPH_OSD_OP(WR, DATA, 9), "trimtrunc") \
229 f(TMAPPUT, __CEPH_OSD_OP(WR, DATA, 11), "tmapput") \
232 f(CREATE, __CEPH_OSD_OP(WR, DATA, 13), "create") \
233 f(ROLLBACK, __CEPH_OSD_OP(WR, DATA, 14), "rollback") \
235 f(WATCH, __CEPH_OSD_OP(WR, DATA, 15), "watch") \
242 f(OMAPSETVALS, __CEPH_OSD_OP(WR, DATA, 21), "omap-set-vals") \
243 f(OMAPSETHEADER, __CEPH_OSD_OP(WR, DATA, 22), "omap-set-header") \
244 f(OMAPCLEAR, __CEPH_OSD_OP(WR, DATA, 23), "omap-clear") \
245 f(OMAPRMKEYS, __CEPH_OSD_OP(WR, DATA, 24), "omap-rm-keys") \
249 f(COPY_FROM, __CEPH_OSD_OP(WR, DATA, 26), "copy-from") \
251 f(UNDIRTY, __CEPH_OSD_OP(WR, DATA, 28), "undirty") \
262 f(SETALLOCHINT, __CEPH_OSD_OP(WR, DATA, 35), "set-alloc-hint") \
265 f(CLONERANGE, __CEPH_OSD_OP(WR, MULTI, 1), "clonerange") \
276 f(SETXATTR, __CEPH_OSD_OP(WR, ATTR, 1), "setxattr") \
277 f(SETXATTRS, __CEPH_OSD_OP(WR, ATTR, 2), "setxattrs") \
278 f(RESETXATTRS, __CEPH_OSD_OP(WR, ATTR, 3), "resetxattrs") \
279 f(RMXATTR, __CEPH_OSD_OP(WR, ATTR, 4), "rmxattr") \
293 f(WRLOCK, __CEPH_OSD_OP(WR, LOCK, 1), "wrlock") \
294 f(WRUNLOCK, __CEPH_OSD_OP(WR, LOCK, 2), "wrunlock") \
295 f(RDLOCK, __CEPH_OSD_OP(WR, LOCK, 3), "rdlock") \
296 f(RDUNLOCK, __CEPH_OSD_OP(WR, LOCK, 4), "rdunlock") \
297 f(UPLOCK, __CEPH_OSD_OP(WR, LOCK, 5), "uplock") \
298 f(DNLOCK, __CEPH_OSD_OP(WR, LOCK, 6), "dnlock") \
H A Dceph_fs.h515 #define CEPH_FILE_MODE_RDWR 3 /* RD | WR */
/linux-4.4.14/sound/soc/au1x/
H A Dac97c.c76 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) WR() function
102 WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ); au1xac97c_ac97_read()
141 WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v)); au1xac97c_ac97_write()
158 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN); au1xac97c_ac97_warm_reset()
160 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG); au1xac97c_ac97_warm_reset()
161 WR(ctx, AC97_CONFIG, ctx->cfg); au1xac97c_ac97_warm_reset()
169 WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS); au1xac97c_ac97_cold_reset()
171 WR(ctx, AC97_CONFIG, ctx->cfg); au1xac97c_ac97_cold_reset()
266 WR(ctx, AC97_ENABLE, EN_D | EN_CE); au1xac97c_drvprobe()
267 WR(ctx, AC97_ENABLE, EN_CE); au1xac97c_drvprobe()
270 WR(ctx, AC97_CONFIG, ctx->cfg); au1xac97c_drvprobe()
293 WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */ au1xac97c_drvremove()
305 WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */ au1xac97c_drvsuspend()
314 WR(ctx, AC97_ENABLE, EN_D | EN_CE); au1xac97c_drvresume()
315 WR(ctx, AC97_ENABLE, EN_CE); au1xac97c_drvresume()
316 WR(ctx, AC97_CONFIG, ctx->cfg); au1xac97c_drvresume()
H A Di2sc.c74 static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v) WR() function
145 WR(ctx, I2S_ENABLE, EN_D | EN_CE); au1xi2s_trigger()
146 WR(ctx, I2S_ENABLE, EN_CE); au1xi2s_trigger()
148 WR(ctx, I2S_CFG, ctx->cfg); au1xi2s_trigger()
153 WR(ctx, I2S_CFG, ctx->cfg); au1xi2s_trigger()
154 WR(ctx, I2S_ENABLE, EN_D); /* power off */ au1xi2s_trigger()
277 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ au1xi2s_drvremove()
287 WR(ctx, I2S_ENABLE, EN_D); /* clock off, disable */ au1xi2s_drvsuspend()
/linux-4.4.14/drivers/tty/serial/jsm/
H A Djsm.h269 u8 txrx; /* WR RHR/THR - Holding Reg */
270 u8 ier; /* WR IER - Interrupt Enable Reg */
271 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
272 u8 lcr; /* WR LCR - Line Control Reg */
273 u8 mcr; /* WR MCR - Modem Control Reg */
274 u8 lsr; /* WR LSR - Line Status Reg */
275 u8 msr; /* WR MSR - Modem Status Reg */
276 u8 spr; /* WR SPR - Scratch Pad Reg */
324 u8 txrx; /* WR RHR/THR - Holding Reg */
325 u8 ier; /* WR IER - Interrupt Enable Reg */
326 u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
327 u8 lcr; /* WR LCR - Line Control Reg */
328 u8 mcr; /* WR MCR - Modem Control Reg */
329 u8 lsr; /* WR LSR - Line Status Reg */
330 u8 msr; /* WR MSR - Modem Status Reg */
331 u8 spr; /* WR SPR - Scratch Pad Reg */
332 u8 fctr; /* WR FCTR - Feature Control Reg */
333 u8 efr; /* WR EFR - Enhanced Function Reg */
334 u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
335 u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
336 u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
337 u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
338 u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
339 u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
/linux-4.4.14/drivers/net/ethernet/8390/
H A D8390.h157 #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
159 #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
160 #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
162 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
164 #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
166 #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
167 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
172 #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
173 #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
175 #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
176 #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
178 #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
180 #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
199 #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
201 #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
202 #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
/linux-4.4.14/arch/blackfin/include/asm/
H A Dnand.h33 /* RD/WR strobe delay timing information, all times in SCLK cycles */
H A Dbfin_can.h121 #define WR 0x0002 /* RX Warning Flag */ macro
/linux-4.4.14/drivers/staging/rdma/amso1100/
H A Dc2_cm.c103 * the WR. c2_llp_connect()
114 * Send WR to adapter. NOTE: There is no synch reply from c2_llp_connect()
159 * Build the WR c2_llp_service_create()
175 * Send WR to adapter c2_llp_service_create()
245 * Build the WR c2_llp_service_destroy()
258 * Send WR to adapter c2_llp_service_destroy()
293 struct c2wr_cr_accept_req *wr; /* variable length WR */ c2_llp_accept()
324 /* Build the WR */ c2_llp_accept()
354 /* Send WR to adapter */ c2_llp_accept()
412 * Build the WR c2_llp_reject()
425 * Send WR to adapter c2_llp_reject()
H A Dc2_mm.c56 struct c2wr_nsmr_pbl_req *wr; /* PBL WR ptr */ send_pbl_messages()
134 * Send WR to adapter send_pbl_messages()
210 * build the WR c2_nsmr_register_phys_kern()
251 * send the WR to the adapter c2_nsmr_register_phys_kern()
320 struct c2wr_stag_dealloc_rep *reply; /* WR reply */ c2_stag_dealloc()
333 * Build the WR c2_stag_dealloc()
346 * Send WR to adapter c2_stag_dealloc()
H A Dc2_qp.c319 * Initialize the WR destroy_qp()
343 * Send WR to adapter destroy_qp()
481 /* Send the WR to the adapter */ c2_alloc_qp()
645 * message, swapping to WR byte order and ensure the total length doesn't
696 * Setup the SGL in the WR to make it easier for the RNIC. move_sgl()
749 * the completed WR into msg. Then it posts the message.
753 * wr - ptr to host-copy of the WR.
775 * Since all header fields in the WR are the same as the qp_wr_post()
885 * Move the local and remote stag/to/len into the WR. c2_post_send()
907 * break out. Possible errors include bogus WR c2_post_send()
971 * Create local host-copy of the WR c2_post_receive()
986 * break out. Possible errors include bogus WR c2_post_receive()
H A Dc2_intr.c113 * Handles verbs WR replies.
147 * just copy the WR header into a local variable. handle_vq()
H A Dc2_wr.h716 * No synchronous reply from adapter to this WR. The results of
934 struct c2wr_hdr hdr; /* Has status and WR Type */
948 struct c2wr_hdr hdr; /* Has status and WR Type */
1103 * hdr.context is the user_context from the rnic_open WR. NULL If this
H A Dc2_rnic.c567 /* create the WR init message */ c2_rnic_init()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfbtft-io.c146 /* Start writing by pulling down /WR */ fbtft_write_gpio8_wr()
169 /* Pullup /WR */ fbtft_write_gpio8_wr()
196 /* Start writing by pulling down /WR */ fbtft_write_gpio16_wr()
219 /* Pullup /WR */ fbtft_write_gpio16_wr()
H A Dfbtft_device.c1234 /* Start writing by pulling down /WR */ write_gpio16_wr_slow()
1257 /* Pullup /WR */ write_gpio16_wr_slow()
/linux-4.4.14/drivers/isdn/act2000/
H A Dact2000_isa.h73 #define ISA_EPR_IN 0x02 /* Rom Register In (WR) */
74 #define ISA_EPR_CLK 0x04 /* Rom Clock (WR) */
75 #define ISA_EPR_CS 0x08 /* Rom Cip Select (WR) */
76 #define ISA_EPR_HOLD 0x10 /* Rom Hold Signal (WR) */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dfirmware_exports.h35 /* WR OPCODES supported by the firmware.
79 /* Maximum size of a WR sent from the host, limited by the SGE.
81 * Note: WR coming from ULP or TP are only limited by CIM.
124 * every WR.
H A Dadapter.h179 unsigned int token; /* WR token */
H A Dsge.c84 /* WR size in bytes */
148 * HW allows up to 4 descriptors to be combined into a WR.
937 * packet. Ethernet packets require addition of WR and CPL headers.
1031 * write_wr_hdr_sgl - write a WR header and, optionally, SGL
1033 * @skb: the packet corresponding to the WR
1041 * @wr_hi: top 32 bits of WR header based on WR type (big endian)
1042 * @wr_lo: low 32 bits of WR header based on WR type (big endian)
1046 * and we just need to write the WR header. Otherwise we distribute the
H A Dcxgb3_offload.c548 * Populate a TID_RELEASE WR. The skb must be already propely sized.
/linux-4.4.14/net/sunrpc/xprtrdma/
H A Dfrwr_ops.c27 * LOCAL_INV WR is posted. If posting succeeds, the MR is placed on
32 * that is INVALID but the LOCAL_INV WR has not completed. Work Queue
33 * ordering prevents a subsequent FAST_REG WR from executing against
50 * (Or, the LOCAL_INV WR has not completed or flushed yet).
53 * entered ERROR state, and the pending WR was flushed.
203 * 1. FRMR reg WR for head frwr_op_open()
204 * 2. FRMR invalidate WR for head frwr_op_open()
207 * 5. FRMR reg WR for tail frwr_op_open()
208 * 6. FRMR invalidate WR for tail frwr_op_open()
209 * 7. The RDMA_SEND WR frwr_op_open()
H A Dsvc_rdma_transport.c179 * last WR that uses it completes. svc_rdma_unmap_dma()
465 /* Decrement used SQ WR count */ sq_cq_reap()
999 * Fast Global DMA Remote WR svc_rdma_accept()
1278 /* See if we can opportunistically reap SQ WR to make room */ svc_rdma_send()
1281 /* Wait until SQ WR available if SQ still full */ svc_rdma_send()
1289 /* Take a transport ref for each WR posted */ svc_rdma_send()
1293 /* Bump used SQ WR count and post */ svc_rdma_send()
1301 dprintk("svcrdma: failed to post SQ WR rc=%d, " svc_rdma_send()
1347 /* Prepare SEND WR */ svc_rdma_send_error()
H A Dsvc_rdma.c286 printk(KERN_INFO "Could not allocate WR ctxt cache.\n"); svc_rdma_init()
H A Dsvc_rdma_recvfrom.c301 /* Prepare REG WR */ rdma_read_chunk_frmr()
H A Dsvc_rdma_sendto.c282 /* Prepare WRITE WR */ send_write()
H A Dxprt_rdma.h534 /* WR context cache. Created in svc_rdma.c */
/linux-4.4.14/drivers/scsi/csiostor/
H A Dcsio_scsi.c193 * csio_scsi_init_cmd_wr - Initialize the SCSI CMD WR.
196 * @size: Size of WR (including FW WR + immed data + rsp SG entry
241 (sizeof(struct fw_scsi_cmd_wr) + /* WR size */ \
248 * csio_scsi_cmd - Create a SCSI CMD WR.
251 * Gets a WR slot in the ingress queue and initializes it with SCSI CMD WR.
267 /* Initialize WR in one shot */ csio_scsi_cmd()
273 * Make a temporary copy of the WR and write back csio_scsi_cmd()
274 * the copy into the WR pair. csio_scsi_cmd()
352 * csio_scsi_init_read_wr - Initialize the READ SCSI WR.
355 * @size: Size of WR (including FW WR + immed data + rsp SG entry + data SGL
396 /* Move WR pointer past command and immediate data */ csio_scsi_init_read_wr()
405 * csio_scsi_init_write_wr - Initialize the WRITE SCSI WR.
408 * @size: Size of WR (including FW WR + immed data + rsp SG entry + data SGL
449 /* Move WR pointer past command and immediate data */ csio_scsi_init_write_wr()
457 /* Calculate WR size needed for fw_scsi_read_wr/fw_scsi_write_wr */
460 (sz) = sizeof(struct fw_scsi_##oper##_wr) + /* WR size */ \
471 * csio_scsi_read - Create a SCSI READ WR.
474 * Gets a WR slot in the ingress queue and initializes it with
475 * SCSI READ WR.
492 /* Initialize WR in one shot */ csio_scsi_read()
497 * Make a temporary copy of the WR and write back csio_scsi_read()
498 * the copy into the WR pair. csio_scsi_read()
508 * csio_scsi_write - Create a SCSI WRITE WR.
511 * Gets a WR slot in the ingress queue and initializes it with
512 * SCSI WRITE WR.
529 /* Initialize WR in one shot */ csio_scsi_write()
534 * Make a temporary copy of the WR and write back csio_scsi_write()
535 * the copy into the WR pair. csio_scsi_write()
549 * If contiguous,driver posts SGLs in the WR otherwise post internal
637 * csio_scsi_init_abrt_cls_wr - Initialize an ABORT/CLOSE WR.
640 * @size: Size of WR
685 /* Initialize WR in one shot */ csio_scsi_abrt_cls()
690 * Make a temporary copy of the WR and write back csio_scsi_abrt_cls()
691 * the copy into the WR pair. csio_scsi_abrt_cls()
919 * Check if original I/O WR completed before the Abort csio_scsis_aborting()
971 * cleanup paths, if the FW forgot to reply to the ABORT WR csio_scsis_aborting()
1009 * Check if original I/O WR completed before the Close csio_scsis_closing()
1083 * csio_scsi_cmpl_handler - WR completion handler for SCSI.
1085 * @wr: The completed WR from the ingress queue.
1086 * @len: Length of the WR.
1089 * @scsiwr: Pointer to SCSI WR.
1091 * This is the WR completion handler called per completion from the
1093 * header where the actual WR is present.
1094 * It then gets the status, WR handle (ioreq pointer) and the len of
1095 * the WR, based on WR opcode. Only on a non-good status is the entire
1096 * WR copied into the WR cache (ioreq->fw_wr).
1097 * The ioreq corresponding to the WR is returned to the caller.
1146 csio_warn(hw, "WR with invalid opcode in SCSI IQ: %x\n", *tempwr); csio_scsi_cmpl_handler()
1706 csio_err(hw, "Unknown SCSI FW WR status:%d req:%p cmnd:%p\n", csio_scsi_err_handler()
H A Dcsio_wr.c162 * csio_wr_alloc_q - Allocate a WR queue and initialize it.
165 * @wrsize: Since of WR in this queue, if fixed.
213 csio_err(hw, "Invalid Ingress queue WR size:%d\n", csio_wr_alloc_q()
404 * @iq_idx: Ingress queue index in the WR module.
545 * @eq_idx: Egress queue index in the WR module.
770 /* Get the WR */ csio_wr_cleanup_iq_ftr()
839 * csio_wr_get - Get requested size of WR entry/entries from queue.
849 * NOTE about WR pair:
851 * A WR can start towards the end of a queue, and then continue at the
897 * request. Check if we are near the end of q, and if WR spills over. csio_wr_get()
934 * csio_wr_copy_to_wrp - Copies given data into WR.
1029 * @wr: The freelist completion WR in the ingress queue.
1100 * @ftr: Ingress queue WR SGE footer.
1103 * bit in the footer of the current WR.
1155 /* Subtract footer from WR len */ csio_wr_process_iq()
1194 * Ingress *always* has fixed size WR entries. Therefore, csio_wr_process_iq()
1565 * @wrm: WR module
1604 * @wrm: WR module
1607 * Uninitialize WR module. Free q_arr and pointers in it.
H A Dcsio_lnode.c264 csio_ln_dbg(ln, "WR error:%x in processing fdmi rpa cmd\n", csio_ln_fdmi_done()
297 csio_ln_dbg(ln, "WR error:%x in processing fdmi rhba cmd\n", csio_ln_fdmi_rhba_cbfn()
401 csio_ln_dbg(ln, "WR error:%x in processing fdmi dprt cmd\n", csio_ln_fdmi_dprt_cbfn()
502 csio_ln_dbg(ln, "WR error:%x in processing fdmi dhba cmd\n", csio_ln_fdmi_dhba_cbfn()
1406 * @wr - WR.
1407 * @len - WR len.
1408 * This handler is invoked when an outstanding mgmt WR is completed.
1426 "Invalid ELS CT WR length recvd, len:%x\n", len); csio_ln_mgmt_wr_handler()
1438 "Error- Invalid IO handle recv in WR. handle: %p\n", csio_ln_mgmt_wr_handler()
1461 * @cmd: FW cmd/WR.
1463 * Process received FCoE cmd/WR event from FW.
1576 csio_warn(hw, "unexpected WR op(0x%x) recv\n", csio_fcoe_fwevt_handler()
1586 csio_warn(hw, "unexpected WR op(0x%x) recv\n", csio_fcoe_fwevt_handler()
1651 * csio_ln_prep_ecwr - Prepare ELS/CT WR.
1653 * @wr_len - WR len
1654 * @immd_len - WR immediate data
1659 * @fw_wr - ELS/CT WR to be prepared.
1723 /* Calculate WR Size for this ELS REQ */ csio_ln_mgmt_submit_wr()
1733 /* Roundup WR size in units of 16 bytes */ csio_ln_mgmt_submit_wr()
1736 /* Get WR to send ELS REQ */ csio_ln_mgmt_submit_wr()
1739 csio_err(hw, "Failed to get WR for ec_req %p ret:%d\n", csio_ln_mgmt_submit_wr()
1744 /* Prepare Generic WR used by all ELS/CT cmd */ csio_ln_mgmt_submit_wr()
1750 /* Copy ELS/CT WR CMD */ csio_ln_mgmt_submit_wr()
1755 /* Copy payload to Immediate section of WR */ csio_ln_mgmt_submit_wr()
H A Dcsio_scsi.h64 * Max Egress WR size = 512 bytes
65 * One SCSI egress WR has the following fixed no of bytes:
66 * 48 (sizeof(struct fw_scsi_write[read]_wr)) - FW WR
H A Dcsio_wr.h102 /* WR status is at the same position as retval in a CMD header */
249 uint16_t wr_status; /* WR completion status */
319 * WR pair:
321 * A WR can start towards the end of a queue, and then continue at the
H A Dcsio_isr.c138 * csio_process_scsi_cmpl - Process a SCSI WR completion.
140 * @wr: The completed WR from the ingress queue.
141 * @len: Length of the WR.
H A Dcsio_hw.c3715 * WR queues and save off the queue index returned by the WR
/linux-4.4.14/arch/blackfin/kernel/
H A Dcplbinfo.c39 seq_printf(m, "Index\tAddress\t\tData\tSize\tU/RD\tU/WR\tS/WR\tSwitch\n"); cplbinfo_print_header()
/linux-4.4.14/include/uapi/linux/
H A Datmioc.h16 /* everybody including atmioc.h will also need _IO{,R,W,WR} */
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c70 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
76 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
82 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
88 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ setup_chip_select()
94 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ setup_chip_select()
/linux-4.4.14/drivers/bus/
H A Domap_l3_noc.h477 { 0x29, "Crypto DMA WR"},
482 { 0x35, "USB0 WR"},
484 { 0x37, "USB1 WR"},
H A Domap_l3_smx.h168 /* SDMA WR has 2 IDs */
241 /* SDMA WR IA */
/linux-4.4.14/arch/powerpc/include/asm/
H A Dpte-40x.h18 * RPN..................... 0 0 EX WR ZSEL....... W I M G
/linux-4.4.14/arch/mips/sgi-ip22/
H A Dip22-berr.c71 gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "", print_buserr()
H A Dip28-berr.c273 gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "", print_buserr()
/linux-4.4.14/include/linux/sunrpc/
H A Dsvc_rdma.h136 atomic_t sc_sq_count; /* Number of SQ WR on queue */
139 int sc_max_req_size; /* Size of each RQ WR buf */
/linux-4.4.14/include/uapi/sound/
H A Dasound.h111 unsigned int device; /* WR: device number */
311 unsigned int device; /* RO/WR (control): device number */
312 unsigned int subdevice; /* RO/WR (control): subdevice number */
313 int stream; /* RO/WR (control): stream direction */
609 unsigned int device; /* RO/WR (control): device number */
610 unsigned int subdevice; /* RO/WR (control): subdevice number */
611 int stream; /* WR: stream */
/linux-4.4.14/drivers/media/pci/cx23885/
H A Dcx23885-cards.c1311 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1352 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1449 GPIO-18 ~WR to CiMax cx23885_gpio_setup()
1459 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ cx23885_gpio_setup()
1508 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1542 GPIO-13 ~WR out cx23885_gpio_setup()
1557 /* ~RD, ~WR high; ADDR low; ~CS high */ cx23885_gpio_setup()
1626 * GPIO-18 ~WR to CiMax cx23885_gpio_setup()
1639 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ cx23885_gpio_setup()
H A Daltera-ci.c29 * GPIO-13 ~WR out
44 * | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS |
H A Dcimax2.c36 | WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
H A Dcx23885-417.c332 /* Transition CS/WR to effect write transaction across bus. */ mc417_register_write()
426 * Transition 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)? mc417_register_read()
490 /* Transition CS/WR to effect write transaction across bus. */ mc417_memory_write()
/linux-4.4.14/drivers/sbus/char/
H A Dflash.c184 printk(KERN_INFO "%s: OBP Flash, RD %lx[%lx] WR %lx[%lx]\n", flash_probe()
/linux-4.4.14/drivers/infiniband/hw/cxgb3/
H A Diwch.h55 u32 max_sge_per_rdma_write_wr; /* for RDMA Write WR */
H A Diwch_cq.c214 * with a WR, we might have to poll again after removing iwch_poll_cq()
H A Diwch_provider.h321 * will NOT replay outstanding WR
H A Diwch_qp.c172 /* If we need a 2nd WR, then set it up */ build_memreg()
299 * it to the uP in the recv WR. The uP will build the PBL and setup build_zero_stag_recv()
H A Dcxio_wr.h697 u32 wptr; /* idx to next available WR slot */
H A Dcxio_hal.c1275 * signaled WR is completed. cxio_poll_cq()
1296 * Reap the associated WR(s) that are freed up with this cxio_poll_cq()
H A Diwch_provider.c965 * 2 WR fragments. iwch_create_qp()
/linux-4.4.14/drivers/net/wireless/b43/
H A Dphy_a.h40 #define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
/linux-4.4.14/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c89 /* Enable WR-REQ: */ a3xx_hw_init()
109 /* Enable WR-REQ: */ a3xx_hw_init()
129 /* Enable WR-REQ: */ a3xx_hw_init()
144 /* Enable WR-REQ: */ a3xx_hw_init()
/linux-4.4.14/arch/arm/mach-pxa/
H A Dam300epd.c97 static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR",
H A Dcm-x300.c168 GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC WR */
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dskfbi.h385 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
402 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
420 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
436 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
506 #define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */
508 #define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */
511 #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */
512 #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */
693 #define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */
698 #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */
809 /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_uld.h252 unsigned char wr_cred; /* WR 16-byte credits */
272 /* WR */
H A Dsge.c123 * for a full sized WR.
129 * into a WR.
134 * Max size of a WR sent through a control Tx queue.
783 * calc_tx_flits - calculate the number of flits for a packet Tx WR
786 * Returns the number of flits needed for a Tx WR for the given Ethernet
787 * packet, including the needed WR and CPL headers.
826 * packet, including the needed WR and CPL headers.
906 * memory mapped BAR2 space. For coalesced WR SGE fetches
1337 * Returns true if a packet can be sent as a WR with immediate data.
1347 * @wr: most recent WR written to the queue
1352 * we suspend it and have the last WR wake it up.
1480 * Returns true if a packet can be sent as an offload WR with immediate
H A Dt4_hw.h79 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
H A Dcxgb4_main.c1594 * Populate a TID_RELEASE WR. Caller must properly size the skb.
H A Dt4_hw.c5501 /* t4_mk_filtdelwr - create a delete filter WR
/linux-4.4.14/drivers/infiniband/ulp/iser/
H A Discsi_iser.h127 /* the max TX (send) WR supported by the iSER QP is defined by *
131 * send WR. D=8 comes from 64K/8K */
283 * @wr_idx: Current WR index
H A Diser_verbs.c1136 * @wr_id: completion WR identifier
/linux-4.4.14/net/9p/
H A Dtrans_rdma.c110 * p9_rdma_context - Keeps track of in-process WR
112 * @wc_op: The original WR op for when the CQE completes in error.
113 * @busa: Bus address to unmap when the WR completes
/linux-4.4.14/net/rds/
H A Diw_rdma.c684 * Perform a WR for the reg_mr. Each individual page rds_iw_rdma_reg_mr()
686 * inside the reg_mr WR. The key used is a rolling 8bit rds_iw_rdma_reg_mr()
777 /* Try to post the LOCAL_INV WR to the queue. */ rds_iw_free_fastreg()
H A Dib_recv.c661 /* Failed to send. Release the WR, and rds_ib_send_ack()
683 * 3. If the ACK WR is done sending, we get called from the
685 * another ACK pending (postponed because the WR was on the
689 * - i_ack_flags, which keeps track of whether the ACK WR
H A Diw_recv.c450 /* Failed to send. Release the WR, and rds_iw_send_ack()
472 * 3. If the ACK WR is done sending, we get called from the
474 * another ACK pending (postponed because the WR was on the
478 * - i_ack_flags, which keeps track of whether the ACK WR
H A Dib_send.c103 * we would need to take an event for the rdma WR. To implement #1, rds_ib_send_unmap_rdma()
178 "RDS/IB: %s: unexpected opcode 0x%x in WR!\n", rds_ib_send_unmap_op()
317 * each SEND WR we post, we decrement this by one.
H A Diw_send.c255 "RDS/IW: %s: unexpected opcode 0x%x in WR!\n", rds_iw_send_cq_comp_handler()
303 * each SEND WR we post, we decrement this by one.
700 printk(KERN_NOTICE "send WR dport=%u flags=0x%x len=%d\n", rds_iw_xmit()
H A Diw_cm.c186 /* The offset of 1 is to accommodate the additional ACK WR. */ rds_iw_init_qp_attrs()
/linux-4.4.14/drivers/rtc/
H A Drtc-v3020.c107 { 0, GPIOF_OUT_INIT_HIGH, "RTC WR"},
/linux-4.4.14/drivers/net/wireless/b43legacy/
H A Dphy.h142 #define B43legacy_PHY_ANTWRSETT B43legacy_PHY_OFDM(0x8C) /* Antenna WR settle */
/linux-4.4.14/drivers/usb/gadget/udc/
H A Dm66592-udc.h83 #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
84 #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
H A Dbcm63xx_udc.c2240 seq_printf(s, " <<WR"); bcm63xx_iudma_dbg_show()
/linux-4.4.14/drivers/staging/rdma/ipath/
H A Dipath_ud.c76 * qkey from the QP context instead of the WR (see 10.2.5). ipath_ud_loopback()
378 * qkey from the QP context instead of the WR (see 10.2.5). ipath_make_ud_req()
H A Dipath_srq.c44 * @bad_wr: the first WR to cause a problem is put here
H A Dipath_verbs.c454 * @bad_wr: the first bad WR is put here
482 * @wr: the WR to post
483 * @bad_wr: the first bad WR is put here
H A Dipath_eeprom.c1055 ipath_dev_err(dd, "Failed tempsense WR command %02X\n", ipath_tempsense_internal_read()
/linux-4.4.14/drivers/mtd/nand/
H A Dcafe_nand.c211 /* Set RD or WR bits as appropriate */ cafe_nand_cmdfunc()
253 /* If WR or RD bits set, set up DMA */ cafe_nand_cmdfunc()
/linux-4.4.14/drivers/infiniband/hw/qib/
H A Dqib_ud.c104 * qkey from the QP context instead of the WR (see 10.2.5). qib_ud_loopback()
378 * qkey from the QP context instead of the WR (see 10.2.5). qib_make_ud_req()
H A Dqib_srq.c44 * @bad_wr: A pointer to the first WR to cause a problem is put here
H A Dqib_verbs.c475 * @bad_wr: the first bad WR is put here
505 * @wr: the WR to post
506 * @bad_wr: the first bad WR is put here
H A Dqib_sd7220.c1168 "Global WR failed: elt %d, addr 0x%X, val %02X\n", ibsd_mod_allchnls()
/linux-4.4.14/drivers/infiniband/ulp/ipoib/
H A Dipoib.h210 * post another WR that completes on the same CQ and wait for this
211 * WR to return as a WC;
H A Dipoib_cm.c216 * make sure we have at most 1 outstanding WR. */ ipoib_cm_start_rx_drain()
223 * error" WC will be immediately generated for each WR we post. ipoib_cm_start_rx_drain()
254 .send_cq = priv->recv_cq, /* For drain WR */ ipoib_cm_create_rx_qp()
257 .cap.max_send_wr = 1, /* For drain WR */ ipoib_cm_create_rx_qp()
/linux-4.4.14/include/linux/usb/
H A Dr8a66597.h204 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
205 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
/linux-4.4.14/drivers/tty/serial/
H A Dip22zilog.h265 /* Read Register 15 (value of WR 15) */
H A Dsunzilog.h273 /* Read Register 15 (value of WR 15) */
H A Dpmac_zilog.h360 /* Read Register 15 (value of WR 15) */
/linux-4.4.14/drivers/staging/rdma/hfi1/
H A Dsrq.c61 * @bad_wr: A pointer to the first WR to cause a problem is put here
H A Dud.c126 * qkey from the QP context instead of the WR (see 10.2.5). ud_loopback()
412 * qkey from the QP context instead of the WR (see 10.2.5). hfi1_make_ud_req()
H A Dverbs.c479 * @bad_wr: the first bad WR is put here
523 * @wr: the WR to post
524 * @bad_wr: the first bad WR is put here
/linux-4.4.14/drivers/mmc/host/
H A Dmmc_spi.c486 * - N(WR) (== 1..N) bytes of all-ones, before data write mmc_spi_command_send()
513 cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ mmc_spi_command_send()
637 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. mmc_spi_setup_data_message()
660 * - caller handled preceding N(WR) [1+] all-ones bytes
H A Dsunxi-mmc.c443 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", sunxi_mmc_dump_errinfo()
/linux-4.4.14/drivers/net/hamradio/
H A Dz8530.h220 /* Read Register 15 (value of WR 15) */
/linux-4.4.14/include/linux/mmc/
H A Dmmc.h85 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
/linux-4.4.14/arch/alpha/kernel/
H A Derr_marvel.c743 "TLB - Invalid WR transaction", marvel_print_pox_err()
745 "DMA - WR error (see north port)", marvel_print_pox_err()
747 "PPR - WR error (see north port)", marvel_print_pox_err()
/linux-4.4.14/drivers/infiniband/hw/mlx4/
H A Dqp.c275 /* Post NOP WQE to prevent wrap-around in the middle of WR */ pad_wraparound()
449 * WR posting. Unfortunately, if we do this then the set_kernel_sq_size()
450 * wqe_index field in CQEs can't be used to look up the WR ID set_kernel_sq_size()
455 * constant-sized WRs to make sure a WR is always fully within set_kernel_sq_size()
459 * work queue, to avoid wrap-around in the middle of WR. We set_kernel_sq_size()
488 * We need to leave 2 KB + 1 WR of headroom in the SQ to set_kernel_sq_size()
3029 * in the middle of WR). mlx4_ib_post_send()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dskge.h246 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
248 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
251 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
252 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
784 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
785 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
H A Dsky2.h509 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
511 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
514 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
515 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
/linux-4.4.14/drivers/i2c/algos/
H A Di2c-algo-pca.c216 printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s", pca_xfer()
/linux-4.4.14/drivers/net/wan/
H A Dz85230.h243 /* Read Register 15 (value of WR 15) */
/linux-4.4.14/drivers/phy/
H A Dphy-xgene.c580 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", sds_wr()
601 pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n", sds_rd()
619 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); cmu_wr()
680 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, serdes_wr()
/linux-4.4.14/drivers/staging/rdma/ehca/
H A Dehca_reqs.c450 /* Reject WR if QP is in RESET, INIT or RTR state */ ehca_post_send()
590 /* Reject WR if QP is in RESET state */ ehca_post_recv()
/linux-4.4.14/drivers/infiniband/hw/cxgb4/
H A Dcq.c598 * signaled WR is completed. poll_cq()
617 * Reap the associated WR(s) that are freed up with this poll_cq()
H A Dqp.c154 * so no need to post a RESET WR for these EQs. destroy_qp()
H A Dcm.c514 /* Pad WR to 16 byte boundary */ send_flowc()
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
H A Danysee.c211 u8 buf[52]; /* 4 + 48 (I2C WR USB command header + I2C WR max) */ anysee_master_xfer()
H A Drtl28xxu.c153 * with RTL2831U + MT2060 gives max RD 24 and max WR 22 bytes. rtl28xxu_i2c_xfer()
1453 dev_dbg(&d->intf->dev, "WR SYS0=%02x GPIO_OUT_VAL=%02x\n", sys0, gpio); rtl2831u_power_ctrl()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dsge.c118 * inlined into a WR. This is limited by the maximum value which
125 * Max size of a WR sent through a control TX queue.
850 * calc_tx_flits - calculate the number of flits for a packet TX WR
854 * given Ethernet packet, including the needed WR and CPL headers.
1262 * the WR Header wrapping around the TX Descriptor Ring. If our t4vf_eth_xmit()
/linux-4.4.14/drivers/spi/
H A Dspi-dln2.c131 * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
/linux-4.4.14/drivers/scsi/cxgbi/
H A Dlibcxgbi.h263 CTPF_TX_DATA_SENT, /* already sent a TX_DATA WR */
/linux-4.4.14/drivers/edac/
H A Dmce_amd.c48 "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
/linux-4.4.14/arch/x86/include/asm/
H A Dcpufeature.h223 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
/linux-4.4.14/net/dccp/
H A Dinput.c37 * On receiving Close/CloseReq, both RD/WR shutdown are performed. dccp_fin()
/linux-4.4.14/arch/microblaze/include/asm/
H A Dpgtable.h184 * RPN..................... 0 0 EX WR ZSEL....... W I M G pte_mkspecial()
/linux-4.4.14/drivers/media/radio/wl128x/
H A Dfmdrv_common.c211 cmd_hdr->rd_wr ? "RD" : "WR", cmd_hdr->dlen); dump_tx_skb_data()
236 (evt_hdr->rd_wr) ? "RD" : "WR", evt_hdr->dlen); dump_rx_skb_data()
/linux-4.4.14/fs/ceph/
H A Dcaps.c346 /* prefer mds with WR|BUFFER|EXCL caps */ __ceph_get_cap_mds()
2362 * for WRBUFFER|WR -> WR to avoid a new WR sync write from try_get_cap_refs()
2462 * Wait for caps, and take cap references. If we can't get a WR cap
2575 * If we are releasing a WR cap (from a sync write), finalize any affected
H A Dsnap.c560 " seq %llu used WR, now pending\n", inode, ceph_queue_cap_snap()
/linux-4.4.14/drivers/tty/
H A Dmxser.c1443 #define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1444 #define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1445 #define EN0_DCFG 0x00E /* Data configuration reg WR */
/linux-4.4.14/drivers/infiniband/core/
H A Dmad.c1152 /* Set WR ID to find mad_send_wr upon completion */ ib_send_mad()
2885 /* Initialize common receive WR fields */ ib_mad_post_receive_mads()
2919 /* Post receive WR */ ib_mad_post_receive_mads()
H A Dverbs.c91 [IB_WC_WR_FLUSH_ERR] = "WR flushed",
/linux-4.4.14/drivers/pinctrl/sh-pfc/
H A Dpfc-sh73a0.c2036 /* CS, WR, RD, RS */
2126 /* CS, WR, RD, RS */
2134 /* CS, WR, RD, RS */
H A Dpfc-r8a7740.c2191 /* CS, WR, RD, RS */
2286 /* CS, WR, RD, RS */
H A Dpfc-r8a7778.c2960 [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */
/linux-4.4.14/drivers/mtd/nand/brcmnand/
H A Dbrcmnand.c656 acc_control |= ecc_flags; /* enable RD/WR ECC */ brcmnand_set_ecc_enabled()
660 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ brcmnand_set_ecc_enabled()
/linux-4.4.14/drivers/gpu/drm/sti/
H A Dsti_hqvdp.c633 /* Configure Plugs (same for RD & WR) */ sti_hqvdp_init_plugs()
/linux-4.4.14/drivers/media/platform/davinci/
H A Ddm355_ccdc.c474 /* set WR bit to write */ ccdc_write_dfc_entry()
/linux-4.4.14/drivers/media/rc/
H A Dnuvoton-cir.c207 pr_info(" * WR FIFO DATA: 0x%x\n", cir_wake_dump_regs()
/linux-4.4.14/drivers/net/wireless/ath/ath6kl/
H A Dsdio.c232 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr, ath6kl_sdio_setup_scat_data()
/linux-4.4.14/drivers/usb/host/
H A Disp1362-hcd.c29 * Rev 1.00 from 27 May data corruption may occur when the #WR signal
32 * implement the recommended fix (gating the #WR with #CS) software
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_ddi.c1214 /* Special case handling for 540 pixel clock: bypass WR PLL entirely hsw_ddi_calculate_wrpll()
1225 * the WR PLL. hsw_ddi_calculate_wrpll()
/linux-4.4.14/drivers/target/iscsi/
H A Discsi_target_configfs.c620 rb += sprintf(page+rb, " CmdSN/WR : CmdSN/WC : ExpCmdSN" lio_target_nacl_info_show()
/linux-4.4.14/drivers/scsi/cxgbi/cxgb3i/
H A Dcxgb3i.c844 * Process an acknowledgment of WR completion. Advance snd_una and send the
/linux-4.4.14/drivers/media/pci/cx88/
H A Dcx88-video.c382 bits 10 and 11: BERR signal asserted for RISC: RD, WR start_video_dma()
/linux-4.4.14/drivers/net/wireless/orinoco/
H A Dorinoco_usb.c127 #define USB_BUFFALO_L11G_WR_ID 0x000B /* BUFFALO WLI-USB-L11G-WR */
/linux-4.4.14/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
/linux-4.4.14/arch/tile/kernel/
H A Dpci_gx.c51 pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
/linux-4.4.14/arch/microblaze/kernel/
H A Dhw_exception_handler.S661 /* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
/linux-4.4.14/kernel/
H A Dworkqueue.c137 * WR: wq->mutex protected for writes. Sched-RCU protected for reads.
209 struct list_head pwqs_node; /* WR: node on wq->pwqs */
238 struct list_head pwqs; /* WR: all pwqs of this wq */
/linux-4.4.14/drivers/scsi/cxgbi/cxgb4i/
H A Dcxgb4i.c171 * Returns true if a packet can be sent as an offload WR with immediate
/linux-4.4.14/drivers/net/wireless/iwlwifi/pcie/
H A Dtx.c320 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); iwl_pcie_txq_inc_wr_ptr()
H A Dtrans.c1722 "WR pointer moved while flushing %d -> %d\n", iwl_trans_pcie_wait_txq_empty()
/linux-4.4.14/drivers/parisc/
H A Dlba_pci.c866 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
/linux-4.4.14/drivers/scsi/
H A Dscsi_debug.c2922 sdev_printk(KERN_ERR, scp->device, "Unprotected WR " resp_write_dt0()
3163 sdev_printk(KERN_ERR, scp->device, "Unprotected WR " resp_comp_write()
/linux-4.4.14/drivers/infiniband/ulp/isert/
H A Dib_isert.c2027 * @wr_id: completion WR identifier
/linux-4.4.14/drivers/infiniband/ulp/srp/
H A Dib_srp.c1080 "Queueing INV WR for rkey %#x failed (%d)\n", srp_unmap_data()
/linux-4.4.14/drivers/atm/
H A Didt77252.c367 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", idt77252_write_gp()
/linux-4.4.14/drivers/net/wireless/iwlwifi/dvm/
H A Dcommands.h990 * When using full FIFO flush this command checks the scheduler HW block WR/RD
/linux-4.4.14/drivers/net/wireless/iwlwifi/mvm/
H A Dmac80211.c1042 /* Set fence pointer to the same place like WR pointer */ iwl_mvm_dump_fifos()
/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h20 * WR - Write Clear (write 1 to clear the bit)

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