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Searched refs:rd32 (Results 1 – 101 of 101) sorted by relevance

/linux-4.1.27/drivers/net/ethernet/intel/igb/
De1000_mac.c78 reg = rd32(E1000_STATUS); in igb_get_bus_info_pcie()
475 rd32(E1000_CRCERRS); in igb_clear_hw_cntrs_base()
476 rd32(E1000_SYMERRS); in igb_clear_hw_cntrs_base()
477 rd32(E1000_MPC); in igb_clear_hw_cntrs_base()
478 rd32(E1000_SCC); in igb_clear_hw_cntrs_base()
479 rd32(E1000_ECOL); in igb_clear_hw_cntrs_base()
480 rd32(E1000_MCC); in igb_clear_hw_cntrs_base()
481 rd32(E1000_LATECOL); in igb_clear_hw_cntrs_base()
482 rd32(E1000_COLC); in igb_clear_hw_cntrs_base()
483 rd32(E1000_DC); in igb_clear_hw_cntrs_base()
[all …]
De1000_82575.c91 reg = rd32(E1000_MDIC); in igb_sgmii_uses_mdio_82575()
99 reg = rd32(E1000_MDICNFG); in igb_sgmii_uses_mdio_82575()
179 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_init_phy_params_82575()
215 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> in igb_init_phy_params_82575()
305 u32 eecd = rd32(E1000_EECD); in igb_init_nvm_params_82575()
421 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) in igb_init_mac_params_82575()
470 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_set_sfp_media_type_82575()
595 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_get_invariants_82575()
823 mdic = rd32(E1000_MDIC); in igb_get_phy_id_82575()
832 mdic = rd32(E1000_MDICNFG); in igb_get_phy_id_82575()
[all …]
Digb_ethtool.c146 status = rd32(E1000_STATUS); in igb_get_settings()
462 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
463 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
464 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
465 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
466 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
467 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
468 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
469 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
470 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
[all …]
Digb_ptp.c87 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82576()
88 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82576()
108 rd32(E1000_SYSTIMR); in igb_ptp_read_82580()
109 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82580()
110 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82580()
129 rd32(E1000_SYSTIMR); in igb_ptp_read_i210()
130 nsec = rd32(E1000_SYSTIML); in igb_ptp_read_i210()
131 sec = rd32(E1000_SYSTIMH); in igb_ptp_read_i210()
386 ctrl = rd32(E1000_CTRL); in igb_pin_extts()
387 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_pin_extts()
[all …]
Digb_main.c305 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
309 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
313 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
317 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
321 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
325 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
329 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
333 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
337 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
341 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
[all …]
De1000_i210.c50 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
66 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
83 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
87 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
151 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
190 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
274 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
352 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
477 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
653 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
[all …]
De1000_nvm.c72 u32 eecd = rd32(E1000_EECD); in igb_shift_out_eec_bits()
117 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
126 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
154 reg = rd32(E1000_EERD); in igb_poll_eerd_eewr_done()
156 reg = rd32(E1000_EEWR); in igb_poll_eerd_eewr_done()
179 u32 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
185 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
191 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
214 u32 eecd = rd32(E1000_EECD); in igb_standby_nvm()
239 eecd = rd32(E1000_EECD); in e1000_stop_nvm()
[all …]
De1000_mbx.c244 u32 mbvficr = rd32(E1000_MBVFICR); in igb_check_for_bit_pf()
302 u32 vflre = rd32(E1000_VFLRE); in igb_check_for_rst_pf()
330 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_obtain_mbx_lock_pf()
De1000_regs.h379 #define rd32(reg) (igb_rd32(hw, reg)) macro
381 #define wrfl() ((void)rd32(E1000_STATUS))
De1000_phy.c68 manc = rd32(E1000_MANC); in igb_check_reset_block()
163 mdic = rd32(E1000_MDIC); in igb_read_phy_reg_mdic()
220 mdic = rd32(E1000_MDIC); in igb_write_phy_reg_mdic()
266 i2ccmd = rd32(E1000_I2CCMD); in igb_read_phy_reg_i2c()
323 i2ccmd = rd32(E1000_I2CCMD); in igb_write_phy_reg_i2c()
375 data_local = rd32(E1000_I2CCMD); in igb_read_sfp_data_byte()
1358 ctrl = rd32(E1000_CTRL); in igb_phy_force_speed_duplex_setup()
2095 ctrl = rd32(E1000_CTRL); in igb_phy_hw_reset()
/linux-4.1.27/drivers/net/ethernet/intel/i40e/
Di40e_ptp.c67 lo = rd32(hw, I40E_PRTTSYN_TIME_L); in i40e_ptp_read()
68 hi = rd32(hw, I40E_PRTTSYN_TIME_H); in i40e_ptp_read()
258 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_rx_hang()
286 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); in i40e_ptp_rx_hang()
287 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); in i40e_ptp_rx_hang()
288 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); in i40e_ptp_rx_hang()
289 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); in i40e_ptp_rx_hang()
320 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); in i40e_ptp_tx_hwtstamp()
321 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); in i40e_ptp_tx_hwtstamp()
358 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_rx_hwtstamp()
[all …]
Di40e_diag.c43 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
47 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
57 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
Di40e_nvm.c49 gens = rd32(hw, I40E_GLNVM_GENS); in i40e_init_nvm()
56 fla = rd32(hw, I40E_GLNVM_FLA); in i40e_init_nvm()
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
154 srctl = rd32(hw, I40E_GLNVM_SRCTL); in i40e_poll_sr_srctl_done_bit()
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); in i40e_read_nvm_word_srctl()
788 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_nvmupd_state_writing()
Di40e_lan_hmc.c128 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
131 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
148 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
154 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
171 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
177 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
194 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
200 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
Di40e_adminq.c318 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
350 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
679 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
682 rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
716 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
745 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
950 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); in i40e_clean_arq_element()
Di40e_osdep.h47 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
Di40e_common.c148 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
574 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) in i40e_init_shared_code()
577 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> in i40e_init_shared_code()
579 func_rid = rd32(hw, I40E_PF_FUNC_RID); in i40e_init_shared_code()
712 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
881 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & in i40e_pf_reset()
885 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
897 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
922 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
926 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
[all …]
Di40e_main.c513 new_data = rd32(hw, loreg); in i40e_stat_update48()
514 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; in i40e_stat_update48()
540 new_data = rd32(hw, reg); in i40e_stat_update32()
1107 val = rd32(hw, I40E_PRTPM_EEE_STAT); in i40e_update_pf_stats()
2864 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ in i40e_enable_misc_int_causes()
3153 icr0 = rd32(hw, I40E_PFINT_ICR0); in i40e_intr()
3154 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); in i40e_intr()
3169 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); in i40e_intr()
3173 qval = rd32(hw, I40E_QINT_TQCTL(0)); in i40e_intr()
3200 val = rd32(hw, I40E_GLGEN_RSTAT); in i40e_intr()
[all …]
Di40e_virtchnl_pf.c166 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); in i40e_vc_disable_vf()
754 reg = rd32(hw, I40E_PF_PCI_CIAD); in i40e_quiesce_vf_pci()
788 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); in i40e_reset_vf()
808 reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); in i40e_reset_vf()
823 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); in i40e_reset_vf()
1953 reg = rd32(hw, I40E_PFINT_ICR0_ENA); in i40e_vc_process_vflr_event()
1964 reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx)); in i40e_vc_process_vflr_event()
Di40e_dcb_nl.c42 val = rd32(hw, I40E_PRTDCB_GENC); in i40e_get_pfc_delay()
Di40e_ethtool.c901 reg_buf[ri++] = rd32(hw, reg); in i40e_get_regs()
1007 val = (rd32(hw, I40E_GLPCI_LBARCTRL) in i40e_get_eeprom_len()
1981 u64 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | in i40e_set_rss_hash_opt()
1982 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); in i40e_set_rss_hash_opt()
2459 reg_val = rd32(hw, I40E_PFQF_HLUT(i)); in i40e_get_rxfh()
2468 reg_val = rd32(hw, I40E_PFQF_HKEY(i)); in i40e_get_rxfh()
Di40e_dcb.c45 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
Di40e_fcoe.c297 val = rd32(hw, I40E_PFQF_HENA(1)); in i40e_init_pf_fcoe()
319 val = rd32(hw, I40E_GLFCOE_RCTL); in i40e_init_pf_fcoe()
Di40e_txrx.c1909 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); in i40e_napi_poll()
1913 qval = rd32(hw, I40E_QINT_TQCTL(0)); in i40e_napi_poll()
Di40e_debugfs.c1504 value = rd32(&pf->hw, address); in i40e_dbg_command_write()
1523 value = rd32(&pf->hw, address); in i40e_dbg_command_write()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgf100.c58 .rd32 = _nvkm_falcon_context_rd32,
150 .rd32 = _nvkm_falcon_rd32,
163 .rd32 = _nvkm_falcon_rd32,
Dgt215.c59 .rd32 = _nvkm_falcon_context_rd32,
149 .rd32 = _nvkm_falcon_rd32,
Dgk104.c52 .rd32 = _nvkm_engctx_rd32,
Dgm204.c52 .rd32 = _nvkm_engctx_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/vp/
Dg84.c51 .rd32 = _nvkm_engctx_rd32,
90 .rd32 = _nvkm_xtensa_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/bsp/
Dg84.c51 .rd32 = _nvkm_engctx_rd32,
90 .rd32 = _nvkm_xtensa_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
Dg98.c55 .rd32 = _nvkm_falcon_context_rd32,
107 .rd32 = _nvkm_falcon_rd32,
Dgk104.c53 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
Dgf100.c53 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
Dgk104.c53 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
Dg98.c54 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
Dgf100.c53 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
Dg98.c54 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
Dgf100.c53 .rd32 = _nvkm_falcon_context_rd32,
106 .rd32 = _nvkm_falcon_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
Dg98.c58 .rd32 = _nvkm_falcon_context_rd32,
146 .rd32 = _nvkm_falcon_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c67 .rd32 = _nvkm_gpuobj_rd32,
89 .rd32 = _nvkm_engctx_rd32,
/linux-4.1.27/drivers/net/ethernet/intel/i40evf/
Di40evf_main.c190 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_misc_irq_disable()
208 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_misc_irq_enable()
228 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_irq_disable()
263 dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01); in i40evf_fire_sw_int()
271 dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1)); in i40evf_fire_sw_int()
292 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_irq_enable()
309 val = rd32(hw, I40E_VFINT_ICR01); in i40evf_msix_aq()
310 ena_mask = rd32(hw, I40E_VFINT_ICR0_ENA1); in i40evf_msix_aq()
313 val = rd32(hw, I40E_VFINT_DYN_CTL01); in i40evf_msix_aq()
1319 rstat_val = rd32(hw, I40E_VFGEN_RSTAT) & in i40evf_watchdog_task()
[all …]
Di40evf_ethtool.c374 u64 hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) | in i40evf_get_rss_hash_opts()
375 ((u64)rd32(hw, I40E_VFQF_HENA(1)) << 32); in i40evf_get_rss_hash_opts()
461 u64 hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) | in i40evf_set_rss_hash_opt()
462 ((u64)rd32(hw, I40E_VFQF_HENA(1)) << 32); in i40evf_set_rss_hash_opt()
646 hlut_val = rd32(hw, I40E_VFQF_HLUT(i)); in i40evf_get_rxfh()
Di40e_adminq.c316 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
348 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
629 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
632 rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
667 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40evf_asq_done()
696 val = rd32(hw, hw->aq.asq.head); in i40evf_asq_send_command()
902 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); in i40evf_clean_arq_element()
Di40e_osdep.h46 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
Di40e_common.c148 return !!(rd32(hw, hw->aq.asq.len) & in i40evf_check_asq_alive()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv10.c109 .rd32 = _nvkm_fifo_channel_rd32,
132 .rd32 = _nvkm_fifo_context_rd32,
Dnv17.c116 .rd32 = _nvkm_fifo_channel_rd32,
139 .rd32 = _nvkm_fifo_context_rd32,
Dnv40.c235 .rd32 = _nvkm_fifo_channel_rd32,
258 .rd32 = _nvkm_fifo_context_rd32,
Dg84.c335 .rd32 = _nvkm_fifo_channel_rd32,
347 .rd32 = _nvkm_fifo_channel_rd32,
412 .rd32 = _nvkm_fifo_context_rd32,
Dnv50.c361 .rd32 = _nvkm_fifo_channel_rd32,
373 .rd32 = _nvkm_fifo_channel_rd32,
445 .rd32 = _nvkm_fifo_context_rd32,
Dnv04.c250 .rd32 = _nvkm_fifo_channel_rd32,
291 .rd32 = _nvkm_fifo_context_rd32,
Dgf100.c300 .rd32 = _nvkm_fifo_channel_rd32,
364 .rd32 = _nvkm_fifo_context_rd32,
Dgk104.c333 .rd32 = _nvkm_fifo_channel_rd32,
396 .rd32 = _nvkm_fifo_context_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c69 .rd32 = _nvkm_gpuobj_rd32,
113 .rd32 = _nvkm_mpeg_context_rd32,
Dg84.c56 .rd32 = _nvkm_mpeg_context_rd32,
Dnv44.c84 .rd32 = _nvkm_mpeg_context_rd32,
Dnv31.c104 .rd32 = _nvkm_gpuobj_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c100 .rd32 = nv04_instobj_rd32,
189 .rd32 = nv04_instmem_rd32,
Dnv40.c132 .rd32 = nv40_instmem_rd32,
Dnv50.c125 .rd32 = nv50_instobj_rd32,
Dgk20a.c374 .rd32 = gk20a_instobj_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgk20a.c39 .rd32 = _nvkm_gr_context_rd32,
Dctxgk110b.c80 .rd32 = _nvkm_gr_context_rd32,
Dctxgf104.c90 .rd32 = _nvkm_gr_context_rd32,
Dctxgm206.c60 .rd32 = _nvkm_gr_context_rd32,
Dctxgf110.c341 .rd32 = _nvkm_gr_context_rd32,
Dctxgf119.c509 .rd32 = _nvkm_gr_context_rd32,
Dctxgk208.c541 .rd32 = _nvkm_gr_context_rd32,
Dctxgk110.c819 .rd32 = _nvkm_gr_context_rd32,
Dnv2a.c81 .rd32 = _nvkm_gr_context_rd32,
Dctxgf108.c786 .rd32 = _nvkm_gr_context_rd32,
Dnv25.c114 .rd32 = _nvkm_gr_context_rd32,
Dnv35.c115 .rd32 = _nvkm_gr_context_rd32,
Dnv34.c115 .rd32 = _nvkm_gr_context_rd32,
Dnv40.c85 .rd32 = _nvkm_gpuobj_rd32,
196 .rd32 = _nvkm_gr_context_rd32,
Dctxgf117.c263 .rd32 = _nvkm_gr_context_rd32,
Dctxgm204.c1031 .rd32 = _nvkm_gr_context_rd32,
Dnv30.c117 .rd32 = _nvkm_gr_context_rd32,
Dctxgk104.c1001 .rd32 = _nvkm_gr_context_rd32,
Dctxgm107.c1005 .rd32 = _nvkm_gr_context_rd32,
Dnv50.c81 .rd32 = _nvkm_gpuobj_rd32,
168 .rd32 = _nvkm_gr_context_rd32,
Dnv20.c148 .rd32 = _nvkm_gr_context_rd32,
Dctxgf100.c1372 .rd32 = _nvkm_gr_context_rd32,
Dnv04.c980 .rd32 = _nvkm_gpuobj_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgm107.c60 .rd32 = gm107_fuse_rd32,
Dnv50.c74 .rd32 = nv50_fuse_rd32,
Dgf100.c76 .rd32 = gf100_fuse_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dobject.h97 u32 (*rd32)(struct nvkm_object *, u64 offset); member
156 u32 data = nv_ofuncs(obj)->rd32(obj, addr); in nv_ro32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dramht.c84 .rd32 = _nvkm_gpuobj_rd32,
Dgpuobj.c186 return pfuncs->rd32(gpuobj->parent, addr); in _nvkm_gpuobj_rd32()
207 .rd32 = _nvkm_gpuobj_rd32,
Dioctl.c251 if (ret = -ENODEV, ofuncs->rd32) { in nvkm_ioctl_rd()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dbase.c100 .rd32 = nvkm_barobj_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf110.c353 .base.rd32 = nv50_disp_chan_rd32,
447 .base.rd32 = nv50_disp_chan_rd32,
528 .base.rd32 = nv50_disp_chan_rd32,
599 .base.rd32 = nv50_disp_chan_rd32,
616 .base.rd32 = nv50_disp_chan_rd32,
Dnv50.c582 .base.rd32 = nv50_disp_chan_rd32,
684 .base.rd32 = nv50_disp_chan_rd32,
774 .base.rd32 = nv50_disp_chan_rd32,
892 .base.rd32 = nv50_disp_chan_rd32,
940 .base.rd32 = nv50_disp_chan_rd32,
1280 .rd32 = _nvkm_engctx_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Di2c_.fuc291 call(rd32)
298 call(rd32)
Dmacros.fuc229 */ call(rd32) /*
Dkernel.fuc52 rd32:
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dbase.c201 .rd32 = nvkm_bios_rd32,
Dshadow.c87 .rd32 = shadow_rd32,
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c274 .rd32 = nvkm_devobj_rd32,