513 		new_data = rd32(hw, loreg);  in i40e_stat_update48()
514 		new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;  in i40e_stat_update48()
540 	new_data = rd32(hw, reg);  in i40e_stat_update32()
1107 	val = rd32(hw, I40E_PRTPM_EEE_STAT);  in i40e_update_pf_stats()
2864 	rd32(hw, I40E_PFINT_ICR0);         /* read to clear */  in i40e_enable_misc_int_causes()
3153 	icr0 = rd32(hw, I40E_PFINT_ICR0);  in i40e_intr()
3154 	ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_intr()
3169 		u32 qval = rd32(hw, I40E_QINT_RQCTL(0));  in i40e_intr()
3173 		qval = rd32(hw, I40E_QINT_TQCTL(0));  in i40e_intr()
3200 		val = rd32(hw, I40E_GLGEN_RSTAT);  in i40e_intr()
3217 			 rd32(hw, I40E_PFHMC_ERRORINFO),  in i40e_intr()
3218 			 rd32(hw, I40E_PFHMC_ERRORDATA));  in i40e_intr()
3222 		u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);  in i40e_intr()
3508 		tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));  in i40e_pf_txq_wait()
3541 			tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));  in i40e_vsi_control_tx()
3597 		rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));  in i40e_pf_rxq_wait()
3624 			rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));  in i40e_vsi_control_rx()
3721 			val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));  in i40e_vsi_free_irq()
3731 				val = rd32(hw, I40E_QINT_RQCTL(qp));  in i40e_vsi_free_irq()
3743 				val = rd32(hw, I40E_QINT_TQCTL(qp));  in i40e_vsi_free_irq()
3763 		val = rd32(hw, I40E_PFINT_LNKLST0);  in i40e_vsi_free_irq()
3770 		val = rd32(hw, I40E_QINT_RQCTL(qp));  in i40e_vsi_free_irq()
3781 		val = rd32(hw, I40E_QINT_TQCTL(qp));  in i40e_vsi_free_irq()
5074 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_do_reset()
5085 		val = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_do_reset()
5374 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);  in i40e_get_cur_guaranteed_fd_count()
5387 	val = rd32(&pf->hw, I40E_PFQF_FDSTAT);  in i40e_get_current_fd_count()
5402 	val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);  in i40e_get_global_fd_count()
5487 			reg = rd32(&pf->hw, I40E_PFQF_CTL_1);  in i40e_fdir_flush_and_replay()
5842 	val = rd32(&pf->hw, pf->hw.aq.arq.len);  in i40e_clean_adminq_subtask()
5859 	val = rd32(&pf->hw, pf->hw.aq.asq.len);  in i40e_clean_adminq_subtask()
5933 	val = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_clean_adminq_subtask()
6218 	if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {  in i40e_fdir_sb_setup()
6533 	reg = rd32(hw, I40E_GL_MDET_TX);  in i40e_handle_mdd_event()
6550 	reg = rd32(hw, I40E_GL_MDET_RX);  in i40e_handle_mdd_event()
6567 		reg = rd32(hw, I40E_PF_MDET_TX);  in i40e_handle_mdd_event()
6573 		reg = rd32(hw, I40E_PF_MDET_RX);  in i40e_handle_mdd_event()
6589 		reg = rd32(hw, I40E_VP_MDET_TX(i));  in i40e_handle_mdd_event()
6597 		reg = rd32(hw, I40E_VP_MDET_RX(i));  in i40e_handle_mdd_event()
6616 	reg = rd32(hw, I40E_PFINT_ICR0_ENA);  in i40e_handle_mdd_event()
7422 	hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |  in i40e_config_rss()
7423 		((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);  in i40e_config_rss()
7431 	reg_val = rd32(hw, I40E_PFQF_CTL_0);  in i40e_config_rss()
9709 	    (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {  in i40e_probe()
9944 		val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);  in i40e_probe()
10187 		reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);  in i40e_pci_error_slot_reset()