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Searched refs:mmio (Results 1 – 200 of 309) sorted by relevance

12

/linux-4.1.27/sound/pci/au88x0/
Dau88x0_xtalk.c260 hwwrite(vortex->mmio, 0x24200 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetLeftEQ()
261 hwwrite(vortex->mmio, 0x24204 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetLeftEQ()
262 hwwrite(vortex->mmio, 0x24208 + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetLeftEQ()
263 hwwrite(vortex->mmio, 0x2420c + i * 0x24, coefs[i][3]); in vortex_XtalkHw_SetLeftEQ()
264 hwwrite(vortex->mmio, 0x24210 + i * 0x24, coefs[i][4]); in vortex_XtalkHw_SetLeftEQ()
266 hwwrite(vortex->mmio, 0x24538, arg_0 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
267 hwwrite(vortex->mmio, 0x2453C, arg_4 & 0xffff); in vortex_XtalkHw_SetLeftEQ()
277 hwwrite(vortex->mmio, 0x242b4 + i * 0x24, coefs[i][0]); in vortex_XtalkHw_SetRightEQ()
278 hwwrite(vortex->mmio, 0x242b8 + i * 0x24, coefs[i][1]); in vortex_XtalkHw_SetRightEQ()
279 hwwrite(vortex->mmio, 0x242bc + i * 0x24, coefs[i][2]); in vortex_XtalkHw_SetRightEQ()
[all …]
Dau88x0_core.c91 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_en_sr()
92 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel)); in vortex_mixer_en_sr()
96 hwwrite(vortex->mmio, VORTEX_MIXER_SR, in vortex_mixer_dis_sr()
97 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel)); in vortex_mixer_dis_sr()
105 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
107 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
114 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
126 a = hwread(vortex->mmio,
151 a = hwread(vortex->mmio,
155 hwwrite(vortex->mmio,
[all …]
Dau88x0_mpu401.c56 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) | in snd_vortex_midi()
58 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
62 (hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_PORT) & in snd_vortex_midi()
64 hwwrite(vortex->mmio, VORTEX_CTRL, temp); in snd_vortex_midi()
68 temp = hwread(vortex->mmio, VORTEX_CTRL2) & 0xffff00cf; in snd_vortex_midi()
70 hwwrite(vortex->mmio, VORTEX_CTRL2, temp); in snd_vortex_midi()
71 hwwrite(vortex->mmio, VORTEX_MIDI_CMD, MPU401_RESET); in snd_vortex_midi()
74 temp = hwread(vortex->mmio, VORTEX_MIDI_DATA); in snd_vortex_midi()
80 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, in snd_vortex_midi()
81 hwread(vortex->mmio, VORTEX_IRQ_CTRL) | IRQ_MIDI); in snd_vortex_midi()
[all …]
Dau88x0_synth.c45 temp = hwread(vortex->mmio, WT_STEREO(wt)); in vortex_wt_setstereo()
48 hwwrite(vortex->mmio, WT_STEREO(wt), temp); in vortex_wt_setstereo()
57 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0)); in vortex_wt_setdsout()
62 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp); in vortex_wt_setdsout()
82 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000); in vortex_wt_allocroute()
85 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000); in vortex_wt_allocroute()
88 hwwrite(vortex->mmio, WT_PARM(wt, 0), 0); in vortex_wt_allocroute()
89 hwwrite(vortex->mmio, WT_PARM(wt, 1), 0); in vortex_wt_allocroute()
90 hwwrite(vortex->mmio, WT_PARM(wt, 2), 0); in vortex_wt_allocroute()
92 temp = hwread(vortex->mmio, WT_PARM(wt, 3)); in vortex_wt_allocroute()
[all …]
Dau88x0_eq.c53 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
54 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
72 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
73 hwwrite(vortex->mmio, 0x2b004 + n * 0x30, coefs[i + 1]); in vortex_EqHw_SetLeftCoefs()
76 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, coefs[i + 2]); in vortex_EqHw_SetLeftCoefs()
77 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, coefs[i + 3]); in vortex_EqHw_SetLeftCoefs()
78 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, coefs[i + 4]); in vortex_EqHw_SetLeftCoefs()
80 hwwrite(vortex->mmio, 0x2b008 + n * 0x30, sign_invert(coefs[2 + i])); in vortex_EqHw_SetLeftCoefs()
81 hwwrite(vortex->mmio, 0x2b00c + n * 0x30, sign_invert(coefs[3 + i])); in vortex_EqHw_SetLeftCoefs()
82 hwwrite(vortex->mmio, 0x2b010 + n * 0x30, sign_invert(coefs[4 + i])); in vortex_EqHw_SetLeftCoefs()
[all …]
Dau88x0_a3d.c37 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
39 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
41 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
43 hwwrite(vortex->mmio, in a3dsrc_SetTimeConsts()
63 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
66 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
69 hwwrite(vortex->mmio, in a3dsrc_SetAtmosTarget()
78 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
81 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
84 hwwrite(vortex->mmio, in a3dsrc_SetAtmosCurrent()
[all …]
Dau88x0_game.c46 return hwread(vortex->mmio, VORTEX_GAME_LEGACY); in vortex_game_read()
52 hwwrite(vortex->mmio, VORTEX_GAME_LEGACY, 0xff); in vortex_game_trigger()
61 *buttons = (~hwread(vortex->mmio, VORTEX_GAME_LEGACY) >> 4) & 0xf; in vortex_game_cooked_read()
65 hwread(vortex->mmio, VORTEX_GAME_AXIS + (i * AXIS_SIZE)); in vortex_game_cooked_read()
78 hwwrite(vortex->mmio, VORTEX_CTRL2, in vortex_game_open()
79 hwread(vortex->mmio, in vortex_game_open()
84 hwwrite(vortex->mmio, VORTEX_CTRL2, in vortex_game_open()
85 hwread(vortex->mmio, in vortex_game_open()
Dau88x0.c129 iounmap(vortex->mmio); in snd_vortex_dev_free()
182 chip->mmio = pci_ioremap_bar(pci, 0); in snd_vortex_create()
183 if (!chip->mmio) { in snd_vortex_create()
222 iounmap(chip->mmio); in snd_vortex_create()
/linux-4.1.27/sound/soc/nuc900/
Dnuc900-ac97.c37 if (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS0) & CODEC_READY)) in nuc900_checkready()
59 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, R_WB | reg); in nuc900_ac97_read()
62 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0); in nuc900_ac97_read()
64 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); in nuc900_ac97_read()
69 while (!(AUDIO_READ(nuc900_audio->mmio + ACTL_ACCON) & AC_R_FINISH) in nuc900_ac97_read()
79 val = AUDIO_READ(nuc900_audio->mmio + ACTL_ACOS0) ; in nuc900_ac97_read()
81 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS0, val); in nuc900_ac97_read()
83 if (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS1) >> 2 != reg) { in nuc900_ac97_read()
89 val = (AUDIO_READ(nuc900_audio->mmio + ACTL_ACIS2) & 0xFFFF); in nuc900_ac97_read()
110 AUDIO_WRITE(nuc900_audio->mmio + ACTL_ACOS1, reg); in nuc900_ac97_write()
[all …]
Dnuc900-pcm.c55 mmio_addr = nuc900_audio->mmio + ACTL_PDSTB; in nuc900_update_dma_register()
56 mmio_len = nuc900_audio->mmio + ACTL_PDST_LENGTH; in nuc900_update_dma_register()
58 mmio_addr = nuc900_audio->mmio + ACTL_RDSTB; in nuc900_update_dma_register()
59 mmio_len = nuc900_audio->mmio + ACTL_RDST_LENGTH; in nuc900_update_dma_register()
72 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_start()
74 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); in nuc900_dma_start()
83 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_stop()
85 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val); in nuc900_dma_stop()
96 val = AUDIO_READ(nuc900_audio->mmio + ACTL_CON); in nuc900_dma_interrupt()
99 AUDIO_WRITE(nuc900_audio->mmio + ACTL_CON, val | R_DMA_IRQ); in nuc900_dma_interrupt()
[all …]
Dnuc900-audio.h101 void __iomem *mmio; member
/linux-4.1.27/drivers/video/fbdev/i810/
Di810_main.c166 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
171 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
172 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
176 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
177 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
178 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
190 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
194 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
197 i810_writeb(DRAMCH, mmio, val); in i810_dram_off()
209 static void i810_protect_regs(u8 __iomem *mmio, int mode) in i810_protect_regs() argument
[all …]
Di810-i2c.c46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl() local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda() local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl() local
74 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
[all …]
Di810_accel.c36 static inline void i810_report_error(u8 __iomem *mmio) in i810_report_error() argument
43 i810_readw(IIR, mmio), in i810_report_error()
44 i810_readb(EIR, mmio), in i810_report_error()
45 i810_readl(PGTBL_ER, mmio), in i810_report_error()
46 i810_readl(IPEIR, mmio), in i810_report_error()
47 i810_readl(IPEHR, mmio)); in i810_report_error()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space() local
67 head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK; in wait_for_space()
76 i810_report_error(mmio); in wait_for_space()
93 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_engine_idle() local
[all …]
Di810.h292 #define i810_readb(where, mmio) readb(mmio + where) argument
293 #define i810_readw(where, mmio) readw(mmio + where) argument
294 #define i810_readl(where, mmio) readl(mmio + where) argument
295 #define i810_writeb(where, mmio, val) writeb(val, mmio + where) argument
296 #define i810_writew(where, mmio, val) writew(val, mmio + where) argument
297 #define i810_writel(where, mmio, val) writel(val, mmio + where) argument
Di810_gtf.c128 u8 __iomem *mmio = par->mmio_start_virtual; in i810fb_encode_registers() local
168 par->regs.cr11 = i810_readb(CR11, mmio) & ~0x0F; in i810fb_encode_registers()
/linux-4.1.27/drivers/net/ethernet/amd/
Damd8111e.c115 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
119 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
121 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_read_phy()
124 ((reg & 0x1f) << 16), mmio +PHY_ACCESS); in amd8111e_read_phy()
126 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
145 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
148 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
150 reg_val = readl( mmio + PHY_ACCESS ); in amd8111e_write_phy()
153 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
156 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
[all …]
/linux-4.1.27/drivers/staging/comedi/drivers/
Dni_pcidio.c314 dev->mmio + DMA_Line_Control_Group1); in ni_pcidio_request_di_mite_channel()
333 dev->mmio + DMA_Line_Control_Group1); in ni_pcidio_release_di_mite_channel()
402 status = readb(dev->mmio + Interrupt_And_Window_Status); in nidio_interrupt()
403 flags = readb(dev->mmio + Group_1_Flags); in nidio_interrupt()
432 dev->mmio + Master_DMA_And_Interrupt_Control); in nidio_interrupt()
444 writeb(0x00, dev->mmio + in nidio_interrupt()
449 auxdata = readl(dev->mmio + Group_1_FIFO); in nidio_interrupt()
451 flags = readb(dev->mmio + Group_1_Flags); in nidio_interrupt()
456 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear); in nidio_interrupt()
459 writeb(0x00, dev->mmio + OpMode); in nidio_interrupt()
[all …]
Drtd520.c485 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
486 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
489 dev->mmio + LAS0_CGT_WRITE); in rtd_load_channelgain_list()
492 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
494 dev->mmio + LAS0_CGL_WRITE); in rtd_load_channelgain_list()
507 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
510 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
515 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
517 fifo_status = readl(dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
527 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
[all …]
Dni_6527.c99 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0)); in ni6527_set_filter_interval()
101 dev->mmio + NI6527_FILT_INTERVAL_REG(1)); in ni6527_set_filter_interval()
103 dev->mmio + NI6527_FILT_INTERVAL_REG(2)); in ni6527_set_filter_interval()
105 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG); in ni6527_set_filter_interval()
114 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0)); in ni6527_set_filter_enable()
115 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1)); in ni6527_set_filter_enable()
116 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2)); in ni6527_set_filter_enable()
160 val = readb(dev->mmio + NI6527_DI_REG(0)); in ni6527_di_insn_bits()
161 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8); in ni6527_di_insn_bits()
162 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16); in ni6527_di_insn_bits()
[all …]
Dme_daq.c208 writew(devpriv->control_2, dev->mmio + ME_CONTROL_2); in me_dio_insn_config()
218 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A; in me_dio_insn_bits()
219 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B; in me_dio_insn_bits()
253 status = readw(dev->mmio + ME_STATUS); in me_ai_eoc()
273 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1); in me_ai_insn_read()
277 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2); in me_ai_insn_read()
280 writew(0x00, dev->mmio + ME_RESET_INTERRUPT); in me_ai_insn_read()
284 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2); in me_ai_insn_read()
291 writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST); in me_ai_insn_read()
295 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1); in me_ai_insn_read()
[all …]
Dicp_multi.c163 writew(devpriv->AdcCmdStatus, dev->mmio + ICP_MULTI_ADC_CSR); in setup_channel_list()
174 status = readw(dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_eoc()
191 writew(devpriv->IntEnable, dev->mmio + ICP_MULTI_INT_EN); in icp_multi_insn_read_ai()
195 writew(devpriv->IntStatus, dev->mmio + ICP_MULTI_INT_STAT); in icp_multi_insn_read_ai()
203 writew(devpriv->AdcCmdStatus, dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_insn_read_ai()
213 data[n] = (readw(dev->mmio + ICP_MULTI_AI) >> 4) & 0x0fff; in icp_multi_insn_read_ai()
218 writew(devpriv->IntEnable, dev->mmio + ICP_MULTI_INT_EN); in icp_multi_insn_read_ai()
222 writew(devpriv->IntStatus, dev->mmio + ICP_MULTI_INT_STAT); in icp_multi_insn_read_ai()
234 status = readw(dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_eoc()
252 writew(devpriv->IntEnable, dev->mmio + ICP_MULTI_INT_EN); in icp_multi_ao_insn_write()
[all …]
Ddt3000.c256 writew(cmd, dev->mmio + DPR_Command_Mbx); in dt3k_send_cmd()
259 status = readw(dev->mmio + DPR_Command_Mbx); in dt3k_send_cmd()
274 writew(subsys, dev->mmio + DPR_SubSys); in dt3k_readsingle()
276 writew(chan, dev->mmio + DPR_Params(0)); in dt3k_readsingle()
277 writew(gain, dev->mmio + DPR_Params(1)); in dt3k_readsingle()
281 return readw(dev->mmio + DPR_Params(2)); in dt3k_readsingle()
287 writew(subsys, dev->mmio + DPR_SubSys); in dt3k_writesingle()
289 writew(chan, dev->mmio + DPR_Params(0)); in dt3k_writesingle()
290 writew(0, dev->mmio + DPR_Params(1)); in dt3k_writesingle()
291 writew(data, dev->mmio + DPR_Params(2)); in dt3k_writesingle()
[all …]
Ddaqboard2000.c282 writew(entry & 0x00ff, dev->mmio + acqScanListFIFO); in writeAcqScanListEntry()
284 writew((entry >> 8) & 0x00ff, dev->mmio + acqScanListFIFO); in writeAcqScanListEntry()
338 status = readw(dev->mmio + acqControl); in daqboard2000_ai_status()
355 DAQBOARD2000_AcqResetConfigPipe, dev->mmio + acqControl); in daqboard2000_ai_insn_read()
362 writel(1000000, dev->mmio + acqPacerClockDivLow); in daqboard2000_ai_insn_read()
363 writew(0, dev->mmio + acqPacerClockDivHigh); in daqboard2000_ai_insn_read()
375 writew(DAQBOARD2000_SeqStartScanList, dev->mmio + acqControl); in daqboard2000_ai_insn_read()
382 writew(DAQBOARD2000_AdcPacerEnable, dev->mmio + acqControl); in daqboard2000_ai_insn_read()
394 data[i] = readw(dev->mmio + acqResultsFIFO); in daqboard2000_ai_insn_read()
395 writew(DAQBOARD2000_AdcPacerDisable, dev->mmio + acqControl); in daqboard2000_ai_insn_read()
[all …]
Dni_65xx.c292 writeb(0x00, dev->mmio + NI_65XX_FILTER_ENA(i)); in ni_65xx_disable_input_filters()
295 writel(0x00000000, dev->mmio + NI_65XX_FILTER_REG); in ni_65xx_disable_input_filters()
329 readb(dev->mmio + in ni_65xx_update_edge_detection()
333 readb(dev->mmio + in ni_65xx_update_edge_detection()
338 dev->mmio + NI_65XX_RISE_EDGE_ENA_REG(port)); in ni_65xx_update_edge_detection()
340 dev->mmio + NI_65XX_FALL_EDGE_ENA_REG(port)); in ni_65xx_update_edge_detection()
384 val = readb(dev->mmio + NI_65XX_FILTER_ENA(port)); in ni_65xx_dio_insn_config()
386 writel(interval, dev->mmio + NI_65XX_FILTER_REG); in ni_65xx_dio_insn_config()
391 writeb(val, dev->mmio + NI_65XX_FILTER_ENA(port)); in ni_65xx_dio_insn_config()
398 dev->mmio + NI_65XX_IO_SEL_REG(port)); in ni_65xx_dio_insn_config()
[all …]
Ds626.c113 writel(val, dev->mmio + reg); in s626_mc_enable()
119 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
128 val = readl(dev->mmio + reg); in s626_mc_test()
171 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) in s626_debi_transfer()
185 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_read()
190 return readl(dev->mmio + S626_P_DEBIAD); in s626_debi_read()
200 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_write()
201 writel(wdata, dev->mmio + S626_P_DEBIAD); in s626_debi_write()
218 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
221 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
[all …]
Dcomedi_8254.c141 if (i8254->mmio) in __i8254_read()
142 val = readb(i8254->mmio + reg_offset); in __i8254_read()
147 if (i8254->mmio) in __i8254_read()
148 val = readw(i8254->mmio + reg_offset); in __i8254_read()
153 if (i8254->mmio) in __i8254_read()
154 val = readl(i8254->mmio + reg_offset); in __i8254_read()
170 if (i8254->mmio) in __i8254_write()
171 writeb(val, i8254->mmio + reg_offset); in __i8254_write()
176 if (i8254->mmio) in __i8254_write()
177 writew(val, i8254->mmio + reg_offset); in __i8254_write()
[all …]
Dii_pci20kc.c138 return dev->mmio + (s->index + 1) * II20K_MOD_OFFSET; in ii20k_module_iobase()
314 writeb(ctrl01, dev->mmio + II20K_CTRL01_REG); in ii20k_dio_config()
315 writeb(ctrl23, dev->mmio + II20K_CTRL23_REG); in ii20k_dio_config()
316 writeb(dir_ena, dev->mmio + II20K_DIR_ENA_REG); in ii20k_dio_config()
357 dev->mmio + II20K_DIO0_REG); in ii20k_dio_insn_bits()
360 dev->mmio + II20K_DIO1_REG); in ii20k_dio_insn_bits()
363 dev->mmio + II20K_DIO2_REG); in ii20k_dio_insn_bits()
366 dev->mmio + II20K_DIO3_REG); in ii20k_dio_insn_bits()
369 data[1] = readb(dev->mmio + II20K_DIO0_REG); in ii20k_dio_insn_bits()
370 data[1] |= readb(dev->mmio + II20K_DIO1_REG) << 8; in ii20k_dio_insn_bits()
[all …]
Daddi_apci_3xxx.c365 status = readl(dev->mmio + 16); in apci3xxx_irq_handler()
368 writel(status, dev->mmio + 16); in apci3xxx_irq_handler()
370 val = readl(dev->mmio + 28); in apci3xxx_irq_handler()
383 if ((readl(dev->mmio + 8) & 0x80000) == 0x80000) in apci3xxx_ai_started()
401 writel(0x10000, dev->mmio + 12); in apci3xxx_ai_setup()
404 delay_mode = readl(dev->mmio + 4); in apci3xxx_ai_setup()
408 writel(delay_mode, dev->mmio + 4); in apci3xxx_ai_setup()
413 writel(val, dev->mmio + 0); in apci3xxx_ai_setup()
416 writel(delay_mode | 0x100, dev->mmio + 4); in apci3xxx_ai_setup()
417 writel(chan, dev->mmio + 0); in apci3xxx_ai_setup()
[all …]
Dni_670x.c110 dev->mmio + AO_CHAN_OFFSET); in ni_670x_ao_insn_write()
112 writel(val, dev->mmio + AO_VALUE_OFFSET); in ni_670x_ao_insn_write()
125 writel(s->state, dev->mmio + DIO_PORT0_DATA_OFFSET); in ni_670x_dio_insn_bits()
127 data[1] = readl(dev->mmio + DIO_PORT0_DATA_OFFSET); in ni_670x_dio_insn_bits()
143 writel(s->io_bits, dev->mmio + DIO_PORT0_DIR_OFFSET); in ni_670x_dio_insn_config()
200 dev->mmio = pci_ioremap_bar(pcidev, 1); in ni_670x_auto_attach()
201 if (!dev->mmio) in ni_670x_auto_attach()
246 writel(0x10, dev->mmio + MISC_CONTROL_OFFSET); in ni_670x_auto_attach()
248 writel(0x00, dev->mmio + AO_CONTROL_OFFSET); in ni_670x_auto_attach()
Dgsc_hpdi.c227 hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG); in gsc_hpdi_interrupt()
228 hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG); in gsc_hpdi_interrupt()
231 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG); in gsc_hpdi_interrupt()
294 writel(0, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cancel()
295 writel(0, dev->mmio + INTERRUPT_CONTROL_REG); in gsc_hpdi_cancel()
314 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cmd()
347 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG); in gsc_hpdi_cmd()
350 writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG); in gsc_hpdi_cmd()
352 writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cmd()
538 writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_init()
[all …]
Dmf6x4.c110 data[1] = ioread16(dev->mmio + MF6X4_DIN_R) & MF6X4_DIN_M; in mf6x4_di_insn_bits()
121 iowrite16(s->state & MF6X4_DOUT_M, dev->mmio + MF6X4_DOUT_R); in mf6x4_do_insn_bits()
153 iowrite16((1 << chan) & MF6X4_ADCTRL_M, dev->mmio + MF6X4_ADCTRL_R); in mf6x4_ai_insn_read()
157 ioread16(dev->mmio + MF6X4_ADSTART_R); in mf6x4_ai_insn_read()
164 d = ioread16(dev->mmio + MF6X4_ADDATA_R); in mf6x4_ai_insn_read()
169 iowrite16(0x0, dev->mmio + MF6X4_ADCTRL_R); in mf6x4_ai_insn_read()
192 iowrite16(val, dev->mmio + MF6X4_DAC_R(chan)); in mf6x4_ao_insn_write()
227 dev->mmio = pci_ioremap_bar(pcidev, board->bar_nums[1]); in mf6x4_auto_attach()
228 if (!dev->mmio) in mf6x4_auto_attach()
Damplc_dio200_common.c119 if (dev->mmio) in dio200_read8()
120 return readb(dev->mmio + offset); in dio200_read8()
132 if (dev->mmio) in dio200_write8()
133 writeb(val, dev->mmio + offset); in dio200_write8()
146 if (dev->mmio) in dio200_read32()
147 return readl(dev->mmio + offset); in dio200_read32()
159 if (dev->mmio) in dio200_write32()
160 writel(val, dev->mmio + offset); in dio200_write32()
173 if (dev->mmio) in dio200_subdev_8254_offset()
174 offset = i8254->mmio - dev->mmio; in dio200_subdev_8254_offset()
[all …]
Dcomedi_8254.h81 void __iomem *mmio; member
128 struct comedi_8254 *comedi_8254_mm_init(void __iomem *mmio,
D8255_pci.c230 dev->mmio = pci_ioremap_bar(pcidev, board->dio_badr); in pci_8255_auto_attach()
231 if (!dev->mmio) in pci_8255_auto_attach()
248 if (dev->mmio) in pci_8255_auto_attach()
Dni_labpc_pci.c98 dev->mmio = pci_ioremap_bar(pcidev, 1); in labpc_pci_auto_attach()
99 if (!dev->mmio) in labpc_pci_auto_attach()
Damplc_dio200_pci.c370 dev->mmio = pci_ioremap_bar(pci_dev, bar); in dio200_pci_auto_attach()
371 if (!dev->mmio) { in dio200_pci_auto_attach()
D8255.c75 writeb(data, dev->mmio + regbase + port); in subdev_8255_mmio()
78 return readb(dev->mmio + regbase + port); in subdev_8255_mmio()
Dni_660x.c591 writew(bits, dev->mmio + addr); in ni_660x_write_register()
594 writel(bits, dev->mmio + addr); in ni_660x_write_register()
610 return readw(dev->mmio + addr); in ni_660x_read_register()
612 return readl(dev->mmio + addr); in ni_660x_read_register()
1184 if (dev->mmio) in ni_660x_detach()
1185 iounmap(dev->mmio); in ni_660x_detach()
Dni_labpc_common.c102 return readb(dev->mmio + reg); in labpc_readb()
108 writeb(byte, dev->mmio + reg); in labpc_writeb()
1192 if (dev->mmio) { in labpc_common_attach()
1217 if (dev->mmio) { in labpc_common_attach()
1218 dev->pacer = comedi_8254_mm_init(dev->mmio + COUNTER_B_BASE_REG, in labpc_common_attach()
1221 devpriv->counter = comedi_8254_mm_init(dev->mmio + in labpc_common_attach()
1282 if (dev->mmio) in labpc_common_attach()
/linux-4.1.27/drivers/ata/
Dsata_sx4.c458 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
469 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
518 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
526 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
569 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; in __pdc20621_push_hdma() local
572 mmio += PDC_CHIP0_OFS; in __pdc20621_push_hdma()
574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma()
575 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
[all …]
Dahci_imx.c78 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
85 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
90 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
94 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
103 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
109 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
112 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
117 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
124 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
130 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
Dsata_nv.c608 void __iomem *mmio = pp->ctl_block; in nv_adma_register_mode() local
615 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
618 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
625 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_register_mode()
626 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_register_mode()
629 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
632 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
646 void __iomem *mmio = pp->ctl_block; in nv_adma_mode() local
655 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_mode()
656 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_mode()
[all …]
Dahci_mvebu.c37 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
38 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
39 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
47 hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
50 hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
61 writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); in ahci_mvebu_regret_option()
62 writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); in ahci_mvebu_regret_option()
Dahci_xgene.c276 void __iomem *mmio = ctx->hpriv->mmio; in xgene_ahci_set_phy_cfg() local
280 mmio, channel); in xgene_ahci_set_phy_cfg()
281 val = readl(mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
283 writel(val, mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
284 readl(mmio + PORTCFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
286 writel(0x0001fffe, mmio + PORTPHY1CFG); in xgene_ahci_set_phy_cfg()
287 readl(mmio + PORTPHY1CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
288 writel(0x28183219, mmio + PORTPHY2CFG); in xgene_ahci_set_phy_cfg()
289 readl(mmio + PORTPHY2CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
290 writel(0x13081008, mmio + PORTPHY3CFG); in xgene_ahci_set_phy_cfg()
[all …]
Dsata_mv.c590 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
592 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
594 void __iomem *mmio);
595 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
597 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
598 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
617 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
619 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
621 void __iomem *mmio);
622 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
[all …]
Dlibahci.c201 static void ahci_enable_ahci(void __iomem *mmio) in ahci_enable_ahci() argument
207 tmp = readl(mmio + HOST_CTL); in ahci_enable_ahci()
216 writel(tmp, mmio + HOST_CTL); in ahci_enable_ahci()
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ in ahci_enable_ahci()
252 void __iomem *mmio = hpriv->mmio; in ahci_show_host_version() local
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); in ahci_show_host_version()
273 void __iomem *mmio = hpriv->mmio; in ahci_read_em_buffer() local
274 void __iomem *em_mmio = mmio + hpriv->em_loc; in ahci_read_em_buffer()
282 em_ctl = readl(mmio + HOST_EM_CTL); in ahci_read_em_buffer()
329 void __iomem *mmio = hpriv->mmio; in ahci_store_em_buffer() local
[all …]
Dsata_svw.c144 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; in k2_sata_softreset() local
146 dmactl = readb(mmio + ATA_DMA_CMD); in k2_sata_softreset()
151 writeb(dmactl, mmio + ATA_DMA_CMD); in k2_sata_softreset()
161 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; in k2_sata_hardreset() local
163 dmactl = readb(mmio + ATA_DMA_CMD); in k2_sata_hardreset()
168 writeb(dmactl, mmio + ATA_DMA_CMD); in k2_sata_hardreset()
251 void __iomem *mmio = ap->ioaddr.bmdma_addr; in k2_bmdma_setup_mmio() local
255 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS); in k2_bmdma_setup_mmio()
258 dmactl = readb(mmio + ATA_DMA_CMD); in k2_bmdma_setup_mmio()
262 writeb(dmactl, mmio + ATA_DMA_CMD); in k2_bmdma_setup_mmio()
[all …]
Dahci_st.c42 static void st_ahci_configure_oob(void __iomem *mmio) in st_ahci_configure_oob() argument
51 old_val = readl(mmio + ST_AHCI_OOBR); in st_ahci_configure_oob()
52 writel(old_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR); in st_ahci_configure_oob()
53 writel(new_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR); in st_ahci_configure_oob()
54 writel(new_val, mmio + ST_AHCI_OOBR); in st_ahci_configure_oob()
171 st_ahci_configure_oob(hpriv->mmio); in st_ahci_probe()
224 st_ahci_configure_oob(hpriv->mmio); in st_ahci_resume()
Dpata_ixp4xx_cf.c50 void __iomem *mmio = ap->ioaddr.data_addr; in ixp4xx_mmio_data_xfer() local
62 buf16[i] = readw(mmio); in ixp4xx_mmio_data_xfer()
65 writew(buf16[i], mmio); in ixp4xx_mmio_data_xfer()
73 align_buf[0] = readw(mmio); in ixp4xx_mmio_data_xfer()
77 writew(align_buf[0], mmio); in ixp4xx_mmio_data_xfer()
Dlibahci_platform.c366 hpriv->mmio = devm_ioremap_resource(dev, in ahci_platform_get_resources()
368 if (IS_ERR(hpriv->mmio)) { in ahci_platform_get_resources()
370 rc = PTR_ERR(hpriv->mmio); in ahci_platform_get_resources()
618 void __iomem *mmio = hpriv->mmio; in ahci_platform_suspend_host() local
631 ctl = readl(mmio + HOST_CTL); in ahci_platform_suspend_host()
633 writel(ctl, mmio + HOST_CTL); in ahci_platform_suspend_host()
634 readl(mmio + HOST_CTL); /* flush */ in ahci_platform_suspend_host()
Dpata_platform.c108 unsigned int mmio; in __pata_platform_probe() local
115 mmio = (( io_res->flags == IORESOURCE_MEM) && in __pata_platform_probe()
149 if (mmio) { in __pata_platform_probe()
169 ata_port_desc(ap, "%s cmd 0x%llx ctl 0x%llx", mmio ? "mmio" : "ioport", in __pata_platform_probe()
Dacard-ahci.c132 void __iomem *mmio = hpriv->mmio; in acard_ahci_pci_device_suspend() local
147 ctl = readl(mmio + HOST_CTL); in acard_ahci_pci_device_suspend()
149 writel(ctl, mmio + HOST_CTL); in acard_ahci_pci_device_suspend()
150 readl(mmio + HOST_CTL); /* flush */ in acard_ahci_pci_device_suspend()
441 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; in acard_ahci_init_one()
Dsata_sis.c297 void __iomem *mmio; in sis_init_one() local
302 mmio = host->iomap[SIS_SCR_PCI_BAR]; in sis_init_one()
304 host->ports[0]->ioaddr.scr_addr = mmio; in sis_init_one()
305 host->ports[1]->ioaddr.scr_addr = mmio + port2_start; in sis_init_one()
Dahci.h324 void __iomem * mmio; /* bus-independent mem map */ member
404 void __iomem *mmio = hpriv->mmio; in __ahci_port_base() local
406 return mmio + 0x100 + (port_no * 0x80); in __ahci_port_base()
Dsata_highbank.c504 hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); in ahci_highbank_probe()
505 if (!hpriv->mmio) { in ahci_highbank_probe()
510 rc = highbank_initialize_phys(dev, hpriv->mmio); in ahci_highbank_probe()
585 void __iomem *mmio = hpriv->mmio; in ahci_highbank_suspend() local
599 ctl = readl(mmio + HOST_CTL); in ahci_highbank_suspend()
601 writel(ctl, mmio + HOST_CTL); in ahci_highbank_suspend()
602 readl(mmio + HOST_CTL); /* flush */ in ahci_highbank_suspend()
Dahci_sunxi.c161 sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400); in ahci_sunxi_start_engine()
194 rc = ahci_sunxi_phy_init(dev, hpriv->mmio); in ahci_sunxi_probe()
232 rc = ahci_sunxi_phy_init(dev, hpriv->mmio); in ahci_sunxi_resume()
Dpata_ns87415.c183 void __iomem *mmio = ap->ioaddr.bmdma_addr; in ns87415_irq_clear() local
185 if (!mmio) in ns87415_irq_clear()
187 iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR), in ns87415_irq_clear()
188 mmio + ATA_DMA_CMD); in ns87415_irq_clear()
Dpata_hpt3x3.c100 void __iomem *mmio = ap->ioaddr.bmdma_addr; in hpt3x3_freeze() local
102 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START, in hpt3x3_freeze()
103 mmio + ATA_DMA_CMD); in hpt3x3_freeze()
Dsata_sil.c414 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); in sil_scr_read() local
416 if (mmio) { in sil_scr_read()
417 *val = readl(mmio); in sil_scr_read()
425 void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); in sil_scr_write() local
427 if (mmio) { in sil_scr_write()
428 writel(val, mmio); in sil_scr_write()
Data_piix.c1289 void __iomem *mmio; in piix_disable_ahci() local
1301 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); in piix_disable_ahci()
1302 if (!mmio) in piix_disable_ahci()
1305 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); in piix_disable_ahci()
1308 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); in piix_disable_ahci()
1310 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); in piix_disable_ahci()
1315 pci_iounmap(pdev, mmio); in piix_disable_ahci()
Dahci_da850.c92 da850_sata_init(dev, pwrdn_reg, hpriv->mmio); in ahci_da850_probe()
/linux-4.1.27/sound/soc/au1x/
Dpsc.h17 void __iomem *mmio; member
30 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET)
31 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET)
32 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET)
33 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET)
34 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET)
35 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET)
36 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET)
37 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET)
38 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET)
[all …]
Di2sc.c71 return __raw_readl(ctx->mmio + reg); in RD()
76 __raw_writel(v, ctx->mmio + reg); in WR()
250 ctx->mmio = devm_ioremap_nocache(&pdev->dev, iores->start, in au1xi2s_drvprobe()
252 if (!ctx->mmio) in au1xi2s_drvprobe()
Dac97c.c73 return __raw_readl(ctx->mmio + reg); in RD()
78 __raw_writel(v, ctx->mmio + reg); in WR()
250 ctx->mmio = devm_ioremap_nocache(&pdev->dev, iores->start, in au1xac97c_drvprobe()
252 if (!ctx->mmio) in au1xac97c_drvprobe()
Dpsc-ac97.c382 wd->mmio = devm_ioremap_resource(&pdev->dev, iores); in au1xpsc_ac97_drvprobe()
383 if (IS_ERR(wd->mmio)) in au1xpsc_ac97_drvprobe()
384 return PTR_ERR(wd->mmio); in au1xpsc_ac97_drvprobe()
/linux-4.1.27/virt/kvm/arm/
Dvgic-v2-emul.c44 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_misc() argument
52 vgic_reg_access(mmio, &reg, word_offset, in handle_mmio_misc()
54 if (mmio->is_write) { in handle_mmio_misc()
64 vgic_reg_access(mmio, &reg, word_offset, in handle_mmio_misc()
70 vgic_reg_access(mmio, &reg, word_offset, in handle_mmio_misc()
79 struct kvm_exit_mmio *mmio, in handle_mmio_set_enable_reg() argument
82 return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, in handle_mmio_set_enable_reg()
87 struct kvm_exit_mmio *mmio, in handle_mmio_clear_enable_reg() argument
90 return vgic_handle_enable_reg(vcpu->kvm, mmio, offset, in handle_mmio_clear_enable_reg()
95 struct kvm_exit_mmio *mmio, in handle_mmio_set_pending_reg() argument
[all …]
Dvgic-v3-emul.c53 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_rao_wi() argument
57 vgic_reg_access(mmio, &reg, offset, in handle_mmio_rao_wi()
64 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_ctlr() argument
76 vgic_reg_access(mmio, &reg, offset, in handle_mmio_ctlr()
78 if (mmio->is_write) { in handle_mmio_ctlr()
96 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_typer() argument
104 vgic_reg_access(mmio, &reg, offset, in handle_mmio_typer()
111 struct kvm_exit_mmio *mmio, phys_addr_t offset) in handle_mmio_iidr() argument
116 vgic_reg_access(mmio, &reg, offset, in handle_mmio_iidr()
123 struct kvm_exit_mmio *mmio, in handle_mmio_set_enable_reg_dist() argument
[all …]
Dvgic.h70 void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
72 bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
76 u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) in mmio_data_read() argument
78 return le32_to_cpu(*((u32 *)mmio->data)) & mask; in mmio_data_read()
82 void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value) in mmio_data_write() argument
84 *((u32 *)mmio->data) = cpu_to_le32(value) & mask; in mmio_data_write()
91 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
110 bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
113 bool vgic_handle_set_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
116 bool vgic_handle_clear_pending_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio,
[all …]
Dvgic.c394 void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, in vgic_reg_access() argument
398 u32 mask = (1UL << (mmio->len * 8)) - 1; in vgic_reg_access()
413 if (mmio->is_write) { in vgic_reg_access()
414 u32 data = mmio_data_read(mmio, mask) << word_offset; in vgic_reg_access()
439 mmio_data_write(mmio, mask, regval >> word_offset); in vgic_reg_access()
444 bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, in handle_mmio_raz_wi() argument
447 vgic_reg_access(mmio, NULL, offset, in handle_mmio_raz_wi()
452 bool vgic_handle_enable_reg(struct kvm *kvm, struct kvm_exit_mmio *mmio, in vgic_handle_enable_reg() argument
460 vgic_reg_access(mmio, reg, offset, mode); in vgic_handle_enable_reg()
461 if (mmio->is_write) { in vgic_handle_enable_reg()
[all …]
/linux-4.1.27/drivers/phy/
Dphy-qcom-ipq806x-sata.c27 void __iomem *mmio; member
67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
69 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
76 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
85 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
90 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
[all …]
Dphy-qcom-ufs-qmp-20nm.c97 writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_20nm_power_control()
110 writel_relaxed(0x0A, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
112 writel_relaxed(0x08, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
122 writel_relaxed(0x0A, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
124 writel_relaxed(0x02, phy->mmio + in ufs_qcom_phy_qmp_20nm_power_control()
133 writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_20nm_power_control()
146 phy->mmio + UFS_PHY_TX_LANE_ENABLE); in ufs_qcom_phy_qmp_20nm_set_tx_lane_enable()
154 tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_20nm_start_serdes()
157 writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_20nm_start_serdes()
166 err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, in ufs_qcom_phy_qmp_20nm_is_pcs_ready()
Dphy-qcom-apq8064-sata.c77 void __iomem *mmio; member
100 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_init()
195 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_exit()
227 phy->mmio = devm_ioremap_resource(dev, res); in qcom_apq8064_sata_phy_probe()
228 if (IS_ERR(phy->mmio)) in qcom_apq8064_sata_phy_probe()
229 return PTR_ERR(phy->mmio); in qcom_apq8064_sata_phy_probe()
Dphy-qcom-ufs-qmp-14nm.c76 writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); in ufs_qcom_phy_qmp_14nm_power_control()
97 tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_14nm_start_serdes()
100 writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); in ufs_qcom_phy_qmp_14nm_start_serdes()
110 err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, in ufs_qcom_phy_qmp_14nm_is_pcs_ready()
Dphy-qcom-ufs.c49 ufs_qcom_phy->mmio + tbl_A[i].reg_offset); in ufs_qcom_phy_calibrate()
67 ufs_qcom_phy->mmio + tbl_B[i].reg_offset); in ufs_qcom_phy_calibrate()
138 phy_common->mmio = devm_ioremap_resource(dev, res); in ufs_qcom_phy_base_init()
139 if (IS_ERR((void const *)phy_common->mmio)) { in ufs_qcom_phy_base_init()
140 err = PTR_ERR((void const *)phy_common->mmio); in ufs_qcom_phy_base_init()
141 phy_common->mmio = NULL; in ufs_qcom_phy_base_init()
/linux-4.1.27/drivers/ssb/
Dscan.c177 lo = readw(bus->mmio + offset); in scan_read32()
178 hi = readw(bus->mmio + offset + 2); in scan_read32()
184 return readl(bus->mmio + offset); in scan_read32()
207 iounmap(bus->mmio); in ssb_iounmap()
211 pci_iounmap(bus->host_pci, bus->mmio); in ssb_iounmap()
219 bus->mmio = NULL; in ssb_iounmap()
226 void __iomem *mmio = NULL; in ssb_ioremap() local
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE); in ssb_ioremap()
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL); in ssb_ioremap()
244 mmio = (void __iomem *)baseaddr; in ssb_ioremap()
[all …]
Ddriver_pcicore.c116 void __iomem *mmio; in ssb_extpci_read_config() local
125 mmio = ioremap_nocache(addr, len); in ssb_extpci_read_config()
126 if (!mmio) in ssb_extpci_read_config()
129 if (mips_busprobe32(val, mmio)) { in ssb_extpci_read_config()
134 val = readl(mmio); in ssb_extpci_read_config()
150 iounmap(mmio); in ssb_extpci_read_config()
162 void __iomem *mmio; in ssb_extpci_write_config() local
171 mmio = ioremap_nocache(addr, len); in ssb_extpci_write_config()
172 if (!mmio) in ssb_extpci_write_config()
175 if (mips_busprobe32(val, mmio)) { in ssb_extpci_write_config()
[all …]
Dpcmcia.c235 value = readb(bus->mmio + offset); in ssb_pcmcia_read8()
251 value = readw(bus->mmio + offset); in ssb_pcmcia_read16()
267 lo = readw(bus->mmio + offset); in ssb_pcmcia_read32()
268 hi = readw(bus->mmio + offset + 2); in ssb_pcmcia_read32()
281 void __iomem *addr = bus->mmio + offset; in ssb_pcmcia_block_read()
342 writeb(value, bus->mmio + offset); in ssb_pcmcia_write8()
356 writew(value, bus->mmio + offset); in ssb_pcmcia_write16()
370 writew((value & 0x0000FFFF), bus->mmio + offset); in ssb_pcmcia_write32()
371 writew(((value & 0xFFFF0000) >> 16), bus->mmio + offset + 2); in ssb_pcmcia_write32()
383 void __iomem *addr = bus->mmio + offset; in ssb_pcmcia_block_write()
Dpci.c277 sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2)); in sprom_do_read()
308 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); in sprom_do_write()
981 return ioread8(bus->mmio + offset); in ssb_pci_read8()
994 return ioread16(bus->mmio + offset); in ssb_pci_read16()
1007 return ioread32(bus->mmio + offset); in ssb_pci_read32()
1015 void __iomem *addr = bus->mmio + offset; in ssb_pci_block_read()
1055 iowrite8(value, bus->mmio + offset); in ssb_pci_write8()
1068 iowrite16(value, bus->mmio + offset); in ssb_pci_write16()
1081 iowrite32(value, bus->mmio + offset); in ssb_pci_write32()
1089 void __iomem *addr = bus->mmio + offset; in ssb_pci_block_write()
Dmain.c604 return readb(bus->mmio + offset); in ssb_ssb_read8()
612 return readw(bus->mmio + offset); in ssb_ssb_read16()
620 return readl(bus->mmio + offset); in ssb_ssb_read32()
631 addr = bus->mmio + offset; in ssb_ssb_block_read()
677 writeb(value, bus->mmio + offset); in ssb_ssb_write8()
685 writew(value, bus->mmio + offset); in ssb_ssb_write16()
693 writel(value, bus->mmio + offset); in ssb_ssb_write32()
704 addr = bus->mmio + offset; in ssb_ssb_block_write()
/linux-4.1.27/drivers/gpu/drm/bochs/
Dbochs_hw.c17 if (bochs->mmio) { in bochs_vga_writeb()
19 writeb(val, bochs->mmio + offset); in bochs_vga_writeb()
29 if (bochs->mmio) { in bochs_dispi_read()
31 ret = readw(bochs->mmio + offset); in bochs_dispi_read()
41 if (bochs->mmio) { in bochs_dispi_write()
43 writew(val, bochs->mmio + offset); in bochs_dispi_write()
65 bochs->mmio = ioremap(ioaddr, iosize); in bochs_hw_init()
66 if (bochs->mmio == NULL) { in bochs_hw_init()
119 if (bochs->mmio && pdev->revision >= 2) { in bochs_hw_init()
120 qext_size = readl(bochs->mmio + 0x600); in bochs_hw_init()
[all …]
/linux-4.1.27/sound/soc/intel/common/
Dsst-acpi.c121 struct resource *mmio; in sst_acpi_probe() local
156 mmio = platform_get_resource(pdev, IORESOURCE_MEM, in sst_acpi_probe()
158 if (mmio) { in sst_acpi_probe()
159 sst_pdata->lpe_base = mmio->start; in sst_acpi_probe()
160 sst_pdata->lpe_size = resource_size(mmio); in sst_acpi_probe()
165 mmio = platform_get_resource(pdev, IORESOURCE_MEM, in sst_acpi_probe()
167 if (mmio) { in sst_acpi_probe()
168 sst_pdata->pcicfg_base = mmio->start; in sst_acpi_probe()
169 sst_pdata->pcicfg_size = resource_size(mmio); in sst_acpi_probe()
174 mmio = platform_get_resource(pdev, IORESOURCE_MEM, in sst_acpi_probe()
[all …]
/linux-4.1.27/drivers/ide/
Dide-io-std.c94 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in ide_tf_load() local
96 if (mmio) in ide_tf_load()
121 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in ide_tf_read() local
123 if (mmio) in ide_tf_read()
172 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in ide_input_data() local
177 if ((io_32bit & 2) && !mmio) { in ide_input_data()
183 if (mmio) in ide_input_data()
188 if ((io_32bit & 2) && !mmio) in ide_input_data()
198 if (mmio) in ide_input_data()
216 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in ide_output_data() local
[all …]
Dide_platform.c55 int ret = 0, mmio = 0; in plat_ide_probe() local
72 mmio = 1; in plat_ide_probe()
81 if (mmio) { in plat_ide_probe()
101 if (mmio) in plat_ide_probe()
Dsiimage.c253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in sil_set_pio_mode() local
254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) in sil_set_pio_mode()
255 : (mmio ? 0xB4 : 0x80); in sil_set_pio_mode()
308 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in sil_set_dma_mode() local
309 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84) in sil_set_dma_mode()
310 : (mmio ? 0xB4 : 0x80); in sil_set_dma_mode()
315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A)); in sil_set_dma_mode()
Dide-dma-sff.c190 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; in ide_dma_setup() local
201 if (mmio) in ide_dma_setup()
208 if (mmio) in ide_dma_setup()
/linux-4.1.27/drivers/input/keyboard/
Dtegra-kbc.c103 void __iomem *mmio; member
169 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); in tegra_kbc_report_keys()
246 val = readl(kbc->mmio + KBC_CONTROL_0); in tegra_kbc_set_fifo_interrupt()
251 writel(val, kbc->mmio + KBC_CONTROL_0); in tegra_kbc_set_fifo_interrupt()
263 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; in tegra_kbc_keypress_timer()
302 val = readl(kbc->mmio + KBC_INT_0); in tegra_kbc_isr()
303 writel(val, kbc->mmio + KBC_INT_0); in tegra_kbc_isr()
331 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); in tegra_kbc_setup_wakekeys()
345 u32 row_cfg = readl(kbc->mmio + r_offs); in tegra_kbc_config_pins()
346 u32 col_cfg = readl(kbc->mmio + c_offs); in tegra_kbc_config_pins()
[all …]
/linux-4.1.27/drivers/media/pci/mantis/
Dmantis_pci.c88 mantis->mmio = ioremap(pci_resource_start(pdev, 0), in mantis_pci_init()
91 if (!mantis->mmio) { in mantis_pci_init()
111 mantis->mmio); in mantis_pci_init()
132 if (mantis->mmio) in mantis_pci_init()
133 iounmap(mantis->mmio); in mantis_pci_init()
154 dprintk(MANTIS_NOTICE, 1, " mem: 0x%p", mantis->mmio); in mantis_pci_exit()
156 if (mantis->mmio) { in mantis_pci_exit()
157 iounmap(mantis->mmio); in mantis_pci_exit()
Dmantis_common.h59 #define mmwrite(dat, addr) mwrite((dat), (mantis->mmio + (addr)))
60 #define mmread(addr) mread(mantis->mmio + (addr))
118 void __iomem *mmio; member
/linux-4.1.27/arch/powerpc/boot/
Dcuboot-pq2.c125 struct pci_range *mem = NULL, *mmio = NULL, in fixup_pci() local
167 mmio = &pci_ranges_buf[i]; in fixup_pci()
172 if (!mem || !mmio || !io) in fixup_pci()
174 if (mem->size[1] != mmio->size[1]) in fixup_pci()
181 if (mem->phys_addr + mem->size[1] == mmio->phys_addr) in fixup_pci()
183 else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr) in fixup_pci()
184 mem_base = mmio; in fixup_pci()
189 out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1)); in fixup_pci()
198 out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12); in fixup_pci()
199 out_le32(&pci_regs[0][8], mmio->phys_addr >> 12); in fixup_pci()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dgt215.c105 u32 *mmio = gt215_devinit_mmio_part; in gt215_devinit_mmio() local
122 while (mmio[0]) { in gt215_devinit_mmio()
123 if (addr >= mmio[0] && addr <= mmio[1]) { in gt215_devinit_mmio()
124 u32 part = (addr / mmio[2]) & 7; in gt215_devinit_mmio()
131 mmio += 3; in gt215_devinit_mmio()
148 .mmio = gt215_devinit_mmio,
Dbase.c94 devinit->mmio = impl->mmio; in nvkm_devinit_create_()
Dpriv.h10 u32 (*mmio)(struct nvkm_devinit *, u32); member
/linux-4.1.27/drivers/block/
Dsx8.c269 void __iomem *mmio; member
459 static void carm_init_buckets(void __iomem *mmio) in carm_init_buckets() argument
464 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); in carm_init_buckets()
482 void __iomem *mmio = host->mmio; in carm_send_msg() local
490 tmp = readl(mmio + CARM_HMUC); in carm_send_msg()
493 tmp = readl(mmio + CARM_INT_MASK); in carm_send_msg()
495 writel(tmp, mmio + CARM_INT_MASK); in carm_send_msg()
496 readl(mmio + CARM_INT_MASK); /* flush */ in carm_send_msg()
501 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); in carm_send_msg()
502 readl(mmio + CARM_IHQP); /* flush */ in carm_send_msg()
[all …]
/linux-4.1.27/drivers/bcma/
Dhost_pci.c45 return ioread8(core->bus->mmio + offset); in bcma_host_pci_read8()
51 return ioread16(core->bus->mmio + offset); in bcma_host_pci_read16()
57 return ioread32(core->bus->mmio + offset); in bcma_host_pci_read32()
64 iowrite8(value, core->bus->mmio + offset); in bcma_host_pci_write8()
71 iowrite16(value, core->bus->mmio + offset); in bcma_host_pci_write16()
78 iowrite32(value, core->bus->mmio + offset); in bcma_host_pci_write32()
85 void __iomem *addr = core->bus->mmio + offset; in bcma_host_pci_block_read()
109 void __iomem *addr = core->bus->mmio + offset; in bcma_host_pci_block_write()
134 return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset); in bcma_host_pci_aread32()
142 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset); in bcma_host_pci_awrite32()
[all …]
Dhost_soc.c175 bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1); in bcma_host_soc_register()
176 if (!bus->mmio) in bcma_host_soc_register()
198 iounmap(bus->mmio); in bcma_host_soc_init()
217 bus->mmio = of_iomap(np, 0); in bcma_host_soc_probe()
218 if (!bus->mmio) in bcma_host_soc_probe()
239 iounmap(bus->mmio); in bcma_host_soc_probe()
248 iounmap(bus->mmio); in bcma_host_soc_remove()
Ddriver_pci_host.c90 void __iomem *mmio = 0; in bcma_extpci_read_config() local
118 mmio = ioremap_nocache(addr, sizeof(val)); in bcma_extpci_read_config()
119 if (!mmio) in bcma_extpci_read_config()
122 if (mips_busprobe32(val, mmio)) { in bcma_extpci_read_config()
142 if (mmio) in bcma_extpci_read_config()
143 iounmap(mmio); in bcma_extpci_read_config()
154 void __iomem *mmio = 0; in bcma_extpci_write_config() local
183 mmio = ioremap_nocache(addr, sizeof(val)); in bcma_extpci_write_config()
184 if (!mmio) in bcma_extpci_write_config()
187 if (mips_busprobe32(val, mmio)) { in bcma_extpci_write_config()
[all …]
/linux-4.1.27/drivers/misc/mic/host/
Dmic_x100.c48 mic_mmio_write(&mdev->mmio, val, in mic_x100_write_spad()
65 u32 val = mic_mmio_read(&mdev->mmio, in mic_x100_read_spad()
81 struct mic_mw *mw = &mdev->mmio; in mic_x100_enable_interrupts()
108 struct mic_mw *mw = &mdev->mmio; in mic_x100_disable_interrupts()
131 struct mic_mw *mw = &mdev->mmio; in mic_x100_send_sbox_intr()
155 mic_mmio_write(&mdev->mmio, 0, in mic_x100_send_rdmasr_intr()
186 u32 reg = mic_mmio_read(&mdev->mmio, sicr0); in mic_x100_ack_interrupt()
187 mic_mmio_write(&mdev->mmio, reg, sicr0); in mic_x100_ack_interrupt()
200 struct mic_mw *mw = &mdev->mmio; in mic_x100_intr_workarounds()
233 return mic_mmio_read(&mdev->mmio, in mic_x100_read_msi_to_src_map()
[all …]
Dmic_main.c336 mdev->mmio.pa = pci_resource_start(pdev, mdev->ops->mmio_bar); in mic_probe()
337 mdev->mmio.len = pci_resource_len(pdev, mdev->ops->mmio_bar); in mic_probe()
338 mdev->mmio.va = pci_ioremap_bar(pdev, mdev->ops->mmio_bar); in mic_probe()
339 if (!mdev->mmio.va) { in mic_probe()
430 iounmap(mdev->mmio.va); in mic_probe()
473 iounmap(mdev->mmio.va); in mic_remove()
/linux-4.1.27/arch/arm/kvm/
Dmmio.c102 if (!run->mmio.is_write) { in kvm_handle_mmio_return()
103 len = run->mmio.len; in kvm_handle_mmio_return()
107 data = mmio_read_buf(run->mmio.data, len); in kvm_handle_mmio_return()
115 trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, in kvm_handle_mmio_return()
205 run->mmio.is_write = is_write; in io_mem_abort()
206 run->mmio.phys_addr = fault_ipa; in io_mem_abort()
207 run->mmio.len = len; in io_mem_abort()
208 memcpy(run->mmio.data, data_buf, len); in io_mem_abort()
DMakefile22 obj-y += coproc.o coproc_a15.o coproc_a7.o mmio.o psci.o perf.o
/linux-4.1.27/drivers/watchdog/
Dvia_wdt.c69 static unsigned int mmio; variable
186 pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio); in wdt_probe()
187 if (mmio) { in wdt_probe()
188 dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio); in wdt_probe()
194 if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) { in wdt_probe()
199 wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN); in wdt_probe()
224 release_mem_region(mmio, VIA_WDT_MMIO_LEN); in wdt_probe()
237 release_mem_region(mmio, VIA_WDT_MMIO_LEN); in wdt_remove()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dsubdev.h13 void __iomem *mmio; member
65 u8 data = ioread8(subdev->mmio + addr); in nv_rd08()
74 u16 data = ioread16_native(subdev->mmio + addr); in nv_rd16()
83 u32 data = ioread32_native(subdev->mmio + addr); in nv_rd32()
93 iowrite8(data, subdev->mmio + addr); in nv_wr08()
101 iowrite16_native(data, subdev->mmio + addr); in nv_wr16()
109 iowrite32_native(data, subdev->mmio + addr); in nv_wr32()
/linux-4.1.27/drivers/video/fbdev/matrox/
Dmatroxfb_accel.c414 vaddr_t mmio; in matroxfb_1bpp_imageblit() local
443 mmio = minfo->mmio.vbase; in matroxfb_1bpp_imageblit()
447 mga_writel(mmio, M_FXBNDRY, fxbndry); in matroxfb_1bpp_imageblit()
448 mga_writel(mmio, M_AR0, ar0); in matroxfb_1bpp_imageblit()
449 mga_writel(mmio, M_AR3, 0); in matroxfb_1bpp_imageblit()
451 mga_writel(mmio, M_YDSTLEN | M_EXEC, ydstlen); in matroxfb_1bpp_imageblit()
452 mga_memcpy_toio(mmio, chardata, xlen); in matroxfb_1bpp_imageblit()
454 mga_writel(mmio, M_AR5, 0); in matroxfb_1bpp_imageblit()
455 mga_writel(mmio, M_YDSTLEN | M_EXEC, ydstlen); in matroxfb_1bpp_imageblit()
459 mga_memcpy_toio(mmio, chardata, charcell); in matroxfb_1bpp_imageblit()
[all …]
Dmatroxfb_base.h423 } mmio; member
691 #define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr))
692 #define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr))
693 #define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val))
694 #define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val))
695 #define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val))
Dmatroxfb_crtc2.c308 fix->mmio_start = m2info->mmio.base; in matroxfb_dh_init_fix()
309 fix->mmio_len = m2info->mmio.len; in matroxfb_dh_init_fix()
628 m2info->mmio.base = minfo->mmio.base; in matroxfb_dh_regit()
629 m2info->mmio.vbase = minfo->mmio.vbase; in matroxfb_dh_regit()
630 m2info->mmio.len = minfo->mmio.len; in matroxfb_dh_regit()
Dmatroxfb_crtc2.h27 } mmio; member
/linux-4.1.27/drivers/misc/mic/card/
Dmic_x100.c50 return mic_mmio_read(&mdev->mmio, in mic_read_spad()
62 struct mic_mw *mw = &mdev->mmio; in mic_send_intr()
201 mdev->mmio.pa = MIC_X100_MMIO_BASE; in mic_probe()
202 mdev->mmio.len = MIC_X100_MMIO_LEN; in mic_probe()
203 mdev->mmio.va = devm_ioremap(&pdev->dev, MIC_X100_MMIO_BASE, in mic_probe()
205 if (!mdev->mmio.va) { in mic_probe()
214 mdrv->mdev.mmio.va); in mic_probe()
Dmic_device.h61 struct mic_mw mmio; member
/linux-4.1.27/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8x74.c23 void __iomem *mmio; member
30 msm_writel(data, phy->mmio + reg); in phy_write()
144 phy_8x74->mmio = msm_ioremap(hdmi->pdev, in hdmi_phy_8x74_init()
146 if (IS_ERR(phy_8x74->mmio)) { in hdmi_phy_8x74_init()
147 ret = PTR_ERR(phy_8x74->mmio); in hdmi_phy_8x74_init()
Dhdmi.h53 void __iomem *mmio; member
104 msm_writel(data, hdmi->mmio + reg); in hdmi_write()
109 return msm_readl(hdmi->mmio + reg); in hdmi_read()
Dhdmi.c104 hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI"); in hdmi_init()
105 if (IS_ERR(hdmi->mmio)) { in hdmi_init()
106 ret = PTR_ERR(hdmi->mmio); in hdmi_init()
/linux-4.1.27/arch/powerpc/kvm/
Dpowerpc.c721 if (run->mmio.len > sizeof(gpr)) { in kvmppc_complete_mmio_load()
722 printk(KERN_ERR "bad MMIO length: %d\n", run->mmio.len); in kvmppc_complete_mmio_load()
727 switch (run->mmio.len) { in kvmppc_complete_mmio_load()
728 case 8: gpr = *(u64 *)run->mmio.data; break; in kvmppc_complete_mmio_load()
729 case 4: gpr = *(u32 *)run->mmio.data; break; in kvmppc_complete_mmio_load()
730 case 2: gpr = *(u16 *)run->mmio.data; break; in kvmppc_complete_mmio_load()
731 case 1: gpr = *(u8 *)run->mmio.data; break; in kvmppc_complete_mmio_load()
734 switch (run->mmio.len) { in kvmppc_complete_mmio_load()
735 case 8: gpr = swab64(*(u64 *)run->mmio.data); break; in kvmppc_complete_mmio_load()
736 case 4: gpr = swab32(*(u32 *)run->mmio.data); break; in kvmppc_complete_mmio_load()
[all …]
/linux-4.1.27/arch/mips/kvm/
Demulate.c1323 void *data = run->mmio.data; in kvm_mips_emulate_store()
1343 if (bytes > sizeof(run->mmio.data)) { in kvm_mips_emulate_store()
1345 run->mmio.len); in kvm_mips_emulate_store()
1347 run->mmio.phys_addr = in kvm_mips_emulate_store()
1350 if (run->mmio.phys_addr == KVM_INVALID_ADDR) { in kvm_mips_emulate_store()
1354 run->mmio.len = bytes; in kvm_mips_emulate_store()
1355 run->mmio.is_write = 1; in kvm_mips_emulate_store()
1367 if (bytes > sizeof(run->mmio.data)) { in kvm_mips_emulate_store()
1369 run->mmio.len); in kvm_mips_emulate_store()
1371 run->mmio.phys_addr = in kvm_mips_emulate_store()
[all …]
/linux-4.1.27/drivers/block/mtip32xx/
Dmtip32xx.c267 writel(HOST_RESET, dd->mmio + HOST_CTL); in mtip_hba_reset()
270 readl(dd->mmio + HOST_CTL); in mtip_hba_reset()
279 } while ((readl(dd->mmio + HOST_CTL) & HOST_RESET) in mtip_hba_reset()
282 if (readl(dd->mmio + HOST_CTL) & HOST_RESET) in mtip_hba_reset()
327 tmp = readl(port->mmio + PORT_CMD); in mtip_enable_fis()
329 writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD); in mtip_enable_fis()
331 writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD); in mtip_enable_fis()
334 readl(port->mmio + PORT_CMD); in mtip_enable_fis()
353 tmp = readl(port->mmio + PORT_CMD); in mtip_enable_engine()
355 writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD); in mtip_enable_engine()
[all …]
Dmtip32xx.h361 void __iomem *mmio; member
459 void __iomem *mmio; /* Base address of the HBA registers. */ member
/linux-4.1.27/drivers/video/backlight/
Dep93xx_bl.c25 void __iomem *mmio; member
33 writel((brightness << 8) | EP93XX_MAX_COUNT, ep93xxbl->mmio); in ep93xxbl_set()
87 ep93xxbl->mmio = devm_ioremap(&dev->dev, res->start, in ep93xxbl_probe()
89 if (!ep93xxbl->mmio) in ep93xxbl_probe()
/linux-4.1.27/tools/lguest/
Dlguest.c187 struct virtio_pci_mmio *mmio; member
721 vq->dev->mmio->isr = 0x1; in trigger_irq()
1167 dev->mmio->cfg.queue_enable = 0; in reset_device()
1888 d->mmio->cfg.device_feature = d->features; in emulate_mmio_write()
1890 d->mmio->cfg.device_feature = (d->features >> 32); in emulate_mmio_write()
1892 d->mmio->cfg.device_feature = 0; in emulate_mmio_write()
1899 if (d->mmio->cfg.guest_feature_select == 0) { in emulate_mmio_write()
1903 assert(d->mmio->cfg.guest_feature_select == 1); in emulate_mmio_write()
1933 if (d->mmio->cfg.device_status & ~val) in emulate_mmio_write()
1935 d->mmio->cfg.device_status, val); in emulate_mmio_write()
[all …]
/linux-4.1.27/drivers/gpu/drm/rcar-du/
Drcar_du_lvdsenc.c29 void __iomem *mmio; member
38 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
152 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem); in rcar_du_lvdsenc_get_resources()
153 if (IS_ERR(lvds->mmio)) in rcar_du_lvdsenc_get_resources()
154 return PTR_ERR(lvds->mmio); in rcar_du_lvdsenc_get_resources()
Drcar_du_drv.h76 void __iomem *mmio; member
109 return ioread32(rcdu->mmio + reg); in rcar_du_read()
114 iowrite32(data, rcdu->mmio + reg); in rcar_du_write()
Drcar_du_drv.c177 rcdu->mmio = devm_ioremap_resource(&pdev->dev, mem); in rcar_du_load()
178 if (IS_ERR(rcdu->mmio)) in rcar_du_load()
179 return PTR_ERR(rcdu->mmio); in rcar_du_load()
/linux-4.1.27/drivers/media/platform/vsp1/
Dvsp1.h57 void __iomem *mmio; member
84 return ioread32(vsp1->mmio + reg); in vsp1_read()
89 iowrite32(data, vsp1->mmio + reg); in vsp1_write()
/linux-4.1.27/drivers/video/fbdev/
Dpmag-ba-fb.c41 volatile void __iomem *mmio; member
185 par->mmio = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len); in pmagbafb_probe()
186 if (!par->mmio) { in pmagbafb_probe()
191 par->dac = par->mmio + PMAG_BA_BT459; in pmagbafb_probe()
225 iounmap(par->mmio); in pmagbafb_probe()
248 iounmap(par->mmio); in pmagbafb_remove()
Dpmagb-b-fb.c37 volatile void __iomem *mmio; member
91 writel(v, par->mmio + PMAGB_B_GP0); in gp0_write()
292 par->mmio = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len); in pmagbbfb_probe()
293 if (!par->mmio) { in pmagbbfb_probe()
298 par->sfb = par->mmio + PMAGB_B_SFB; in pmagbbfb_probe()
299 par->dac = par->mmio + PMAGB_B_BT459; in pmagbbfb_probe()
343 iounmap(par->mmio); in pmagbbfb_probe()
366 iounmap(par->mmio); in pmagbbfb_remove()
Ds3fb.c43 u8 __iomem *mmio; member
205 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
213 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
1280 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); in s3_pci_probe()
1281 if (par->mmio) in s3_pci_probe()
1287 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) in s3_pci_probe()
1385 if (par->mmio) in s3_pci_probe()
1386 iounmap(par->mmio); in s3_pci_probe()
1422 if (par->mmio) in s3_pci_remove()
1423 iounmap(par->mmio); in s3_pci_remove()
Datmel_lcdfb.c44 void __iomem *mmio; member
73 #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
74 #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
1298 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); in atmel_lcdfb_probe()
1299 if (!sinfo->mmio) { in atmel_lcdfb_probe()
1346 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); in atmel_lcdfb_probe()
1358 iounmap(sinfo->mmio); in atmel_lcdfb_probe()
1403 iounmap(sinfo->mmio); in atmel_lcdfb_remove()
/linux-4.1.27/Documentation/devicetree/bindings/arm/rockchip/
Dsmp-sram.txt8 Therefore a reserved section sub-node has to be added to the mmio-sram
14 The rest of the properties should follow the generic mmio-sram discription
20 compatible = "mmio-sram";
Dpmu-sram.txt14 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
/linux-4.1.27/Documentation/devicetree/bindings/arm/exynos/
Dsmp-sysram.txt8 Therefore reserved section sub-nodes have to be added to the mmio-sram
17 The rest of the properties should follow the generic mmio-sram discription
23 compatible = "mmio-sram";
/linux-4.1.27/drivers/staging/comedi/
Dcomedi_pci.c91 if (dev->mmio) { in comedi_pci_detach()
92 iounmap(dev->mmio); in comedi_pci_detach()
93 dev->mmio = NULL; in comedi_pci_detach()
/linux-4.1.27/drivers/video/fbdev/savage/
Dsavagefb.h225 } mmio; member
258 return readb(par->mmio.vbase + addr); in savage_in8()
263 return readw(par->mmio.vbase + addr); in savage_in16()
268 return readl(par->mmio.vbase + addr); in savage_in32()
273 writeb(val, par->mmio.vbase + addr); in savage_out8()
278 writew(val, par->mmio.vbase + addr); in savage_out16()
283 writel(val, par->mmio.vbase + addr); in savage_out32()
Dsavagefb-i2c.c177 par->chan.ioaddr = par->mmio.vbase; in savagefb_create_i2c_busses()
187 par->chan.ioaddr = par->mmio.vbase; in savagefb_create_i2c_busses()
195 par->chan.ioaddr = par->mmio.vbase; in savagefb_create_i2c_busses()
Dsavagefb_driver.c1618 par->vgastate.vgabase = par->mmio.vbase + 0x8000; in savagefb_open()
1724 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1727 par->mmio.pbase = pci_resource_start(par->pcidev, 0) + in savage_map_mmio()
1730 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE; in savage_map_mmio()
1732 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len); in savage_map_mmio()
1733 if (!par->mmio.vbase) { in savage_map_mmio()
1738 par->mmio.vbase); in savage_map_mmio()
1740 info->fix.mmio_start = par->mmio.pbase; in savage_map_mmio()
1741 info->fix.mmio_len = par->mmio.len; in savage_map_mmio()
1743 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET); in savage_map_mmio()
[all …]
/linux-4.1.27/drivers/memstick/host/
Dr592.c60 u32 value = readl(dev->mmio + address); in r592_read_reg()
70 writel(value, dev->mmio + address); in r592_write_reg()
76 u32 value = __raw_readl(dev->mmio + address); in r592_read_reg_raw_be()
86 __raw_writel(cpu_to_be32(value), dev->mmio + address); in r592_write_reg_raw_be()
93 u32 reg = readl(dev->mmio + address); in r592_set_reg_mask()
95 writel(reg | mask , dev->mmio + address); in r592_set_reg_mask()
102 u32 reg = readl(dev->mmio + address); in r592_clear_reg_mask()
105 writel(reg & ~mask, dev->mmio + address); in r592_clear_reg_mask()
765 dev->mmio = pci_ioremap_bar(pdev, 0); in r592_probe()
766 if (!dev->mmio) in r592_probe()
[all …]
Dr592.h137 void __iomem *mmio; member
/linux-4.1.27/arch/powerpc/sysdev/
Ddcr.c55 return dcr_map_ok_mmio(host.host.mmio); in dcr_map_ok_generic()
84 host.host.mmio = dcr_map_mmio(dev, dcr_n, dcr_c); in dcr_map_generic()
97 dcr_unmap_mmio(host.host.mmio, dcr_c); in dcr_unmap_generic()
108 return dcr_read_mmio(host.host.mmio, dcr_n); in dcr_read_generic()
120 dcr_write_mmio(host.host.mmio, dcr_n, value); in dcr_write_generic()
/linux-4.1.27/sound/soc/sh/
Dssi.c65 #define SSIREG(reg) (*(unsigned long *)(ssi->mmio + (reg)))
68 unsigned long mmio; member
74 .mmio = 0xFE680000,
77 .mmio = 0xFE690000,
81 .mmio = 0xFFE70000,
Dhac.c78 unsigned long mmio; /* HAC base address */ member
82 .mmio = 0xFE240000,
85 .mmio = 0xFE250000,
89 .mmio = 0xFFE40000,
96 #define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg)))
Ddma-sh7760.c53 unsigned long mmio; /* DMABRG audio channel control reg MMIO */ member
66 .mmio = 0xFE3C0040,
70 .mmio = 0xFE3C0060,
75 #define BRGREG(x) (*(unsigned long *)(cam->mmio + (x)))
/linux-4.1.27/drivers/gpio/
Dgpio-bt8xx.c62 void __iomem *mmio; member
72 #define bgwrite(dat, adr) writel((dat), bg->mmio+(adr))
73 #define bgread(adr) readl(bg->mmio+(adr))
204 bg->mmio = devm_ioremap(&dev->dev, pci_resource_start(dev, 0), 0x1000); in bt8xxgpio_probe()
205 if (!bg->mmio) { in bt8xxgpio_probe()
/linux-4.1.27/Documentation/devicetree/bindings/virtio/
Dmmio.txt7 - compatible: "virtio,mmio" compatibility string
14 compatible = "virtio,mmio";
/linux-4.1.27/drivers/misc/genwqe/
Dcard_base.c187 void __iomem *mmio; in genwqe_bus_reset() local
192 mmio = cd->mmio; in genwqe_bus_reset()
193 cd->mmio = NULL; in genwqe_bus_reset()
194 pci_iounmap(pci_dev, mmio); in genwqe_bus_reset()
228 cd->mmio = pci_iomap(pci_dev, 0, 0); in genwqe_bus_reset()
229 if (cd->mmio == NULL) { in genwqe_bus_reset()
998 readq(cd->mmio + IO_SLC_CFGREG_GFIR); in genwqe_health_thread()
1124 cd->mmio = pci_iomap(pci_dev, 0, 0); in genwqe_pci_setup()
1125 if (cd->mmio == NULL) { in genwqe_pci_setup()
1143 pci_iounmap(pci_dev, cd->mmio); in genwqe_pci_setup()
[all …]
Dcard_utils.c61 if (cd->mmio == NULL) in __genwqe_writeq()
67 __raw_writeq((__force u64)cpu_to_be64(val), cd->mmio + byte_offs); in __genwqe_writeq()
91 if (cd->mmio == NULL) in __genwqe_readq()
94 return be64_to_cpu((__force __be64)__raw_readq(cd->mmio + byte_offs)); in __genwqe_readq()
112 if (cd->mmio == NULL) in __genwqe_writel()
118 __raw_writel((__force u32)cpu_to_be32(val), cd->mmio + byte_offs); in __genwqe_writel()
134 if (cd->mmio == NULL) in __genwqe_readl()
137 return be32_to_cpu((__force __be32)__raw_readl(cd->mmio + byte_offs)); in __genwqe_readl()
/linux-4.1.27/drivers/gpu/drm/sis/
Dsis_drv.h52 #define SIS_BASE (dev_priv->mmio)
57 drm_local_map_t *mmio; member
Dsis_mm.c249 if (dev_priv->mmio == NULL) { in sis_idle()
250 dev_priv->mmio = sis_reg_init(dev); in sis_idle()
251 if (dev_priv->mmio == NULL) { in sis_idle()
309 dev_priv->mmio = NULL; in sis_lastclose()
/linux-4.1.27/drivers/firmware/
Dpcdp.c26 int mmio; in setup_serial_console() local
30 mmio = (uart->addr.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY); in setup_serial_console()
32 mmio ? "mmio" : "io", uart->addr.address); in setup_serial_console()
/linux-4.1.27/drivers/gpu/drm/shmobile/
Dshmob_drm_regs.h282 iowrite32(data, sdev->mmio + reg + LCDC_MIRROR_OFFSET); in lcdc_write_mirror()
287 iowrite32(data, sdev->mmio + reg); in lcdc_write()
289 iowrite32(data, sdev->mmio + reg + LCDC_SIDE_B_OFFSET); in lcdc_write()
294 return ioread32(sdev->mmio + reg); in lcdc_read()
Dshmob_drm_drv.h32 void __iomem *mmio; member
Dshmob_drm_drv.c153 sdev->mmio = devm_ioremap_nocache(&pdev->dev, res->start, in shmob_drm_load()
155 if (sdev->mmio == NULL) { in shmob_drm_load()
/linux-4.1.27/drivers/gpu/drm/msm/
Dmsm_gpu.h95 void __iomem *mmio; member
144 msm_writel(data, gpu->mmio + (reg << 2)); in gpu_write()
149 return msm_readl(gpu->mmio + (reg << 2)); in gpu_read()
/linux-4.1.27/drivers/pwm/
Dpwm-sti.c63 void __iomem *mmio; member
317 pc->mmio = devm_ioremap_resource(dev, res); in sti_pwm_probe()
318 if (IS_ERR(pc->mmio)) in sti_pwm_probe()
319 return PTR_ERR(pc->mmio); in sti_pwm_probe()
321 pc->regmap = devm_regmap_init_mmio(dev, pc->mmio, in sti_pwm_probe()
/linux-4.1.27/drivers/mtd/nand/
Dcafe_nand.c62 void __iomem *mmio; member
99 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
125 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); in cafe_write_buf()
140 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); in cafe_read_buf()
269 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); in cafe_nand_cmdfunc()
443 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); in cafe_nand_read_page()
610 cafe->mmio = pci_iomap(pdev, 0, 0); in cafe_nand_probe()
611 if (!cafe->mmio) { in cafe_nand_probe()
785 pci_iounmap(pdev, cafe->mmio); in cafe_nand_probe()
[all …]
Dhisi504_nand.c140 void __iomem *mmio; member
375 return *(uint8_t *)(host->mmio); in hisi_nfc_read_byte()
380 return *(uint8_t *)(host->mmio + host->offset - 1); in hisi_nfc_read_byte()
490 memset(host->mmio, 0, 0x10); in hisi_nfc_cmdfunc()
502 memset(host->mmio, 0, 0x10); in hisi_nfc_cmdfunc()
625 memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN); in hisi_nfc_host_init()
732 host->mmio = devm_ioremap_resource(dev, res); in hisi_nfc_probe()
733 if (IS_ERR(host->mmio)) { in hisi_nfc_probe()
734 ret = PTR_ERR(host->mmio); in hisi_nfc_probe()
Dr852.c36 uint8_t reg = readb(dev->mmio + address); in r852_read_reg()
44 writeb(value, dev->mmio + address); in r852_write_reg()
52 uint32_t reg = le32_to_cpu(readl(dev->mmio + address)); in r852_read_reg_dword()
60 writel(cpu_to_le32(value), dev->mmio + address); in r852_write_reg_dword()
898 dev->mmio = pci_ioremap_bar(pci_dev, 0); in r852_probe()
900 if (!dev->mmio) in r852_probe()
949 pci_iounmap(pci_dev, dev->mmio); in r852_probe()
985 pci_iounmap(pci_dev, dev->mmio); in r852_remove()
Dcs553x_nand.c186 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) in cs553x_init_one() argument
192 …printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", ad… in cs553x_init_one()
194 if (!mmio) { in cs553x_init_one()
Dr852.h110 void __iomem *mmio; /* mmio */ member
/linux-4.1.27/drivers/gpu/drm/r128/
Dr128_drv.h122 drm_local_map_t *mmio; member
396 #define R128_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
397 #define R128_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
398 #define R128_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
399 #define R128_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
/linux-4.1.27/drivers/gpu/drm/via/
Dvia_map.c49 dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset); in via_do_init_map()
50 if (!dev_priv->mmio) { in via_do_init_map()
Dvia_drv.h66 drm_local_map_t *mmio; member
112 #define VIA_BASE ((dev_priv->mmio))
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dcom.fuc152 // mmctx_size - determine size of a mmio list transfer
154 // In : $r14 mmio list head
155 // $r15 mmio list tail
172 // mmctx_xfer - execute a list of mmio transfers
179 // $r12 mmio list head
180 // $r13 mmio list tail
207 // loop over the mmio list, and send requests to the hw
Dgpc.fuc156 // determine which GPC we are, setup (optional) mmio access offset
196 // calculate GPC mmio context size
203 // calculate per-TPC mmio context size
213 // calculate per-UNK mmio context size
427 // mmio context
439 // per-TPC mmio context
455 // per-UNK mmio context
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_kms.h44 void __iomem *mmio, *vbif; member
117 msm_writel(data, mdp5_kms->mmio + reg); in mdp5_write()
122 return msm_readl(mdp5_kms->mmio + reg); in mdp5_read()
Dmdp5_kms.c434 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); in mdp5_kms_init()
435 if (IS_ERR(mdp5_kms->mmio)) { in mdp5_kms_init()
436 ret = PTR_ERR(mdp5_kms->mmio); in mdp5_kms_init()
504 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw); in mdp5_kms_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dsubdev.c116 subdev->mmio = nv_subdev(device)->mmio; in nvkm_subdev_create_()
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp4/
Dmdp4_kms.h38 void __iomem *mmio; member
65 msm_writel(data, mdp4_kms->mmio + reg); in mdp4_write()
70 return msm_readl(mdp4_kms->mmio + reg); in mdp4_read()
/linux-4.1.27/Documentation/devicetree/bindings/misc/
Dsram.txt7 - compatible : mmio-sram
40 compatible = "mmio-sram";
/linux-4.1.27/drivers/gpu/drm/mga/
Dmga_drv.h144 drm_local_map_t *mmio; member
200 #define MGA_READ8(reg) DRM_READ8(dev_priv->mmio, (reg))
201 #define MGA_READ(reg) DRM_READ32(dev_priv->mmio, (reg))
202 #define MGA_WRITE8(reg, val) DRM_WRITE8(dev_priv->mmio, (reg), (val))
203 #define MGA_WRITE(reg, val) DRM_WRITE32(dev_priv->mmio, (reg), (val))
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgf100.c282 struct gf100_gr_mmio *mmio = priv->mmio_list; in gf100_gr_context_ctor() local
299 &chan->mmio); in gf100_gr_context_ctor()
303 ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, in gf100_gr_context_ctor()
325 for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { in gf100_gr_context_ctor()
326 u32 addr = mmio->addr; in gf100_gr_context_ctor()
327 u32 data = mmio->data; in gf100_gr_context_ctor()
329 if (mmio->buffer >= 0) { in gf100_gr_context_ctor()
330 u64 info = chan->data[mmio->buffer].vma.offset; in gf100_gr_context_ctor()
331 data |= info >> mmio->shift; in gf100_gr_context_ctor()
334 nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); in gf100_gr_context_ctor()
[all …]
Dctxgf100.c1010 info->mmio->addr = addr; in gf100_grctx_mmio_item()
1011 info->mmio->data = data; in gf100_grctx_mmio_item()
1012 info->mmio->shift = shift; in gf100_grctx_mmio_item()
1013 info->mmio->buffer = buffer; in gf100_grctx_mmio_item()
1016 info->mmio++; in gf100_grctx_mmio_item()
1312 info.mmio = priv->mmio_list; in gf100_grctx_generate()
Dgm206.c38 .mmio = gm204_gr_pack_mmio,
Dgk20a.c47 .mmio = gk104_gr_pack_mmio,
Dgf104.c124 .mmio = gf104_gr_pack_mmio,
Dgk110b.c112 .mmio = gk110b_gr_pack_mmio,
Dgf108.c131 .mmio = gf108_gr_pack_mmio,
Dgf119.c187 .mmio = gf119_gr_pack_mmio,
Dgf110.c113 .mmio = gf110_gr_pack_mmio,
Dgf100.h103 struct nvkm_gpuobj *mmio; member
174 const struct gf100_gr_pack *mmio; member
Dgf117.c132 .mmio = gf117_gr_pack_mmio,
Dgm204.c280 gf100_gr_mmio(priv, oclass->mmio); in gm204_gr_init()
384 .mmio = gm204_gr_pack_mmio,
Dgk208.c186 .mmio = gk208_gr_pack_mmio,
Dgk110.c207 .mmio = gk110_gr_pack_mmio,
Dgk104.c223 gf100_gr_mmio(priv, oclass->mmio); in gk104_gr_init()
355 .mmio = gk104_gr_pack_mmio,
/linux-4.1.27/drivers/gpu/drm/tilcdc/
Dtilcdc_regs.h119 iowrite32(data, priv->mmio + reg); in tilcdc_write()
125 return ioread32(priv->mmio + reg); in tilcdc_read()
Dtilcdc_drv.c141 if (priv->mmio) in tilcdc_unload()
142 iounmap(priv->mmio); in tilcdc_unload()
187 priv->mmio = ioremap_nocache(res->start, resource_size(res)); in tilcdc_load()
188 if (!priv->mmio) { in tilcdc_load()
323 iounmap(priv->mmio); in tilcdc_load()
Dtilcdc_drv.h50 void __iomem *mmio; member
/linux-4.1.27/arch/powerpc/include/asm/
Ddcr-generic.h30 dcr_host_mmio_t mmio; member
/linux-4.1.27/drivers/staging/sm750fb/
Dsm750_cursor.c24 readl(cursor->mmio + (addr))
27 writel((data),cursor->mmio + (addr))
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Ddevinit.h10 u32 (*mmio)(struct nvkm_devinit *, u32 addr); member
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c448 !nv_subdev(device)->mmio) {
449 nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size);
450 if (!nv_subdev(device)->mmio) {
638 if (nv_subdev(device)->mmio)
639 iounmap(nv_subdev(device)->mmio);
/linux-4.1.27/sound/pci/
Dbt87x.c196 void __iomem *mmio; member
219 return readl(chip->mmio + reg); in snd_bt87x_readl()
224 writel(value, chip->mmio + reg); in snd_bt87x_writel()
689 if (chip->mmio) in snd_bt87x_free()
693 iounmap(chip->mmio); in snd_bt87x_free()
755 chip->mmio = pci_ioremap_bar(pci, 0); in snd_bt87x_create()
756 if (!chip->mmio) { in snd_bt87x_create()
/linux-4.1.27/drivers/base/regmap/
DMakefile11 obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
/linux-4.1.27/drivers/dma/
Dmic_x100_dma.h145 void __iomem *mmio; member
180 return to_mic_dma_dev(ch)->mmio; in mic_dma_chan_to_mmio()
/linux-4.1.27/arch/openrisc/boot/dts/
Dor1ksim.dts9 bootargs = "console=uart,mmio,0x90000000,115200";
/linux-4.1.27/drivers/gpu/drm/savage/
Dsavage_drv.h157 drm_local_map_t *mmio; member
487 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
488 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
/linux-4.1.27/tools/perf/Documentation/
Dperf-kvm.txt54 of KVM events. Currently, vmexit, mmio (x86 only) and ioport (x86 only)
106 event to be analyzed. Possible values: vmexit, mmio (x86 only),
142 mmio (x86 only), ioport (x86 only).
/linux-4.1.27/arch/arm/boot/dts/
Dat91sam9g20.dtsi24 compatible = "mmio-sram";
/linux-4.1.27/arch/x86/mm/
DMakefile27 mmiotrace-y := kmmio.o pf_in.o mmio-mod.o
/linux-4.1.27/Documentation/devicetree/bindings/input/touchscreen/
Dsun4i.txt7 - reg: mmio address range of the chip
/linux-4.1.27/arch/arm64/kvm/
DMakefile15 kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dfw-cfg.txt54 - compatible: "qemu,fw-cfg-mmio".
69 compatible = "qemu,fw-cfg-mmio";

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