590 	void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
592 	void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
594 			   void __iomem *mmio);
595 	int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
597 	void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
598 	void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
617 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
619 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
621 			   void __iomem *mmio);
622 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
624 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
625 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
627 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
629 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
631 			   void __iomem *mmio);
632 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
634 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
636 				      void __iomem *mmio);
638 				      void __iomem *mmio);
640 				  void __iomem *mmio, unsigned int n_hc);
642 				      void __iomem *mmio);
643 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
645 				  void __iomem *mmio, unsigned int port);
646 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
647 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
921 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)  in mv5_phy_base()  argument
923 	void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);  in mv5_phy_base()
1104 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_set_irq_coalescing()  local
1131 		writel(clks,  mmio + IRQ_COAL_TIME_THRESHOLD);  in mv_set_irq_coalescing()
1132 		writel(count, mmio + IRQ_COAL_IO_THRESHOLD);  in mv_set_irq_coalescing()
1134 		writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);  in mv_set_irq_coalescing()
1143 	hc_mmio = mv_hc_base_from_port(mmio, 0);  in mv_set_irq_coalescing()
1150 		hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);  in mv_set_irq_coalescing()
2901 	void __iomem *mmio = hpriv->base, *hc_mmio;  in mv_host_intr()  local
2906 		writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);  in mv_host_intr()
2949 			hc_mmio = mv_hc_base_from_port(mmio, port);  in mv_host_intr()
2963 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)  in mv_pci_error()  argument
2972 	err_cause = readl(mmio + hpriv->irq_cause_offset);  in mv_pci_error()
2977 	mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));  in mv_pci_error()
2979 	writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_pci_error()
3073 	void __iomem *mmio = hpriv->base;  in mv5_scr_read()  local
3074 	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);  in mv5_scr_read()
3087 	void __iomem *mmio = hpriv->base;  in mv5_scr_write()  local
3088 	void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);  in mv5_scr_write()
3098 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)  in mv5_reset_bus()  argument
3106 		u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_reset_bus()
3108 		writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_reset_bus()
3111 	mv_reset_pci_bus(host, mmio);  in mv5_reset_bus()
3114 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_reset_flash()  argument
3116 	writel(0x0fcfffff, mmio + FLASH_CTL);  in mv5_reset_flash()
3120 			   void __iomem *mmio)  in mv5_read_preamp()  argument
3122 	void __iomem *phy_mmio = mv5_phy_base(mmio, idx);  in mv5_read_preamp()
3131 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv5_enable_leds()  argument
3135 	writel(0, mmio + GPIO_PORT_CTL);  in mv5_enable_leds()
3139 	tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_enable_leds()
3141 	writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);  in mv5_enable_leds()
3144 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_phy_errata()  argument
3147 	void __iomem *phy_mmio = mv5_phy_base(mmio, port);  in mv5_phy_errata()
3173 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc_port()  argument
3176 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv5_reset_hc_port()
3178 	mv_reset_channel(hpriv, mmio, port);  in mv5_reset_hc_port()
3197 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_one_hc()  argument
3200 	void __iomem *hc_mmio = mv_hc_base(mmio, hc);  in mv5_reset_one_hc()
3215 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv5_reset_hc()  argument
3222 			mv5_reset_hc_port(hpriv, mmio,  in mv5_reset_hc()
3225 		mv5_reset_one_hc(hpriv, mmio, hc);  in mv5_reset_hc()
3232 #define ZERO(reg) writel(0, mmio + (reg))
3233 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)  in mv_reset_pci_bus()  argument
3238 	tmp = readl(mmio + MV_PCI_MODE);  in mv_reset_pci_bus()
3240 	writel(tmp, mmio + MV_PCI_MODE);  in mv_reset_pci_bus()
3244 	writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);  in mv_reset_pci_bus()
3255 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_reset_flash()  argument
3259 	mv5_reset_flash(hpriv, mmio);  in mv6_reset_flash()
3261 	tmp = readl(mmio + GPIO_PORT_CTL);  in mv6_reset_flash()
3264 	writel(tmp, mmio + GPIO_PORT_CTL);  in mv6_reset_flash()
3276 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_reset_hc()  argument
3279 	void __iomem *reg = mmio + PCI_MAIN_CMD_STS;  in mv6_reset_hc()
3332 			   void __iomem *mmio)  in mv6_read_preamp()  argument
3337 	tmp = readl(mmio + RESET_CFG);  in mv6_read_preamp()
3344 	port_mmio = mv_port_base(mmio, idx);  in mv6_read_preamp()
3351 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)  in mv6_enable_leds()  argument
3353 	writel(0x00000060, mmio + GPIO_PORT_CTL);  in mv6_enable_leds()
3356 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv6_phy_errata()  argument
3359 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv6_phy_errata()
3435 				      void __iomem *mmio)  in mv_soc_enable_leds()  argument
3441 			   void __iomem *mmio)  in mv_soc_read_preamp()  argument
3446 	port_mmio = mv_port_base(mmio, idx);  in mv_soc_read_preamp()
3456 					void __iomem *mmio, unsigned int port)  in mv_soc_reset_hc_port()  argument
3458 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_reset_hc_port()
3460 	mv_reset_channel(hpriv, mmio, port);  in mv_soc_reset_hc_port()
3481 				       void __iomem *mmio)  in mv_soc_reset_one_hc()  argument
3483 	void __iomem *hc_mmio = mv_hc_base(mmio, 0);  in mv_soc_reset_one_hc()
3494 				  void __iomem *mmio, unsigned int n_hc)  in mv_soc_reset_hc()  argument
3499 		mv_soc_reset_hc_port(hpriv, mmio, port);  in mv_soc_reset_hc()
3501 	mv_soc_reset_one_hc(hpriv, mmio);  in mv_soc_reset_hc()
3507 				      void __iomem *mmio)  in mv_soc_reset_flash()  argument
3512 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)  in mv_soc_reset_bus()  argument
3518 				  void __iomem *mmio, unsigned int port)  in mv_soc_65n_phy_errata()  argument
3520 	void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_soc_65n_phy_errata()
3574 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,  in mv_reset_channel()  argument
3577 	void __iomem *port_mmio = mv_port_base(mmio, port_no);  in mv_reset_channel()
3600 	hpriv->ops->phy_errata(hpriv, mmio, port_no);  in mv_reset_channel()
3640 	void __iomem *mmio = hpriv->base;  in mv_hardreset()  local
3645 	mv_reset_channel(hpriv, mmio, ap->port_no);  in mv_hardreset()
3747 	void __iomem *mmio = hpriv->base;  in mv_in_pcix_mode()  local
3752 	reg = readl(mmio + MV_PCI_MODE);  in mv_in_pcix_mode()
3761 	void __iomem *mmio = hpriv->base;  in mv_pci_cut_through_okay()  local
3765 		reg = readl(mmio + MV_PCI_COMMAND);  in mv_pci_cut_through_okay()
3775 	void __iomem *mmio = hpriv->base;  in mv_60x1b2_errata_pci7()  local
3779 		u32 reg = readl(mmio + MV_PCI_COMMAND);  in mv_60x1b2_errata_pci7()
3780 		writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);  in mv_60x1b2_errata_pci7()
3942 	void __iomem *mmio = hpriv->base;  in mv_init_host()  local
3949 		hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3950 		hpriv->main_irq_mask_addr  = mmio + SOC_HC_MAIN_IRQ_MASK;  in mv_init_host()
3952 		hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;  in mv_init_host()
3953 		hpriv->main_irq_mask_addr  = mmio + PCI_HC_MAIN_IRQ_MASK;  in mv_init_host()
3966 			hpriv->ops->read_preamp(hpriv, port, mmio);  in mv_init_host()
3968 	rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);  in mv_init_host()
3972 	hpriv->ops->reset_flash(hpriv, mmio);  in mv_init_host()
3973 	hpriv->ops->reset_bus(host, mmio);  in mv_init_host()
3974 	hpriv->ops->enable_leds(hpriv, mmio);  in mv_init_host()
3978 		void __iomem *port_mmio = mv_port_base(mmio, port);  in mv_init_host()
3984 		void __iomem *hc_mmio = mv_hc_base(mmio, hc);  in mv_init_host()
3997 		writelfl(0, mmio + hpriv->irq_cause_offset);  in mv_init_host()
4000 		writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);  in mv_init_host()