Home
last modified time | relevance | path

Searched refs:cycle (Results 1 – 200 of 228) sorted by relevance

12

/linux-4.1.27/drivers/ide/
Dide-timings.c85 u16 cycle = 0; in ide_pio_cycle_time() local
89 cycle = id[ATA_ID_EIDE_PIO_IORDY]; in ide_pio_cycle_time()
91 cycle = id[ATA_ID_EIDE_PIO]; in ide_pio_cycle_time()
94 if (pio < 3 && cycle < t->cycle) in ide_pio_cycle_time()
95 cycle = 0; /* use standard timing */ in ide_pio_cycle_time()
99 cycle = 0; in ide_pio_cycle_time()
102 return cycle ? cycle : t->cycle; in ide_pio_cycle_time()
118 q->cycle = EZ(t->cycle * 1000, T); in ide_timing_quantize()
138 m->cycle = max(a->cycle, b->cycle); in ide_timing_merge()
171 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ide_timing_compute()
[all …]
Dtx4938ide.c30 unsigned int cycle = 1000000000 / clock; in tx4938ide_tune_ebusc() local
35 wt = DIV_ROUND_UP(t->act8b, cycle) - 2; in tx4938ide_tune_ebusc()
37 wt = max_t(int, wt, DIV_ROUND_UP(35, cycle)); in tx4938ide_tune_ebusc()
43 shwt = DIV_ROUND_UP(t->setup, cycle); in tx4938ide_tune_ebusc()
46 while ((shwt * 4 + wt + (wt ? 2 : 3)) * cycle < t->cycle) in tx4938ide_tune_ebusc()
53 ebus_ch, cycle, wt, shwt); in tx4938ide_tune_ebusc()
Dpalm_bk3710.c122 cycletime = max_t(int, t->cycle, min_cycle); in palm_bk3710_setdmamode()
/linux-4.1.27/arch/avr32/mach-at32ap/
Dhsmc.c36 int cycle; in smc_set_timing() local
98 cycle = config->ncs_read_setup + config->ncs_read_pulse + recover; in smc_set_timing()
100 if (config->read_cycle < cycle) in smc_set_timing()
101 config->read_cycle = cycle; in smc_set_timing()
109 cycle = config->nrd_setup + config->nrd_pulse + recover; in smc_set_timing()
111 if (config->read_cycle < cycle) in smc_set_timing()
112 config->read_cycle = cycle; in smc_set_timing()
120 cycle = config->ncs_write_setup + config->ncs_write_pulse + recover; in smc_set_timing()
122 if (config->write_cycle < cycle) in smc_set_timing()
123 config->write_cycle = cycle; in smc_set_timing()
[all …]
/linux-4.1.27/fs/xfs/
Dxfs_sysfs.c136 int cycle; in log_head_lsn_show() local
140 cycle = log->l_curr_cycle; in log_head_lsn_show()
144 return snprintf(buf, PAGE_SIZE, "%d:%d\n", cycle, block); in log_head_lsn_show()
154 int cycle; in log_tail_lsn_show() local
157 xlog_crack_atomic_lsn(&log->l_tail_lsn, &cycle, &block); in log_tail_lsn_show()
158 return snprintf(buf, PAGE_SIZE, "%d:%d\n", cycle, block); in log_tail_lsn_show()
168 int cycle; in reserve_grant_head_show() local
171 xlog_crack_grant_head(&log->l_reserve_head.grant, &cycle, &bytes); in reserve_grant_head_show()
172 return snprintf(buf, PAGE_SIZE, "%d:%d\n", cycle, bytes); in reserve_grant_head_show()
182 int cycle; in write_grant_head_show() local
[all …]
Dxfs_log_priv.h470 xlog_crack_atomic_lsn(atomic64_t *lsn, uint *cycle, uint *block) in xlog_crack_atomic_lsn() argument
474 *cycle = CYCLE_LSN(val); in xlog_crack_atomic_lsn()
482 xlog_assign_atomic_lsn(atomic64_t *lsn, uint cycle, uint block) in xlog_assign_atomic_lsn() argument
484 atomic64_set(lsn, xlog_assign_lsn(cycle, block)); in xlog_assign_atomic_lsn()
493 xlog_crack_grant_head_val(int64_t val, int *cycle, int *space) in xlog_crack_grant_head_val() argument
495 *cycle = val >> 32; in xlog_crack_grant_head_val()
500 xlog_crack_grant_head(atomic64_t *head, int *cycle, int *space) in xlog_crack_grant_head() argument
502 xlog_crack_grant_head_val(atomic64_read(head), cycle, space); in xlog_crack_grant_head()
506 xlog_assign_grant_head_val(int cycle, int space) in xlog_assign_grant_head_val() argument
508 return ((int64_t)cycle << 32) | space; in xlog_assign_grant_head_val()
[all …]
Dxfs_log.c148 int cycle, space; in xlog_grant_sub_space() local
150 xlog_crack_grant_head_val(head_val, &cycle, &space); in xlog_grant_sub_space()
155 cycle--; in xlog_grant_sub_space()
159 new = xlog_assign_grant_head_val(cycle, space); in xlog_grant_sub_space()
175 int cycle, space; in xlog_grant_add_space() local
177 xlog_crack_grant_head_val(head_val, &cycle, &space); in xlog_grant_add_space()
184 cycle++; in xlog_grant_add_space()
188 new = xlog_assign_grant_head_val(cycle, space); in xlog_grant_add_space()
1805 __uint32_t cycle = be32_to_cpu(*(__be32 *)dptr); in xlog_sync() local
1806 if (++cycle == XLOG_HEADER_MAGIC_NUM) in xlog_sync()
[all …]
Dxfs_log_recover.c397 uint cycle) in xlog_find_cycle_start() argument
412 if (mid_cycle == cycle) in xlog_find_cycle_start()
443 uint cycle; in xlog_find_verify_cycle() local
474 cycle = xlog_get_cycle(buf); in xlog_find_verify_cycle()
475 if (cycle == stop_on_cycle_no) { in xlog_find_verify_cycle()
1203 int cycle, in xlog_add_record() argument
1212 recp->h_cycle = cpu_to_be32(cycle); in xlog_add_record()
1215 recp->h_lsn = cpu_to_be64(xlog_assign_lsn(cycle, block)); in xlog_add_record()
1224 int cycle, in xlog_write_log_records() argument
1289 xlog_add_record(log, offset, cycle, i+j, in xlog_write_log_records()
/linux-4.1.27/scripts/
Dheaderdep.pl115 my $cycle = shift;
118 for my $i (0 .. $#$cycle - 1) {
119 $cycle->[$i]->[0] = $cycle->[$i + 1]->[0];
121 $cycle->[-1]->[0] = 0;
123 my $first = shift @$cycle;
124 my $last = pop @$cycle;
129 for my $header (reverse @$cycle) {
/linux-4.1.27/drivers/ata/
Dpata_at91.c109 int *setup, int *pulse, int *cycle, int *cs_pulse) in calc_smc_vals() argument
132 *cycle += ret_val; in calc_smc_vals()
138 *cycle += ret_val; in calc_smc_vals()
140 ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle)); in calc_smc_vals()
144 *cs_pulse = *cycle; in calc_smc_vals()
155 *cycle = *cs_pulse; in calc_smc_vals()
170 static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse) in to_smc_format() argument
174 *cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1); in to_smc_format()
211 unsigned int cycle; /* SMC Cycle width in MCK ticks */ in set_smc_timing() local
220 cycle = calc_mck_cycles(ata->cyc8b, mck_hz); in set_smc_timing()
[all …]
Dpata_icside.c191 unsigned int cycle; in pata_icside_set_dmamode() local
204 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) in pata_icside_set_dmamode()
205 iomd_type = 'D', cycle = 187; in pata_icside_set_dmamode()
206 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) in pata_icside_set_dmamode()
207 iomd_type = 'C', cycle = 250; in pata_icside_set_dmamode()
208 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) in pata_icside_set_dmamode()
209 iomd_type = 'B', cycle = 437; in pata_icside_set_dmamode()
211 iomd_type = 'A', cycle = 562; in pata_icside_set_dmamode()
214 t.active, t.recover, t.cycle, iomd_type); in pata_icside_set_dmamode()
216 state->port[ap->port_no].speed[adev->devno] = cycle; in pata_icside_set_dmamode()
Dpata_acpi.c122 acpi->gtm.drive[unit].pio = t->cycle; in pacpi_set_piomode()
149 acpi->gtm.drive[unit].dma = t->cycle; in pacpi_set_dmamode()
Dlibata-core.c2954 q->cycle = EZ(t->cycle * 1000, T); in ata_timing_quantize()
2968 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle); in ata_timing_merge()
3014 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; in ata_timing_compute()
3017 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; in ata_timing_compute()
3019 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; in ata_timing_compute()
3050 if (t->active + t->recover < t->cycle) { in ata_timing_compute()
3051 t->active += (t->cycle - (t->active + t->recover)) / 2; in ata_timing_compute()
3052 t->recover = t->cycle - t->active; in ata_timing_compute()
3058 if (t->active + t->recover > t->cycle) in ata_timing_compute()
3059 t->cycle = t->active + t->recover; in ata_timing_compute()
[all …]
Dpata_ep93xx.c267 unsigned long t0 = reg ? t->cyc8b : t->cycle; in ep93xx_pata_read()
301 unsigned long t0 = reg ? t->cyc8b : t->cycle; in ep93xx_pata_write()
Dpata_octeon_cf.c172 pause = (int)timing.cycle - (int)timing.active - in octeon_cf_set_piomode()
240 T0 = timing->cycle; in octeon_cf_set_dmamode()
/linux-4.1.27/arch/alpha/lib/
Dev6-csum_ipv6_magic.S114 cmpult $20,$3,$3 # E : (1 cycle stall on $20)
115 addq $20,$18,$20 # E : U L U L (1 cycle stall on $20)
118 addq $20,$19,$20 # E : (1 cycle stall on $20)
123 addq $18,$19,$18 # E : (1 cycle stall on $19)
129 zapnot $0,15,$1 # U : Start folding output (1 cycle stall on $0)
131 srl $0,32,$0 # U : U L U L : (1 cycle stall on $0)
134 extwl $1,2,$2 # U : ushort[1] (1 cycle stall on $1)
135 zapnot $1,3,$0 # U : ushort[0] (1 cycle stall on $1)
136 extwl $1,4,$1 # U : ushort[2] (1 cycle stall on $1)
141 extwl $3,2,$1 # U : ushort[1] (1 cycle stall on $3)
[all …]
Dev6-memchr.S66 extqh $6, $16, $6 # U : 2 cycle stall for $6
106 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
109 addq $0, 2, $3 # E : U L U L : 2 cycle stall on $0
111 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
114 addq $0, 1, $3 # E : U L U L : 2 cycle stall on $0
116 cmoveq $1, $3, $0 # E : Latency 2, extra map cycle
Dev6-memset.S172 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
349 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
536 cmovlt $2, $7, $4 # E : Latency 2, extra mapping cycle
Dev6-stxcpy.S80 cmpbge zero, t1, t8 # E : (3 cycle stall)
252 zap t0, t8, t0 # U : kill dest bytes <= null (2 cycle data stall)
Dev6-copy_user.S67 beq $3, $destaligned # .. U .. .. : 2nd (one cycle fetcher stall)
Dev6-stxncpy.S199 extqh t2, a1, t4 # U : (3 cycle stall on t2)
259 extqh t2, a1, t0 # U : extract low bits (2 cycle stall)
Dev6-clear_user.S170 cmovlt $5, $6, $3 # E : U L L U : Latency 2, extra mapping cycle
/linux-4.1.27/drivers/vme/bridges/
Dvme_tsi148.c557 dma_addr_t pci_base, u32 aspace, u32 cycle) in tsi148_slave_set() argument
645 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_slave_set()
659 if (cycle & VME_BLT) in tsi148_slave_set()
661 if (cycle & VME_MBLT) in tsi148_slave_set()
663 if (cycle & VME_2eVME) in tsi148_slave_set()
665 if (cycle & VME_2eSST) in tsi148_slave_set()
667 if (cycle & VME_2eSSTB) in tsi148_slave_set()
675 if (cycle & VME_SUPER) in tsi148_slave_set()
677 if (cycle & VME_USER) in tsi148_slave_set()
679 if (cycle & VME_PROG) in tsi148_slave_set()
[all …]
Dvme_ca91cx42.c343 dma_addr_t pci_base, u32 aspace, u32 cycle) in ca91cx42_slave_set() argument
427 if (cycle & VME_SUPER) in ca91cx42_slave_set()
429 if (cycle & VME_USER) in ca91cx42_slave_set()
431 if (cycle & VME_PROG) in ca91cx42_slave_set()
433 if (cycle & VME_DATA) in ca91cx42_slave_set()
449 dma_addr_t *pci_base, u32 *aspace, u32 *cycle) in ca91cx42_slave_get() argument
476 *cycle = 0; in ca91cx42_slave_get()
493 *cycle |= VME_SUPER; in ca91cx42_slave_get()
495 *cycle |= VME_USER; in ca91cx42_slave_get()
497 *cycle |= VME_PROG; in ca91cx42_slave_get()
[all …]
/linux-4.1.27/drivers/clocksource/
Dtimer-atmel-pit.c46 u32 cycle; member
88 elapsed += PIT_PICNT(t) * data->cycle; in read_pit_clk()
104 data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); in pit_clkevt_mode()
106 (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); in pit_clkevt_mode()
115 (data->cycle - 1) | AT91_PIT_PITEN); in pit_clkevt_mode()
141 (data->cycle - 1) | AT91_PIT_PITEN); in at91sam926x_pit_reset()
172 data->cnt += data->cycle; in at91sam926x_pit_interrupt()
197 data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); in at91sam926x_pit_common_init()
198 WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); in at91sam926x_pit_common_init()
207 bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; in at91sam926x_pit_common_init()
/linux-4.1.27/tools/power/cpupower/bench/
Dbenchmark.c93 unsigned int _round, cycle; in start_benchmark() local
138 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
164 for (cycle = 0; cycle < config->cycles; cycle++) { in start_benchmark()
/linux-4.1.27/Documentation/devicetree/bindings/spi/
Dsh-msiof.txt36 50 (0.5-clock-cycle delay)
37 100 (1-clock-cycle delay)
38 150 (1.5-clock-cycle delay)
39 200 (2-clock-cycle delay)
44 50 (0.5-clock-cycle delay)
45 100 (1-clock-cycle delay)
46 150 (1.5-clock-cycle delay)
47 200 (2-clock-cycle delay)
48 300 (3-clock-cycle delay)
/linux-4.1.27/drivers/vme/
Dvme.c154 u32 aspace, cycle, dwidth; in vme_get_size() local
159 &aspace, &cycle, &dwidth); in vme_get_size()
165 &buf_base, &aspace, &cycle); in vme_get_size()
232 u32 cycle) in vme_slave_request() argument
259 ((slave_image->cycle_attr & cycle) == cycle) && in vme_slave_request()
297 dma_addr_t buf_base, u32 aspace, u32 cycle) in vme_slave_set() argument
316 ((image->cycle_attr & cycle) == cycle))) { in vme_slave_set()
326 aspace, cycle); in vme_slave_set()
332 dma_addr_t *buf_base, u32 *aspace, u32 *cycle) in vme_slave_get() argument
350 aspace, cycle); in vme_slave_get()
[all …]
Dvme_bridge.h47 u32 cycle; member
/linux-4.1.27/arch/mips/dec/
Dkn02xa-berr.c57 const char *kind, *agent, *cycle, *event; in dec_kn02xa_be_backend() local
76 cycle = mreadstr; in dec_kn02xa_be_backend()
79 cycle = invoker ? writestr : readstr; in dec_kn02xa_be_backend()
88 kind, agent, cycle, event, address); in dec_kn02xa_be_backend()
Dkn01-berr.c85 const char *kind, *agent, *cycle, *event; in dec_kn01_be_backend() local
130 cycle = mreadstr; in dec_kn01_be_backend()
133 cycle = invoker ? writestr : readstr; in dec_kn01_be_backend()
142 kind, agent, cycle, event, address); in dec_kn01_be_backend()
Decc-berr.c58 const char *kind, *agent, *cycle, *event; in dec_ecc_be_backend() local
85 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr; in dec_ecc_be_backend()
89 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr; in dec_ecc_be_backend()
189 kind, agent, cycle, event, address); in dec_ecc_be_backend()
/linux-4.1.27/Documentation/devicetree/bindings/mtd/
Dgpmc-nor.txt21 - gpmc,access-ns: Start cycle to first data capture (read access)
22 - gpmc,rd-cycle-ns: Total read cycle time
23 - gpmc,wr-cycle-ns: Total write cycle time
70 gpmc,rd-cycle-ns = <186>;
71 gpmc,wr-cycle-ns = <186>;
Dfsmc-nand.txt25 one cycle, 255 means 256 cycles.
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
30 command is asserted. Zero means one cycle, 255 means 256
Dgpmc-nand.txt83 gpmc,rd-cycle-ns = <82>;
84 gpmc,wr-cycle-ns = <82>;
/linux-4.1.27/Documentation/hwmon/
Ddme1737144 cycle) of the input. The chip adjusts the sampling rate based on this value.
155 manual mode, the fan speed is set by writing the duty-cycle value to the
157 current duty-cycle as set by the fan controller in the chip. All PWM outputs
174 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
175 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
176 pwm[1-3]_auto_pwm_min min-speed duty-cycle
183 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
186 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
189 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
190 all PWM outputs are set to 100% duty-cycle.
[all …]
Dvt1211181 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
182 pwm[1-2]_auto_point3_pwm high speed duty-cycle
183 pwm[1-2]_auto_point2_pwm low speed duty-cycle
184 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
194 PWM output duty-cycle based on the input temperature:
199 full speed duty-cycle full speed duty-cycle
201 high speed duty-cycle full speed duty-cycle
203 low speed duty-cycle high speed duty-cycle
205 off duty-cycle low speed duty-cycle
Dlm9398 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
99 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
104 contains a value controlling the duty cycle for the PWM signal used when
106 indicating minimum duty cycle and 15 indicating maximum.
137 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
138 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
142 cycle chosen by the h/w.
218 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
219 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
221 file has the same representation as other PWM duty cycle values. The
[all …]
Dmax663938 pwm1 RW Fan 1 target duty cycle (0..255)
39 pwm2 RW Fan 2 target duty cycle (0..255)
Df71882fg99 There are 2 modes to specify the speed of the fan, PWM duty cycle (or DC
100 voltage) mode, where 0-100% duty cycle (0-100% of 12V) is specified. And RPM
122 You ask for a specific PWM duty cycle / DC voltage or a specific % of
133 * 3: Thermostat mode (Only available on the F8000 when in duty cycle mode)
Dw83792d133 specific speed set by pwm# and automatically controlled its PWM duty cycle
137 cycle will increase slowly.
143 (3) If the temperature goes below the low limit, PWM duty cycle will decrease
160 pwm[1-3] - this file stores PWM duty cycle or DC value (fan speed) in range:
Dadm924055 The measurement cycle
62 ADM9240 has a very fast 320us temperature and voltage measurement cycle
66 DS1780 measurement cycle is about once per second including fan speed.
68 LM81 measurement cycle is about once per 400ms including fan speed.
Dw83l786ng44 pwm[1-2] - this file stores PWM duty cycle or DC value (fan speed) in range:
Dg760a20 cycle counts of an assumed 32kHz clock source.
Dabituguru-datasheet125 ready mode, so that it is ready for the next read / write cycle. This way
145 ready mode, so that it is ready for the next read / write cycle. This way
312 the read/write cycle for the non sensor part is different from the sensor part.
Dw83791d78 Each fan controlled is controlled by PWM. The PWM duty cycle can be read and
Df71805f152 You ask for a specific PWM duty cycle or DC voltage by writing to the
Dnct677587 pwm[1-5] - this file stores PWM duty cycle or DC value (fan speed) in range:
Dw83627ehf103 pwm[1-4] - this file stores PWM duty cycle or DC value (fan speed) in range:
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-fs-xfs7 log. The LSN is exported in "cycle:basic block" format.
16 log. The LSN is exported in "cycle:basic block" format.
26 "cycle:bytes" format.
38 "cycle:bytes" format.
Dsysfs-driver-samsung-laptop25 Description: Max battery charge level can be modified, battery cycle
Dsysfs-class-pwm62 Sets the PWM signal duty cycle in nanoseconds.
Dsysfs-class-cxl179 card. A power cycle is required to load the image.
Dsysfs-bus-coresight-devices-etm3x149 context ID size and cycle accurate tracing. Driver specific
/linux-4.1.27/Documentation/devicetree/bindings/net/
Dgpmc-eth.txt36 - gpmc,access-ns: Start cycle to first data capture (read access)
37 - gpmc,rd-cycle-ns: Total read cycle time
38 - gpmc,wr-cycle-ns: Total write cycle time
78 gpmc,rd-cycle-ns = <186>;
79 gpmc,wr-cycle-ns = <186>;
/linux-4.1.27/arch/arm/boot/dts/
Domap3430-sdp.dts76 gpmc,rd-cycle-ns = <186>;
77 gpmc,wr-cycle-ns = <186>;
122 gpmc,rd-cycle-ns = <72>;
123 gpmc,wr-cycle-ns = <72>;
167 gpmc,rd-cycle-ns = <108>;
168 gpmc,wr-cycle-ns = <96>;
Domap-gpmc-smsc911x.dtsi39 gpmc,rd-cycle-ns = <155>;
40 gpmc,wr-cycle-ns = <155>;
Domap-gpmc-smsc9221.dtsi42 gpmc,rd-cycle-ns = <60>;
43 gpmc,wr-cycle-ns = <54>;
Domap2420-h4.dts44 gpmc,rd-cycle-ns = <170>;
45 gpmc,wr-cycle-ns = <170>;
Domap2430-sdp.dts61 gpmc,rd-cycle-ns = <187>;
62 gpmc,wr-cycle-ns = <187>;
Domap2420-n8x0-common.dtsi68 gpmc,rd-cycle-ns = <145>;
69 gpmc,wr-cycle-ns = <136>;
Domap-zoom-common.dtsi41 gpmc,rd-cycle-ns = <155>;
42 gpmc,wr-cycle-ns = <155>;
Dimx6dl-tx6u-811x.dts32 * the PWM value and the actual duty cycle
54 * the PWM value and the actual duty cycle
Dimx6q-tx6q-1110.dts32 * the PWM value and the actual duty cycle
54 * the PWM value and the actual duty cycle
Domap3-sb-t35.dtsi123 gpmc,rd-cycle-ns = <155>;
124 gpmc,wr-cycle-ns = <155>;
Domap3-devkit8000.dts126 gpmc,rd-cycle-ns = <82>;
127 gpmc,wr-cycle-ns = <82>;
Ddm8168-evm.dts107 gpmc,rd-cycle-ns = <82>;
108 gpmc,wr-cycle-ns = <82>;
Domap4-duovero-parlor.dts157 gpmc,rd-cycle-ns = <50>;
158 gpmc,wr-cycle-ns = <50>;
Domap3-n950-n9.dtsi148 gpmc,rd-cycle-ns = <112>;
149 gpmc,wr-cycle-ns = <112>;
Domap3-lilly-a83x.dtsi385 gpmc,rd-cycle-ns = <100>;
386 gpmc,wr-cycle-ns = <100>;
438 gpmc,rd-cycle-ns = <100>;
439 gpmc,wr-cycle-ns = <100>;
Domap3-igep.dtsi120 gpmc,rd-cycle-ns = <82>;
121 gpmc,wr-cycle-ns = <82>;
Dam335x-chilisom.dtsi228 gpmc,rd-cycle-ns = <82>;
229 gpmc,wr-cycle-ns = <82>;
Domap3-evm-37xx.dts177 gpmc,rd-cycle-ns = <82>;
178 gpmc,wr-cycle-ns = <82>;
Domap3-lilly-dbb056.dts149 gpmc,rd-cycle-ns = <100>;
150 gpmc,wr-cycle-ns = <100>;
Dimx6dl-tx6dl-comtft.dts30 * the PWM value and the actual duty cycle
Dimx6q-tx6q-1010-comtft.dts30 * the PWM value and the actual duty cycle
Dam335x-igep0033.dtsi148 gpmc,rd-cycle-ns = <82>;
149 gpmc,wr-cycle-ns = <82>;
Dimx6q-tx6q-1020-comtft.dts30 * the PWM value and the actual duty cycle
Domap3-ldp.dts120 gpmc,rd-cycle-ns = <82>;
121 gpmc,wr-cycle-ns = <82>;
Domap3-cm-t3x.dtsi290 gpmc,rd-cycle-ns = <120>;
291 gpmc,wr-cycle-ns = <120>;
Domap3-tao3530.dtsi296 gpmc,rd-cycle-ns = <72>;
297 gpmc,wr-cycle-ns = <72>;
Dimx6dl-tx6u-801x.dts30 * the PWM value and the actual duty cycle
Dimx6q-tx6q-1010.dts30 * the PWM value and the actual duty cycle
Domap3-beagle.dts405 gpmc,rd-cycle-ns = <72>;
406 gpmc,wr-cycle-ns = <72>;
Dimx6q-tx6q-1020.dts30 * the PWM value and the actual duty cycle
Dpxa910-dkb.dts143 marvell,88pm860x-gpadc-slot-cycle = <1>;
Dam335x-nano.dts273 gpmc,rd-cycle-ns = <160>;
274 gpmc,wr-cycle-ns = <160>;
Domap3-gta04.dtsi481 gpmc,rd-cycle-ns = <82>;
482 gpmc,wr-cycle-ns = <82>;
Domap3-n900.dts736 gpmc,rd-cycle-ns = <112>;
737 gpmc,wr-cycle-ns = <112>;
804 gpmc,rd-cycle-ns = <180>;
805 gpmc,wr-cycle-ns = <180>;
Dste-href.dtsi138 full-pwr-cycle;
Ddra72-evm.dts316 gpmc,rd-cycle-ns = <80>;
317 gpmc,wr-cycle-ns = <80>;
Domap3-pandora-common.dtsi517 gpmc,rd-cycle-ns = <82>;
518 gpmc,wr-cycle-ns = <82>;
Ddra7-evm.dts592 gpmc,rd-cycle-ns = <80>;
593 gpmc,wr-cycle-ns = <80>;
Dam335x-evm.dts466 gpmc,rd-cycle-ns = <82>;
467 gpmc,wr-cycle-ns = <82>;
Dam437x-gp-evm.dts536 gpmc,rd-cycle-ns = <40>;
537 gpmc,wr-cycle-ns = <40>;
Dam43x-epos-evm.dts495 gpmc,rd-cycle-ns = <40>;
496 gpmc,wr-cycle-ns = <40>;
Dimx28-tx28.dts159 * PWM value and the actual duty cycle
Dste-nomadik-stn8815.dtsi801 full-pwr-cycle;
/linux-4.1.27/Documentation/devicetree/bindings/video/backlight/
Dpwm-backlight.txt8 The actual brightness level (PWM duty cycle) will be interpolated
9 from these values. 0 means a 0% duty cycle (darkest/off), while the
10 last value in the array represents a 100% duty cycle (brightest).
/linux-4.1.27/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt40 cycle from a slow device.
53 ALE[0] to the cycle that the first read data is sampled
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
58 samples data N and the cycle that samples data N+1
64 DEV_OEn and DEV_CSn are asserted at the same cycle.
73 DEV_OEn and DEV_CSn are de-asserted at the same cycle
74 (the cycle of the last data sample).
76 DEV_OEn is always de-asserted the next cycle after
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
Dti-aemif.txt103 Time between the beginning of a memory cycle
114 strobe and the end of the cycle (which may be
120 Time between the beginning of a memory cycle
131 strobe and the end of the cycle (which may be
/linux-4.1.27/drivers/staging/vme/devices/
Dvme_user.h14 __u32 cycle; /* Cycle properties */ member
38 __u32 cycle; /* Cycle properties */ member
Dvme_user.c495 &master.cycle, &master.dwidth); in vme_user_ioctl()
524 master.aspace, master.cycle, master.dwidth); in vme_user_ioctl()
540 &slave.cycle); in vme_user_ioctl()
565 slave.cycle); in vme_user_ioctl()
/linux-4.1.27/Documentation/
Ddcdbas.txt5 management interrupts and host control actions (system power cycle or
48 to perform a power cycle or power off of the system after the OS has finished
53 to schedule the driver to perform a power cycle or power off host control
60 Dell OpenManage performs the following steps to execute a power cycle or
74 perform a power cycle or power off host control action:
Dvme_api.txt89 u32 aspace, u32 cycle, u32 width);
92 u32 cycle);
97 need to be accessed in 'aspace' and VME bus cycle types required in 'cycle'.
137 u32 cycle, u32 width);
141 u32 *cycle, u32 *width);
143 The address spaces, transfer widths and cycle types are the same as described
192 dma_addr_t mem, u32 aspace, u32 cycle);
196 dma_addr_t *mem, u32 *aspace, u32 *cycle);
198 The address spaces, transfer widths and cycle types are the same as described
285 u32 aspace, u32 cycle, u32 width);
[all …]
Dstable_kernel_rules.txt103 Review cycle:
105 - When the -stable maintainers decide for a review cycle, the patches will be
113 - At the end of the review cycle, the ACKed patches will be added to the
116 security kernel team, and not go through the normal review cycle.
Dpwm.txt103 characterizes a signal starts high for the duration of the duty cycle and
105 polarity starts low for the duration of the duty cycle and goes high for the
Dstatic-keys.txt260 1,178,049,567 instructions # 0.80 insns per cycle ( +- 0.06% )
277 1,175,363,994 instructions # 0.82 insns per cycle ( +- 0.04% )
/linux-4.1.27/arch/blackfin/mach-common/
Dpm.c263 u32 cycle, cycle2; in bfin_pm_end() local
273 : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC" in bfin_pm_end()
276 usec64 = ((u64)cycle2 << 32) + cycle; in bfin_pm_end()
/linux-4.1.27/Documentation/devicetree/bindings/bus/
Dti-gpmc.txt58 Access time and cycle time timings (in nanoseconds) corresponding to
61 - gpmc,access-ns: Start-cycle to first data valid delay
62 - gpmc,rd-cycle-ns: Total read cycle time
63 - gpmc,wr-cycle-ns: Total write cycle time
/linux-4.1.27/arch/arm/crypto/
Dsha1-armv4-large.S230 eor r11,r11,r12 @ 1 cycle stall
247 eor r11,r11,r12 @ 1 cycle stall
264 eor r11,r11,r12 @ 1 cycle stall
281 eor r11,r11,r12 @ 1 cycle stall
302 eor r11,r11,r12 @ 1 cycle stall
318 eor r11,r11,r12 @ 1 cycle stall
334 eor r11,r11,r12 @ 1 cycle stall
350 eor r11,r11,r12 @ 1 cycle stall
366 eor r11,r11,r12 @ 1 cycle stall
391 eor r11,r11,r12 @ 1 cycle stall
[all …]
/linux-4.1.27/arch/mips/include/asm/octeon/
Dcvmx.h373 uint64_t cycle; in cvmx_get_cycle() local
374 CVMX_RDHWR(cycle, 31); in cvmx_get_cycle()
375 return cycle; in cvmx_get_cycle()
/linux-4.1.27/sound/firewire/
Damdtp.c355 unsigned int cycle) in calculate_syt() argument
388 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; in calculate_syt()
785 static void out_stream_callback(struct fw_iso_context *context, u32 cycle, in out_stream_callback() argument
797 cycle += QUEUE_LENGTH - packets; in out_stream_callback()
800 syt = calculate_syt(s, ++cycle); in out_stream_callback()
806 static void in_stream_callback(struct fw_iso_context *context, u32 cycle, in in_stream_callback() argument
853 static void slave_stream_callback(struct fw_iso_context *context, u32 cycle, in slave_stream_callback() argument
862 u32 cycle, size_t header_length, in amdtp_stream_first_callback() argument
881 context->callback.sc(context, cycle, header_length, header, s); in amdtp_stream_first_callback()
Disight.c165 static void isight_packet(struct fw_iso_context *context, u32 cycle, in isight_packet() argument
/linux-4.1.27/drivers/staging/media/lirc/
Dlirc_bt829.c48 static void cycle_delay(int cycle);
188 static void cycle_delay(int cycle) in cycle_delay() argument
190 udelay(WAIT_CYCLE*cycle); in cycle_delay()
/linux-4.1.27/arch/arm/mach-rpc/
Ddma.c201 static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle) in iomd_set_dma_speed() argument
205 if (cycle < 188) in iomd_set_dma_speed()
207 else if (cycle <= 250) in iomd_set_dma_speed()
209 else if (cycle < 438) in iomd_set_dma_speed()
/linux-4.1.27/Documentation/video4linux/bttv/
DREADME.quirks60 the cycle following GNT). When FRAME is asserted, it is the initiator s
73 during the same cycle that GNT is de-asserted. This is non PCI 2.1
78 transaction from starting the same cycle as GNT is de-asserted. This
/linux-4.1.27/Documentation/devicetree/bindings/video/
Dadi,adv7511.txt23 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
24 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
/linux-4.1.27/include/uapi/linux/
Dfirewire-cdev.h260 __u32 cycle; member
849 __s32 cycle; member
/linux-4.1.27/tools/testing/ktest/examples/include/
Ddefaults.conf71 POWER_CYCLE = ${SCRIPTS_DIR}/${BOX}-cycle
/linux-4.1.27/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt41 - adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
/linux-4.1.27/arch/powerpc/kernel/
Dsysfs.c95 u64 cycle; in get_idle_ticks_bit() local
98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec; in get_idle_ticks_bit()
100 cycle = div_u64(ns * tb_ticks_per_usec, 1000); in get_idle_ticks_bit()
102 if (!cycle) in get_idle_ticks_bit()
105 return ilog2(cycle); in get_idle_ticks_bit()
/linux-4.1.27/drivers/mtd/chips/
DKconfig123 flash chip addressed by each bus cycle, then say 'Y'.
130 flash chips addressed by each bus cycle, then say 'Y'.
137 flash chips addressed by each bus cycle, then say 'Y'.
144 flash chips addressed by each bus cycle, then say 'Y'.
/linux-4.1.27/Documentation/m68k/
DREADME.buddha137 values are no multiple of 71. One clock-cycle is 71ns long
156 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
172 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
192 clock cycle is shortened to a bit less than 70ns (not worth
/linux-4.1.27/drivers/scsi/
Desp_scsi.h241 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) argument
/linux-4.1.27/Documentation/devicetree/bindings/mmc/
Dmmc.txt36 - full-pwr-cycle: full power cycle of the card is supported
64 - keep-power-in-suspend: Preserves card power during a suspend/resume cycle
/linux-4.1.27/drivers/firewire/
Dcore-iso.c193 int cycle, int sync, int tags) in fw_iso_context_start() argument
195 return ctx->card->driver->start_iso(ctx, cycle, sync, tags); in fw_iso_context_start()
Dcore.h99 s32 cycle, u32 sync, u32 tags);
Dcore-cdev.c924 static void iso_callback(struct fw_iso_context *context, u32 cycle, in iso_callback() argument
936 e->interrupt.cycle = cycle; in iso_callback()
1181 a->cycle, a->sync, a->tags); in ioctl_start_iso()
Dcore-card.c633 s32 cycle, u32 sync, u32 tags) in dummy_start_iso() argument
Dohci.c3040 s32 cycle, u32 sync, u32 tags) in ohci_start_iso() argument
3055 if (cycle >= 0) in ohci_start_iso()
3057 (cycle & 0x7fff) << 16; in ohci_start_iso()
3070 if (cycle >= 0) { in ohci_start_iso()
3071 match |= (cycle & 0x07fff) << 12; in ohci_start_iso()
/linux-4.1.27/tools/perf/Documentation/
Dperf-bench.txt157 --cycle::
189 --cycle::
/linux-4.1.27/include/linux/
Dfirewire.h434 u32 cycle, size_t header_length,
463 int cycle, int sync, int tags);
Dlibata.h1015 unsigned short cycle; /* t0 */ member
1232 extern u8 ata_timing_cycle2mode(unsigned int xfer_shift, int cycle);
Dide.h1467 u16 cycle; /* t0 */ member
/linux-4.1.27/Documentation/power/
Dsuspend-and-cpuhotplug.txt19 On a high level, the suspend-resume cycle goes like this:
104 after the entire cycle is complete (i.e., suspend + resume).
232 hibernate/restore cycle.]
235 as part of the suspend/hibernate cycle (the CPU_DEAD_FROZEN notification),
Dsuspend-and-interrupts.txt36 suspend-resume cycle, including the "noirq" phases of suspending and resuming
44 expected during the suspend-resume cycle, but does not guarantee that the
/linux-4.1.27/Documentation/leds/
Dleds-lp3944.txt23 - duty cycle: percentage of the period the led is on, from 0 to 100
Dledtrig-transient.txt9 should stay in off state. The on and off cycle repeats until the trigger
/linux-4.1.27/Documentation/devicetree/bindings/mfd/
D88pm860x.txt60 marvell,88pm860x-gpadc-slot-cycle = <1>;
Dmax77693.txt31 users with tactile feedback. PWM period and duty-cycle are varied in
/linux-4.1.27/arch/cris/arch-v32/mm/
Dmmu.S92 ; (The pipeline stalls for one cycle; $sp used as address in the next cycle.)
/linux-4.1.27/drivers/mtd/ubi/
DKconfig25 other flashes which have eraseblock life-cycle 100000 or more.
27 life-cycle less than 10000, the threshold should be lessened (e.g.,
/linux-4.1.27/fs/xfs/libxfs/
Dxfs_log_format.h72 static inline xfs_lsn_t xlog_assign_lsn(uint cycle, uint block) in xlog_assign_lsn() argument
74 return ((xfs_lsn_t)cycle << 32) | block; in xlog_assign_lsn()
/linux-4.1.27/Documentation/device-mapper/
Ddm-flakey.txt10 interval> seconds, and then this cycle repeats.
/linux-4.1.27/arch/cris/arch-v32/lib/
Dchecksumcopy.S32 addoq -10*4, $acr, $acr ; loop counter in latency cycle
/linux-4.1.27/drivers/block/
Dskd_s1120.h256 uint8_t cycle; member
/linux-4.1.27/Documentation/development-process/
D2.Process32 cycle, the "merge window" is said to be open. At that time, code which is
35 new development cycle (and all of the major changes) will be merged during
57 best thing to do is to wait for the next development cycle. (An occasional
68 As an example, here is how the 2.6.38 development cycle went (all dates in
82 How do the developers decide when to close the development cycle and create
105 a little more than one development cycle past their initial release. So,
273 development cycle, approximately 5-10% of the patches going into the
284 The primary tree for next-cycle patch merging is linux-next, maintained by
D1.Intro23 Section 2 introduces the development process, the kernel release cycle, and
25 development, review, and merging cycle are covered. There is some
83 free software projects. A typical three-month kernel development cycle can
/linux-4.1.27/arch/arc/lib/
Dmemcmp.S42 ; one more load latency cycle
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dhead.S473 1: move.b [R_DMA_CH6_CMD],$r0 ; wait for reset cycle to finish
478 1: move.b [R_DMA_CH7_CMD],$r0 ; wait for reset cycle to finish
488 1: move.b [R_DMA_CH8_CMD],$r0 ; wait for reset cycle to finish
493 1: move.b [R_DMA_CH9_CMD],$r0 ; wait for reset cycle to finish
/linux-4.1.27/tools/testing/ktest/examples/
Dcrosstests.conf245 POWER_CYCLE = cycle
/linux-4.1.27/Documentation/video4linux/
Dcafe_ccic32 - n_dma_bufs: The controller can cycle through either two or three DMA
/linux-4.1.27/Documentation/networking/
Dnetdev-FAQ.txt73 Finally, the vX.Y gets released, and the whole cycle starts over.
75 Q: So where are we now in this cycle?
82 in the dev cycle. If it was tagged rc7 a week ago, then a release
Dmultiqueue.txt40 blocking. It will cycle though the bands and verify that the hardware queue
Dpktgen.txt152 cycle through the port range.
156 cycle through the port range.
D3c509.txt127 work during that interrupt cycle. With a status of 0x2011 you are receiving
De1000e.txt242 cycle.
/linux-4.1.27/arch/sh/lib/
Dmemcpy-sh4.S174 mov r6, r0 ! 5 MT (0 cycle latency)
183 mov r4, r0 ! 5 MT (0 cycle latency)
196 ! cycle counts for differnet sizes using byte-at-a-time vs. optimised):
/linux-4.1.27/sound/soc/fsl/
Dfsl_spdif.c301 u32 val, cycle = 1000; in spdif_softreset() local
311 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
313 if (cycle) in spdif_softreset()
/linux-4.1.27/Documentation/ABI/stable/
Dfirewire-cdev32 - Query cycle time
Dsysfs-class-tpm167 cycle. Whether a warm boot (reboot) will clear a TPM chip
/linux-4.1.27/drivers/clk/
DKconfig138 at 50% duty cycle.
/linux-4.1.27/arch/powerpc/boot/dts/
Dep405.dts205 0xeed80000 0x00000004 /* Special cycle */
Dwalnut.dts212 0xeed80000 0x00000004 /* Special cycle */
Dsam440ep.dts275 0 0xeed00000 4 /* Special cycle */
Dhotfoot.dts266 0xeed80000 0x00000004 /* Special cycle */
Dbamboo.dts265 0x00000000 0xeed00000 0x00000004 /* Special cycle */
Dyosemite.dts308 0x00000000 0xeed00000 0x00000004 /* Special cycle */
Drainier.dts326 0x00000001 0xeed00000 0x00000004 /* Special cycle */
Dsequoia.dts384 0x00000001 0xeed00000 0x00000004 /* Special cycle */
/linux-4.1.27/Documentation/usb/
DWUSB-Design-overview.txt42 2. Host Controller life cycle
190 Host Controller life cycle
275 they have to deal with WUSB device life cycle and maintenance, wireless
325 *Device life cycle and keep alives*
/linux-4.1.27/sound/sparc/
Ddbri.c886 int length, int cycle) in link_time_slot() argument
919 if (prevpipe == 16 && cycle == 0) in link_time_slot()
920 cycle = dbri->chi_bpf; in link_time_slot()
926 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); in link_time_slot()
931 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); in link_time_slot()
/linux-4.1.27/arch/sh/kernel/cpu/sh5/
Dswitchto.S106 ! do this early as pta->gettr has no pipeline forwarding (=> 5 cycle latency)
/linux-4.1.27/Documentation/i2c/busses/
Di2c-ali15x331 by a power cycle. Cause unknown (see Issues below).
/linux-4.1.27/Documentation/sysctl/
Dnet.txt143 Maximum number of packets taken from all interfaces in one polling cycle (NAPI
144 poll). In one polling cycle interfaces which are registered to polling are
/linux-4.1.27/Documentation/parisc/
Dregisters17 CR16 (Interval Timer) read for cycle count/write starts Interval Tmr
/linux-4.1.27/Documentation/frv/
Datomic-ops.txt62 manages to take place. In theory, this loop could cycle forever because there are too many
/linux-4.1.27/drivers/media/firewire/
Dfiredtv-fw.c97 static void handle_iso(struct fw_iso_context *context, u32 cycle, in handle_iso() argument
/linux-4.1.27/Documentation/x86/x86_64/
Dboot-options.txt232 forcesac Force single-address cycle (SAC) mode for masks <40bits
235 allowdac Allow double-address cycle (DAC) mode, i.e. DMA >4GB.
/linux-4.1.27/drivers/firmware/
DKconfig81 Interrupts (SMIs) and Host Control Actions (system power cycle or
/linux-4.1.27/arch/powerpc/kvm/
DKconfig134 Calculate elapsed time for every exit/enter cycle. A per-vcpu
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dcci.txt118 starting with the cycle counter overflow
/linux-4.1.27/Documentation/cgroups/
Dfreezer-subsystem.txt48 prevent the freeze/unfreeze cycle from becoming visible to the tasks
/linux-4.1.27/arch/alpha/
DKconfig608 the side effect of making the cycle counter unreliable as a timing
612 mechanisms for measuring time than the cycle counter.
617 For SMP systems we cannot use the cycle counter for timing anyway,
/linux-4.1.27/kernel/time/
DKconfig16 # cycle update - x86/TSC misfeature
/linux-4.1.27/Documentation/virtual/kvm/
Dtimekeeping.txt99 each clock to generate a full high / low cycle at the full periodic rate.
108 goes low for 1 clock cycle and returns high. The counter is not reloaded.
114 the output goes low for 1 clock cycle and then returns high. The counter is
507 As the highest precision time source available, the cycle counter of the CPU
/linux-4.1.27/drivers/net/ethernet/freescale/
Dfec_main.c2388 unsigned int cycle; in fec_enet_set_coalesce() local
2403 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr); in fec_enet_set_coalesce()
2404 if (cycle > 0xFFFF) { in fec_enet_set_coalesce()
2409 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr); in fec_enet_set_coalesce()
2410 if (cycle > 0xFFFF) { in fec_enet_set_coalesce()
/linux-4.1.27/Documentation/filesystems/
Ddirectory-locking122 not introduce a cycle will leave it a tree and link() fails for directories).
Dxfs-delayed-logging-design.txt687 The existing log item life cycle is as follows:
732 With delayed logging, there are new steps inserted into the life cycle:
780 From this, it can be seen that the only life cycle differences between the two
781 logging methods are in the middle of the life cycle - they still have the same
/linux-4.1.27/Documentation/dmaengine/
Dprovider.txt24 parameter: the transfer size. At each clock cycle, it would transfer a
30 cycle. For example, we may want to transfer as much data as the
/linux-4.1.27/drivers/media/common/siano/
Dsmscoreapi.h910 u32 cycle; member
/linux-4.1.27/arch/arc/
DKconfig327 bool "Insn: RTSC (64-bit r/o cycle counter)"
/linux-4.1.27/Documentation/PCI/
Dpci-error-recovery.txt306 cycle) and then call slot_reset() again. It the device still can't
336 >>> The current powerpc implementation does not try a power-cycle
/linux-4.1.27/Documentation/timers/
Dtimekeeping.txt41 and the higher 16 bits in a second bus cycle with the counter bits
/linux-4.1.27/Documentation/RCU/
Dstallwarn.txt19 this parameter is checked only at the beginning of a cycle.
Dtorture.txt153 cycle. Defaults to "test_boost_interval=7". It is
/linux-4.1.27/Documentation/spi/
Dspi-summary17 commonly used. Each clock cycle shifts data out and data in; the clock
18 doesn't cycle except when there is a data bit to shift. Not all data bits
/linux-4.1.27/Documentation/laptops/
Dthinkpad-acpi.txt406 sleep cycle is performed or some
420 0x1007 0x06 FN+F7 Video output cycle.
438 ACPI sleep cycle is performed,
557 cycle, or a system shutdown. Obviously, something is very wrong if this
/linux-4.1.27/drivers/atm/
DKconfig68 multiple words of data per PCI bus access cycle. Such a multi-word

12