1Analog Devices ADF4350/ADF4351 device driver
2
3Required properties:
4	- compatible: Should be one of
5		* "adi,adf4350": When using the ADF4350 device
6		* "adi,adf4351": When using the ADF4351 device
7	- reg: SPI chip select numbert for the device
8	- spi-max-frequency: Max SPI frequency to use (< 20000000)
9	- clocks: From common clock binding. Clock is phandle to clock for
10		ADF435x Reference Clock (CLKIN).
11
12Optional properties:
13	- gpios:	 GPIO Lock detect - If set with a valid phandle and GPIO number,
14			pll lock state is tested upon read.
15	- adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16	- adi,power-up-frequency:	If set in Hz the PLL tunes to
17			the desired frequency on probe.
18	- adi,reference-div-factor: If set the driver skips dynamic calculation
19			and uses this default value instead.
20	- adi,reference-doubler-enable: Enables reference doubler.
21	- adi,reference-div2-enable: Enables reference divider.
22	- adi,phase-detector-polarity-positive-enable: Enables positive phase
23			detector polarity. Default = negative.
24	- adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
25			Default = 10ns.
26	- adi,lock-detect-function-integer-n-enable: Enables lock detect
27			for integer-N mode. Default = factional-N mode.
28	- adi,charge-pump-current: Charge pump current in mA.
29			Default = 2500mA.
30	- adi,muxout-select: On chip multiplexer output selection.
31			Valid values for the multiplexer output are:
32			0: Three-State Output (default)
33			1: DVDD
34			2: DGND
35			3: R-Counter output
36			4: N-Divider output
37			5: Analog lock detect
38			6: Digital lock detect
39	- adi,low-spur-mode-enable: Enables low spur mode.
40			Default = Low noise mode.
41	- adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
42	- adi,charge-cancellation-enable: Enabled charge pump
43			charge cancellation for integer-N modes.
44	- adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
45			 for integer-N modes.
46	- adi,band-select-clock-mode-high-enable: Enables faster band
47			selection logic.
48	- adi,12bit-clk-divider: Clock divider value used when
49			adi,12bit-clkdiv-mode != 0
50	- adi,clk-divider-mode:
51			Valid values for the clkdiv mode are:
52			0: Clock divider off (default)
53			1: Fast lock enable
54			2: Phase resync enable
55	- adi,aux-output-enable: Enables auxiliary RF output.
56	- adi,aux-output-fundamental-enable: Selects fundamental VCO output on
57			the auxiliary RF output. Default = Output of RF dividers.
58	- adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
59	- adi,output-power: Output power selection.
60			Valid values for the power mode are:
61			0: -4dBm (default)
62			1: -1dBm
63			2: +2dBm
64			3: +5dBm
65	- adi,aux-output-power: Auxiliary output power selection.
66			Valid values for the power mode are:
67			0: -4dBm (default)
68			1: -1dBm
69			2: +2dBm
70			3: +5dBm
71
72
73Example:
74		lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
75			compatible = "adi,adf4351";
76			reg = <4>;
77			spi-max-frequency = <10000000>;
78			clocks = <&clk0_ad9523 9>;
79			clock-names = "clkin";
80			adi,channel-spacing = <10000>;
81			adi,power-up-frequency = <2400000000>;
82			adi,phase-detector-polarity-positive-enable;
83			adi,charge-pump-current = <2500>;
84			adi,output-power = <3>;
85			adi,mute-till-lock-enable;
86		};
87