1=======================================================
2ARM CCI cache coherent interconnect binding description
3=======================================================
4
5ARM multi-cluster systems maintain intra-cluster coherency through a
6cache coherent interconnect (CCI) that is capable of monitoring bus
7transactions and manage coherency, TLB invalidations and memory barriers.
8
9It allows snooping and distributed virtual memory message broadcast across
10clusters, through memory mapped interface, with a global control register
11space and multiple sets of interface control registers, one per slave
12interface.
13
14Bindings for the CCI node follow the ePAPR standard, available from:
15
16www.power.org/documentation/epapr-version-1-1/
17
18with the addition of the bindings described in this document which are
19specific to ARM.
20
21* CCI interconnect node
22
23	Description: Describes a CCI cache coherent Interconnect component
24
25	Node name must be "cci".
26	Node's parent must be the root node /, and the address space visible
27	through the CCI interconnect is the same as the one seen from the
28	root node (ie from CPUs perspective as per DT standard).
29	Every CCI node has to define the following properties:
30
31	- compatible
32		Usage: required
33		Value type: <string>
34		Definition: must be set to
35			    "arm,cci-400"
36
37	- reg
38		Usage: required
39		Value type: Integer cells. A register entry, expressed as a pair
40			    of cells, containing base and size.
41		Definition: A standard property. Specifies base physical
42			    address of CCI control registers common to all
43			    interfaces.
44
45	- ranges:
46		Usage: required
47		Value type: Integer cells. An array of range entries, expressed
48			    as a tuple of cells, containing child address,
49			    parent address and the size of the region in the
50			    child address space.
51		Definition: A standard property. Follow rules in the ePAPR for
52			    hierarchical bus addressing. CCI interfaces
53			    addresses refer to the parent node addressing
54			    scheme to declare their register bases.
55
56	CCI interconnect node can define the following child nodes:
57
58	- CCI control interface nodes
59
60		Node name must be "slave-if".
61		Parent node must be CCI interconnect node.
62
63		A CCI control interface node must contain the following
64		properties:
65
66		- compatible
67			Usage: required
68			Value type: <string>
69			Definition: must be set to
70				    "arm,cci-400-ctrl-if"
71
72		- interface-type:
73			Usage: required
74			Value type: <string>
75			Definition: must be set to one of {"ace", "ace-lite"}
76				    depending on the interface type the node
77				    represents.
78
79		- reg:
80			Usage: required
81			Value type: Integer cells. A register entry, expressed
82				    as a pair of cells, containing base and
83				    size.
84			Definition: the base address and size of the
85				    corresponding interface programming
86				    registers.
87
88	- CCI PMU node
89
90		Parent node must be CCI interconnect node.
91
92		A CCI pmu node must contain the following properties:
93
94		- compatible
95			Usage: required
96			Value type: <string>
97			Definition: Must contain one of:
98				 "arm,cci-400-pmu,r0"
99				 "arm,cci-400-pmu,r1"
100				 "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has
101						      secure acces to CCI registers
102		- reg:
103			Usage: required
104			Value type: Integer cells. A register entry, expressed
105				    as a pair of cells, containing base and
106				    size.
107			Definition: the base address and size of the
108				    corresponding interface programming
109				    registers.
110
111		- interrupts:
112			Usage: required
113			Value type: Integer cells. Array of interrupt specifier
114				    entries, as defined in
115				    ../interrupt-controller/interrupts.txt.
116			Definition: list of counter overflow interrupts, one per
117				    counter. The interrupts must be specified
118				    starting with the cycle counter overflow
119				    interrupt, followed by counter0 overflow
120				    interrupt, counter1 overflow interrupt,...
121				    ,counterN overflow interrupt.
122
123				    The CCI PMU has an interrupt signal for each
124				    counter. The number of interrupts must be
125				    equal to the number of counters.
126
127* CCI interconnect bus masters
128
129	Description: masters in the device tree connected to a CCI port
130		     (inclusive of CPUs and their cpu nodes).
131
132	A CCI interconnect bus master node must contain the following
133	properties:
134
135	- cci-control-port:
136		Usage: required
137		Value type: <phandle>
138		Definition: a phandle containing the CCI control interface node
139			    the master is connected to.
140
141Example:
142
143	cpus {
144		#size-cells = <0>;
145		#address-cells = <1>;
146
147		CPU0: cpu@0 {
148			device_type = "cpu";
149			compatible = "arm,cortex-a15";
150			cci-control-port = <&cci_control1>;
151			reg = <0x0>;
152		};
153
154		CPU1: cpu@1 {
155			device_type = "cpu";
156			compatible = "arm,cortex-a15";
157			cci-control-port = <&cci_control1>;
158			reg = <0x1>;
159		};
160
161		CPU2: cpu@100 {
162			device_type = "cpu";
163			compatible = "arm,cortex-a7";
164			cci-control-port = <&cci_control2>;
165			reg = <0x100>;
166		};
167
168		CPU3: cpu@101 {
169			device_type = "cpu";
170			compatible = "arm,cortex-a7";
171			cci-control-port = <&cci_control2>;
172			reg = <0x101>;
173		};
174
175	};
176
177	dma0: dma@3000000 {
178		compatible = "arm,pl330", "arm,primecell";
179		cci-control-port = <&cci_control0>;
180		reg = <0x0 0x3000000 0x0 0x1000>;
181		interrupts = <10>;
182		#dma-cells = <1>;
183		#dma-channels = <8>;
184		#dma-requests = <32>;
185	};
186
187	cci@2c090000 {
188		compatible = "arm,cci-400";
189		#address-cells = <1>;
190		#size-cells = <1>;
191		reg = <0x0 0x2c090000 0 0x1000>;
192		ranges = <0x0 0x0 0x2c090000 0x10000>;
193
194		cci_control0: slave-if@1000 {
195			compatible = "arm,cci-400-ctrl-if";
196			interface-type = "ace-lite";
197			reg = <0x1000 0x1000>;
198		};
199
200		cci_control1: slave-if@4000 {
201			compatible = "arm,cci-400-ctrl-if";
202			interface-type = "ace";
203			reg = <0x4000 0x1000>;
204		};
205
206		cci_control2: slave-if@5000 {
207			compatible = "arm,cci-400-ctrl-if";
208			interface-type = "ace";
209			reg = <0x5000 0x1000>;
210		};
211
212		pmu@9000 {
213			 compatible = "arm,cci-400-pmu";
214			 reg = <0x9000 0x5000>;
215			 interrupts = <0 101 4>,
216				      <0 102 4>,
217				      <0 103 4>,
218				      <0 104 4>,
219				      <0 105 4>;
220		};
221	};
222
223This CCI node corresponds to a CCI component whose control registers sits
224at address 0x000000002c090000.
225CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
226CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
227CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
228