| /linux-4.1.27/drivers/isdn/hisax/ |
| H A D | icc.c | 32 ICCVersion(struct IsdnCardState *cs, char *s) ICCVersion() argument
36 val = cs->readisac(cs, ICC_RBCH); ICCVersion()
41 ph_command(struct IsdnCardState *cs, unsigned int command) ph_command() argument
43 if (cs->debug & L1_DEB_ISAC) ph_command()
44 debugl1(cs, "ph_command %x", command); ph_command()
45 cs->writeisac(cs, ICC_CIX0, (command << 2) | 3); ph_command()
50 icc_new_ph(struct IsdnCardState *cs) icc_new_ph() argument
52 switch (cs->dc.icc.ph_state) { icc_new_ph()
54 ph_command(cs, ICC_CMD_DI); icc_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); icc_new_ph()
58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); icc_new_ph()
61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); icc_new_ph()
64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); icc_new_ph()
67 l1_msg(cs, HW_RSYNC | INDICATION, NULL); icc_new_ph()
70 l1_msg(cs, HW_INFO2 | INDICATION, NULL); icc_new_ph()
73 l1_msg(cs, HW_INFO4 | INDICATION, NULL); icc_new_ph()
83 struct IsdnCardState *cs = icc_bh() local
87 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { icc_bh()
88 if (cs->debug) icc_bh()
89 debugl1(cs, "D-Channel Busy cleared"); icc_bh()
90 stptr = cs->stlist; icc_bh()
96 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) icc_bh()
97 icc_new_ph(cs); icc_bh()
98 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) icc_bh()
99 DChannel_proc_rcv(cs); icc_bh()
100 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) icc_bh()
101 DChannel_proc_xmt(cs); icc_bh()
103 if (!test_bit(HW_ARCOFI, &cs->HW_Flags)) icc_bh()
105 if (test_and_clear_bit(D_RX_MON1, &cs->event)) icc_bh()
106 arcofi_fsm(cs, ARCOFI_RX_END, NULL); icc_bh()
107 if (test_and_clear_bit(D_TX_MON1, &cs->event)) icc_bh()
108 arcofi_fsm(cs, ARCOFI_TX_END, NULL); icc_bh()
113 icc_empty_fifo(struct IsdnCardState *cs, int count) icc_empty_fifo() argument
117 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) icc_empty_fifo()
118 debugl1(cs, "icc_empty_fifo"); icc_empty_fifo()
120 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { icc_empty_fifo()
121 if (cs->debug & L1_DEB_WARN) icc_empty_fifo()
122 debugl1(cs, "icc_empty_fifo overrun %d", icc_empty_fifo()
123 cs->rcvidx + count); icc_empty_fifo()
124 cs->writeisac(cs, ICC_CMDR, 0x80); icc_empty_fifo()
125 cs->rcvidx = 0; icc_empty_fifo()
128 ptr = cs->rcvbuf + cs->rcvidx; icc_empty_fifo()
129 cs->rcvidx += count; icc_empty_fifo()
130 cs->readisacfifo(cs, ptr, count); icc_empty_fifo()
131 cs->writeisac(cs, ICC_CMDR, 0x80); icc_empty_fifo()
132 if (cs->debug & L1_DEB_ISAC_FIFO) { icc_empty_fifo()
133 char *t = cs->dlog; icc_empty_fifo()
137 debugl1(cs, "%s", cs->dlog); icc_empty_fifo()
142 icc_fill_fifo(struct IsdnCardState *cs) icc_fill_fifo() argument
147 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) icc_fill_fifo()
148 debugl1(cs, "icc_fill_fifo"); icc_fill_fifo()
150 if (!cs->tx_skb) icc_fill_fifo()
153 count = cs->tx_skb->len; icc_fill_fifo()
162 ptr = cs->tx_skb->data; icc_fill_fifo()
163 skb_pull(cs->tx_skb, count); icc_fill_fifo()
164 cs->tx_cnt += count; icc_fill_fifo()
165 cs->writeisacfifo(cs, ptr, count); icc_fill_fifo()
166 cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa); icc_fill_fifo()
167 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { icc_fill_fifo()
168 debugl1(cs, "icc_fill_fifo dbusytimer running"); icc_fill_fifo()
169 del_timer(&cs->dbusytimer); icc_fill_fifo()
171 init_timer(&cs->dbusytimer); icc_fill_fifo()
172 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); icc_fill_fifo()
173 add_timer(&cs->dbusytimer); icc_fill_fifo()
174 if (cs->debug & L1_DEB_ISAC_FIFO) { icc_fill_fifo()
175 char *t = cs->dlog; icc_fill_fifo()
179 debugl1(cs, "%s", cs->dlog); icc_fill_fifo()
184 icc_interrupt(struct IsdnCardState *cs, u_char val) icc_interrupt() argument
190 if (cs->debug & L1_DEB_ISAC) icc_interrupt()
191 debugl1(cs, "ICC interrupt %x", val); icc_interrupt()
193 exval = cs->readisac(cs, ICC_RSTA); icc_interrupt()
196 if (cs->debug & L1_DEB_WARN) icc_interrupt()
197 debugl1(cs, "ICC RDO"); icc_interrupt()
199 cs->err_rx++; icc_interrupt()
203 if (cs->debug & L1_DEB_WARN) icc_interrupt()
204 debugl1(cs, "ICC CRC error"); icc_interrupt()
206 cs->err_crc++; icc_interrupt()
209 cs->writeisac(cs, ICC_CMDR, 0x80); icc_interrupt()
211 count = cs->readisac(cs, ICC_RBCL) & 0x1f; icc_interrupt()
214 icc_empty_fifo(cs, count); icc_interrupt()
215 if ((count = cs->rcvidx) > 0) { icc_interrupt()
216 cs->rcvidx = 0; icc_interrupt()
220 memcpy(skb_put(skb, count), cs->rcvbuf, count); icc_interrupt()
221 skb_queue_tail(&cs->rq, skb); icc_interrupt()
225 cs->rcvidx = 0; icc_interrupt()
226 schedule_event(cs, D_RCVBUFREADY); icc_interrupt()
229 icc_empty_fifo(cs, 32); icc_interrupt()
233 if (cs->debug & L1_DEB_WARN) icc_interrupt()
234 debugl1(cs, "ICC RSC interrupt"); icc_interrupt()
237 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) icc_interrupt()
238 del_timer(&cs->dbusytimer); icc_interrupt()
239 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) icc_interrupt()
240 schedule_event(cs, D_CLEARBUSY); icc_interrupt()
241 if (cs->tx_skb) { icc_interrupt()
242 if (cs->tx_skb->len) { icc_interrupt()
243 icc_fill_fifo(cs); icc_interrupt()
246 dev_kfree_skb_irq(cs->tx_skb); icc_interrupt()
247 cs->tx_cnt = 0; icc_interrupt()
248 cs->tx_skb = NULL; icc_interrupt()
251 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { icc_interrupt()
252 cs->tx_cnt = 0; icc_interrupt()
253 icc_fill_fifo(cs); icc_interrupt()
255 schedule_event(cs, D_XMTBUFREADY); icc_interrupt()
259 exval = cs->readisac(cs, ICC_CIR0); icc_interrupt()
260 if (cs->debug & L1_DEB_ISAC) icc_interrupt()
261 debugl1(cs, "ICC CIR0 %02X", exval); icc_interrupt()
263 cs->dc.icc.ph_state = (exval >> 2) & 0xf; icc_interrupt()
264 if (cs->debug & L1_DEB_ISAC) icc_interrupt()
265 debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state); icc_interrupt()
266 schedule_event(cs, D_L1STATECHANGE); icc_interrupt()
269 exval = cs->readisac(cs, ICC_CIR1); icc_interrupt()
270 if (cs->debug & L1_DEB_ISAC) icc_interrupt()
271 debugl1(cs, "ICC CIR1 %02X", exval); icc_interrupt()
276 if (cs->debug & L1_DEB_WARN) icc_interrupt()
277 debugl1(cs, "ICC SIN interrupt"); icc_interrupt()
280 exval = cs->readisac(cs, ICC_EXIR); icc_interrupt()
281 if (cs->debug & L1_DEB_WARN) icc_interrupt()
282 debugl1(cs, "ICC EXIR %02x", exval); icc_interrupt()
284 debugl1(cs, "ICC XMR"); icc_interrupt()
288 debugl1(cs, "ICC XDU"); icc_interrupt()
291 cs->err_tx++; icc_interrupt()
293 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) icc_interrupt()
294 del_timer(&cs->dbusytimer); icc_interrupt()
295 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) icc_interrupt()
296 schedule_event(cs, D_CLEARBUSY); icc_interrupt()
297 if (cs->tx_skb) { /* Restart frame */ icc_interrupt()
298 skb_push(cs->tx_skb, cs->tx_cnt); icc_interrupt()
299 cs->tx_cnt = 0; icc_interrupt()
300 icc_fill_fifo(cs); icc_interrupt()
303 debugl1(cs, "ICC XDU no skb"); icc_interrupt()
307 v1 = cs->readisac(cs, ICC_MOSR); icc_interrupt()
308 if (cs->debug & L1_DEB_MONITOR) icc_interrupt()
309 debugl1(cs, "ICC MOSR %02x", v1); icc_interrupt()
312 if (!cs->dc.icc.mon_rx) { icc_interrupt()
313 if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { icc_interrupt()
314 if (cs->debug & L1_DEB_WARN) icc_interrupt()
315 debugl1(cs, "ICC MON RX out of memory!"); icc_interrupt()
316 cs->dc.icc.mocr &= 0xf0; icc_interrupt()
317 cs->dc.icc.mocr |= 0x0a; icc_interrupt()
318 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
321 cs->dc.icc.mon_rxp = 0; icc_interrupt()
323 if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) { icc_interrupt()
324 cs->dc.icc.mocr &= 0xf0; icc_interrupt()
325 cs->dc.icc.mocr |= 0x0a; icc_interrupt()
326 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
327 cs->dc.icc.mon_rxp = 0; icc_interrupt()
328 if (cs->debug & L1_DEB_WARN) icc_interrupt()
329 debugl1(cs, "ICC MON RX overflow!"); icc_interrupt()
332 cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0); icc_interrupt()
333 if (cs->debug & L1_DEB_MONITOR) icc_interrupt()
334 debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]); icc_interrupt()
335 if (cs->dc.icc.mon_rxp == 1) { icc_interrupt()
336 cs->dc.icc.mocr |= 0x04; icc_interrupt()
337 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
342 if (!cs->dc.icc.mon_rx) { icc_interrupt()
343 if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { icc_interrupt()
344 if (cs->debug & L1_DEB_WARN) icc_interrupt()
345 debugl1(cs, "ICC MON RX out of memory!"); icc_interrupt()
346 cs->dc.icc.mocr &= 0x0f; icc_interrupt()
347 cs->dc.icc.mocr |= 0xa0; icc_interrupt()
348 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
351 cs->dc.icc.mon_rxp = 0; icc_interrupt()
353 if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) { icc_interrupt()
354 cs->dc.icc.mocr &= 0x0f; icc_interrupt()
355 cs->dc.icc.mocr |= 0xa0; icc_interrupt()
356 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
357 cs->dc.icc.mon_rxp = 0; icc_interrupt()
358 if (cs->debug & L1_DEB_WARN) icc_interrupt()
359 debugl1(cs, "ICC MON RX overflow!"); icc_interrupt()
362 cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1); icc_interrupt()
363 if (cs->debug & L1_DEB_MONITOR) icc_interrupt()
364 debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]); icc_interrupt()
365 cs->dc.icc.mocr |= 0x40; icc_interrupt()
366 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
370 cs->dc.icc.mocr &= 0xf0; icc_interrupt()
371 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
372 cs->dc.icc.mocr |= 0x0a; icc_interrupt()
373 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
374 schedule_event(cs, D_RX_MON0); icc_interrupt()
377 cs->dc.icc.mocr &= 0x0f; icc_interrupt()
378 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
379 cs->dc.icc.mocr |= 0xa0; icc_interrupt()
380 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
381 schedule_event(cs, D_RX_MON1); icc_interrupt()
384 if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && icc_interrupt()
385 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && icc_interrupt()
387 cs->dc.icc.mocr &= 0xf0; icc_interrupt()
388 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
389 cs->dc.icc.mocr |= 0x0a; icc_interrupt()
390 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
391 if (cs->dc.icc.mon_txc && icc_interrupt()
392 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) icc_interrupt()
393 schedule_event(cs, D_TX_MON0); icc_interrupt()
396 if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) { icc_interrupt()
397 schedule_event(cs, D_TX_MON0); icc_interrupt()
400 cs->writeisac(cs, ICC_MOX0, icc_interrupt()
401 cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]); icc_interrupt()
402 if (cs->debug & L1_DEB_MONITOR) icc_interrupt()
403 debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]); icc_interrupt()
407 if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && icc_interrupt()
408 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && icc_interrupt()
410 cs->dc.icc.mocr &= 0x0f; icc_interrupt()
411 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
412 cs->dc.icc.mocr |= 0xa0; icc_interrupt()
413 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); icc_interrupt()
414 if (cs->dc.icc.mon_txc && icc_interrupt()
415 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) icc_interrupt()
416 schedule_event(cs, D_TX_MON1); icc_interrupt()
419 if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) { icc_interrupt()
420 schedule_event(cs, D_TX_MON1); icc_interrupt()
423 cs->writeisac(cs, ICC_MOX1, icc_interrupt()
424 cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]); icc_interrupt()
425 if (cs->debug & L1_DEB_MONITOR) icc_interrupt()
426 debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]); icc_interrupt()
437 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; ICC_l1hw() local
444 if (cs->debug & DEB_DLOG_HEX) ICC_l1hw()
445 LogFrame(cs, skb->data, skb->len); ICC_l1hw()
446 if (cs->debug & DEB_DLOG_VERBOSE) ICC_l1hw()
447 dlogframe(cs, skb, 0); ICC_l1hw()
448 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
449 if (cs->tx_skb) { ICC_l1hw()
450 skb_queue_tail(&cs->sq, skb); ICC_l1hw()
452 if (cs->debug & L1_DEB_LAPD) ICC_l1hw()
453 Logl2Frame(cs, skb, "PH_DATA Queued", 0); ICC_l1hw()
456 cs->tx_skb = skb; ICC_l1hw()
457 cs->tx_cnt = 0; ICC_l1hw()
459 if (cs->debug & L1_DEB_LAPD) ICC_l1hw()
460 Logl2Frame(cs, skb, "PH_DATA", 0); ICC_l1hw()
462 icc_fill_fifo(cs); ICC_l1hw()
464 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
467 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
468 if (cs->tx_skb) { ICC_l1hw()
469 if (cs->debug & L1_DEB_WARN) ICC_l1hw()
470 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); ICC_l1hw()
471 skb_queue_tail(&cs->sq, skb); ICC_l1hw()
472 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
475 if (cs->debug & DEB_DLOG_HEX) ICC_l1hw()
476 LogFrame(cs, skb->data, skb->len); ICC_l1hw()
477 if (cs->debug & DEB_DLOG_VERBOSE) ICC_l1hw()
478 dlogframe(cs, skb, 0); ICC_l1hw()
479 cs->tx_skb = skb; ICC_l1hw()
480 cs->tx_cnt = 0; ICC_l1hw()
482 if (cs->debug & L1_DEB_LAPD) ICC_l1hw()
483 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); ICC_l1hw()
485 icc_fill_fifo(cs); ICC_l1hw()
486 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
490 if (cs->debug & L1_DEB_LAPD) ICC_l1hw()
491 debugl1(cs, "-> PH_REQUEST_PULL"); ICC_l1hw()
493 if (!cs->tx_skb) { ICC_l1hw()
500 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
501 if ((cs->dc.icc.ph_state == ICC_IND_EI1) || ICC_l1hw()
502 (cs->dc.icc.ph_state == ICC_IND_DR)) ICC_l1hw()
503 ph_command(cs, ICC_CMD_DI); ICC_l1hw()
505 ph_command(cs, ICC_CMD_RES); ICC_l1hw()
506 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
509 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
510 ph_command(cs, ICC_CMD_DI); ICC_l1hw()
511 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
514 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
515 ph_command(cs, ICC_CMD_AR); ICC_l1hw()
516 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
519 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
520 ph_command(cs, ICC_CMD_AI); ICC_l1hw()
521 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
524 spin_lock_irqsave(&cs->lock, flags); ICC_l1hw()
530 if (test_bit(HW_IOM1, &cs->HW_Flags)) { ICC_l1hw()
533 cs->writeisac(cs, ICC_SPCR, 0xa); ICC_l1hw()
534 cs->writeisac(cs, ICC_ADF1, 0x2); ICC_l1hw()
536 cs->writeisac(cs, ICC_SPCR, val); ICC_l1hw()
537 cs->writeisac(cs, ICC_ADF1, 0xa); ICC_l1hw()
541 cs->writeisac(cs, ICC_SPCR, val); ICC_l1hw()
543 cs->writeisac(cs, ICC_ADF1, 0x8); ICC_l1hw()
545 cs->writeisac(cs, ICC_ADF1, 0x0); ICC_l1hw()
547 spin_unlock_irqrestore(&cs->lock, flags); ICC_l1hw()
550 skb_queue_purge(&cs->rq); ICC_l1hw()
551 skb_queue_purge(&cs->sq); ICC_l1hw()
552 if (cs->tx_skb) { ICC_l1hw()
553 dev_kfree_skb_any(cs->tx_skb); ICC_l1hw()
554 cs->tx_skb = NULL; ICC_l1hw()
556 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) ICC_l1hw()
557 del_timer(&cs->dbusytimer); ICC_l1hw()
558 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) ICC_l1hw()
559 schedule_event(cs, D_CLEARBUSY); ICC_l1hw()
562 if (cs->debug & L1_DEB_WARN) ICC_l1hw()
563 debugl1(cs, "icc_l1hw unknown %04x", pr); ICC_l1hw()
569 setstack_icc(struct PStack *st, struct IsdnCardState *cs) setstack_icc() argument
575 DC_Close_icc(struct IsdnCardState *cs) { DC_Close_icc() argument
576 kfree(cs->dc.icc.mon_rx); DC_Close_icc()
577 cs->dc.icc.mon_rx = NULL; DC_Close_icc()
578 kfree(cs->dc.icc.mon_tx); DC_Close_icc()
579 cs->dc.icc.mon_tx = NULL; DC_Close_icc()
583 dbusy_timer_handler(struct IsdnCardState *cs) dbusy_timer_handler() argument
588 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dbusy_timer_handler()
589 rbch = cs->readisac(cs, ICC_RBCH); dbusy_timer_handler()
590 star = cs->readisac(cs, ICC_STAR); dbusy_timer_handler()
591 if (cs->debug) dbusy_timer_handler()
592 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x", dbusy_timer_handler()
595 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags); dbusy_timer_handler()
596 stptr = cs->stlist; dbusy_timer_handler()
603 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); dbusy_timer_handler()
604 if (cs->tx_skb) { dbusy_timer_handler()
605 dev_kfree_skb_any(cs->tx_skb); dbusy_timer_handler()
606 cs->tx_cnt = 0; dbusy_timer_handler()
607 cs->tx_skb = NULL; dbusy_timer_handler()
610 debugl1(cs, "D-Channel Busy no skb"); dbusy_timer_handler()
612 cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */ dbusy_timer_handler()
613 cs->irq_func(cs->irq, cs); dbusy_timer_handler()
619 initicc(struct IsdnCardState *cs) initicc() argument
621 cs->setstack_d = setstack_icc; initicc()
622 cs->DC_Close = DC_Close_icc; initicc()
623 cs->dc.icc.mon_tx = NULL; initicc()
624 cs->dc.icc.mon_rx = NULL; initicc()
625 cs->writeisac(cs, ICC_MASK, 0xff); initicc()
626 cs->dc.icc.mocr = 0xaa; initicc()
627 if (test_bit(HW_IOM1, &cs->HW_Flags)) { initicc()
629 cs->writeisac(cs, ICC_ADF2, 0x0); initicc()
630 cs->writeisac(cs, ICC_SPCR, 0xa); initicc()
631 cs->writeisac(cs, ICC_ADF1, 0x2); initicc()
632 cs->writeisac(cs, ICC_STCR, 0x70); initicc()
633 cs->writeisac(cs, ICC_MODE, 0xc9); initicc()
636 if (!cs->dc.icc.adf2) initicc()
637 cs->dc.icc.adf2 = 0x80; initicc()
638 cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2); initicc()
639 cs->writeisac(cs, ICC_SQXR, 0xa0); initicc()
640 cs->writeisac(cs, ICC_SPCR, 0x20); initicc()
641 cs->writeisac(cs, ICC_STCR, 0x70); initicc()
642 cs->writeisac(cs, ICC_MODE, 0xca); initicc()
643 cs->writeisac(cs, ICC_TIMR, 0x00); initicc()
644 cs->writeisac(cs, ICC_ADF1, 0x20); initicc()
646 ph_command(cs, ICC_CMD_RES); initicc()
647 cs->writeisac(cs, ICC_MASK, 0x0); initicc()
648 ph_command(cs, ICC_CMD_DI); initicc()
652 clear_pending_icc_ints(struct IsdnCardState *cs) clear_pending_icc_ints() argument
656 val = cs->readisac(cs, ICC_STAR); clear_pending_icc_ints()
657 debugl1(cs, "ICC STAR %x", val); clear_pending_icc_ints()
658 val = cs->readisac(cs, ICC_MODE); clear_pending_icc_ints()
659 debugl1(cs, "ICC MODE %x", val); clear_pending_icc_ints()
660 val = cs->readisac(cs, ICC_ADF2); clear_pending_icc_ints()
661 debugl1(cs, "ICC ADF2 %x", val); clear_pending_icc_ints()
662 val = cs->readisac(cs, ICC_ISTA); clear_pending_icc_ints()
663 debugl1(cs, "ICC ISTA %x", val); clear_pending_icc_ints()
665 eval = cs->readisac(cs, ICC_EXIR); clear_pending_icc_ints()
666 debugl1(cs, "ICC EXIR %x", eval); clear_pending_icc_ints()
668 val = cs->readisac(cs, ICC_CIR0); clear_pending_icc_ints()
669 debugl1(cs, "ICC CIR0 %x", val); clear_pending_icc_ints()
670 cs->dc.icc.ph_state = (val >> 2) & 0xf; clear_pending_icc_ints()
671 schedule_event(cs, D_L1STATECHANGE); clear_pending_icc_ints()
673 cs->writeisac(cs, ICC_MASK, 0xFF); clear_pending_icc_ints()
676 void setup_icc(struct IsdnCardState *cs) setup_icc() argument
678 INIT_WORK(&cs->tqueue, icc_bh); setup_icc()
679 cs->dbusytimer.function = (void *) dbusy_timer_handler; setup_icc()
680 cs->dbusytimer.data = (long) cs; setup_icc()
681 init_timer(&cs->dbusytimer); setup_icc()
|
| H A D | isac.c | 31 void ISACVersion(struct IsdnCardState *cs, char *s) ISACVersion() argument
35 val = cs->readisac(cs, ISAC_RBCH); ISACVersion()
40 ph_command(struct IsdnCardState *cs, unsigned int command) ph_command() argument
42 if (cs->debug & L1_DEB_ISAC) ph_command()
43 debugl1(cs, "ph_command %x", command); ph_command()
44 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3); ph_command()
49 isac_new_ph(struct IsdnCardState *cs) isac_new_ph() argument
51 switch (cs->dc.isac.ph_state) { isac_new_ph()
54 ph_command(cs, ISAC_CMD_DUI); isac_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); isac_new_ph()
58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); isac_new_ph()
61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); isac_new_ph()
64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); isac_new_ph()
67 l1_msg(cs, HW_RSYNC | INDICATION, NULL); isac_new_ph()
70 l1_msg(cs, HW_INFO2 | INDICATION, NULL); isac_new_ph()
73 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); isac_new_ph()
76 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL); isac_new_ph()
86 struct IsdnCardState *cs = isac_bh() local
90 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { isac_bh()
91 if (cs->debug) isac_bh()
92 debugl1(cs, "D-Channel Busy cleared"); isac_bh()
93 stptr = cs->stlist; isac_bh()
99 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) isac_bh()
100 isac_new_ph(cs); isac_bh()
101 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) isac_bh()
102 DChannel_proc_rcv(cs); isac_bh()
103 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) isac_bh()
104 DChannel_proc_xmt(cs); isac_bh()
106 if (!test_bit(HW_ARCOFI, &cs->HW_Flags)) isac_bh()
108 if (test_and_clear_bit(D_RX_MON1, &cs->event)) isac_bh()
109 arcofi_fsm(cs, ARCOFI_RX_END, NULL); isac_bh()
110 if (test_and_clear_bit(D_TX_MON1, &cs->event)) isac_bh()
111 arcofi_fsm(cs, ARCOFI_TX_END, NULL); isac_bh()
116 isac_empty_fifo(struct IsdnCardState *cs, int count) isac_empty_fifo() argument
120 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) isac_empty_fifo()
121 debugl1(cs, "isac_empty_fifo"); isac_empty_fifo()
123 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { isac_empty_fifo()
124 if (cs->debug & L1_DEB_WARN) isac_empty_fifo()
125 debugl1(cs, "isac_empty_fifo overrun %d", isac_empty_fifo()
126 cs->rcvidx + count); isac_empty_fifo()
127 cs->writeisac(cs, ISAC_CMDR, 0x80); isac_empty_fifo()
128 cs->rcvidx = 0; isac_empty_fifo()
131 ptr = cs->rcvbuf + cs->rcvidx; isac_empty_fifo()
132 cs->rcvidx += count; isac_empty_fifo()
133 cs->readisacfifo(cs, ptr, count); isac_empty_fifo()
134 cs->writeisac(cs, ISAC_CMDR, 0x80); isac_empty_fifo()
135 if (cs->debug & L1_DEB_ISAC_FIFO) { isac_empty_fifo()
136 char *t = cs->dlog; isac_empty_fifo()
140 debugl1(cs, "%s", cs->dlog); isac_empty_fifo()
145 isac_fill_fifo(struct IsdnCardState *cs) isac_fill_fifo() argument
150 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) isac_fill_fifo()
151 debugl1(cs, "isac_fill_fifo"); isac_fill_fifo()
153 if (!cs->tx_skb) isac_fill_fifo()
156 count = cs->tx_skb->len; isac_fill_fifo()
165 ptr = cs->tx_skb->data; isac_fill_fifo()
166 skb_pull(cs->tx_skb, count); isac_fill_fifo()
167 cs->tx_cnt += count; isac_fill_fifo()
168 cs->writeisacfifo(cs, ptr, count); isac_fill_fifo()
169 cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa); isac_fill_fifo()
170 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { isac_fill_fifo()
171 debugl1(cs, "isac_fill_fifo dbusytimer running"); isac_fill_fifo()
172 del_timer(&cs->dbusytimer); isac_fill_fifo()
174 init_timer(&cs->dbusytimer); isac_fill_fifo()
175 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); isac_fill_fifo()
176 add_timer(&cs->dbusytimer); isac_fill_fifo()
177 if (cs->debug & L1_DEB_ISAC_FIFO) { isac_fill_fifo()
178 char *t = cs->dlog; isac_fill_fifo()
182 debugl1(cs, "%s", cs->dlog); isac_fill_fifo()
187 isac_interrupt(struct IsdnCardState *cs, u_char val) isac_interrupt() argument
193 if (cs->debug & L1_DEB_ISAC) isac_interrupt()
194 debugl1(cs, "ISAC interrupt %x", val); isac_interrupt()
196 exval = cs->readisac(cs, ISAC_RSTA); isac_interrupt()
199 if (cs->debug & L1_DEB_WARN) isac_interrupt()
200 debugl1(cs, "ISAC RDO"); isac_interrupt()
202 cs->err_rx++; isac_interrupt()
206 if (cs->debug & L1_DEB_WARN) isac_interrupt()
207 debugl1(cs, "ISAC CRC error"); isac_interrupt()
209 cs->err_crc++; isac_interrupt()
212 cs->writeisac(cs, ISAC_CMDR, 0x80); isac_interrupt()
214 count = cs->readisac(cs, ISAC_RBCL) & 0x1f; isac_interrupt()
217 isac_empty_fifo(cs, count); isac_interrupt()
218 if ((count = cs->rcvidx) > 0) { isac_interrupt()
219 cs->rcvidx = 0; isac_interrupt()
223 memcpy(skb_put(skb, count), cs->rcvbuf, count); isac_interrupt()
224 skb_queue_tail(&cs->rq, skb); isac_interrupt()
228 cs->rcvidx = 0; isac_interrupt()
229 schedule_event(cs, D_RCVBUFREADY); isac_interrupt()
232 isac_empty_fifo(cs, 32); isac_interrupt()
236 if (cs->debug & L1_DEB_WARN) isac_interrupt()
237 debugl1(cs, "ISAC RSC interrupt"); isac_interrupt()
240 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) isac_interrupt()
241 del_timer(&cs->dbusytimer); isac_interrupt()
242 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) isac_interrupt()
243 schedule_event(cs, D_CLEARBUSY); isac_interrupt()
244 if (cs->tx_skb) { isac_interrupt()
245 if (cs->tx_skb->len) { isac_interrupt()
246 isac_fill_fifo(cs); isac_interrupt()
249 dev_kfree_skb_irq(cs->tx_skb); isac_interrupt()
250 cs->tx_cnt = 0; isac_interrupt()
251 cs->tx_skb = NULL; isac_interrupt()
254 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { isac_interrupt()
255 cs->tx_cnt = 0; isac_interrupt()
256 isac_fill_fifo(cs); isac_interrupt()
258 schedule_event(cs, D_XMTBUFREADY); isac_interrupt()
262 exval = cs->readisac(cs, ISAC_CIR0); isac_interrupt()
263 if (cs->debug & L1_DEB_ISAC) isac_interrupt()
264 debugl1(cs, "ISAC CIR0 %02X", exval); isac_interrupt()
266 cs->dc.isac.ph_state = (exval >> 2) & 0xf; isac_interrupt()
267 if (cs->debug & L1_DEB_ISAC) isac_interrupt()
268 debugl1(cs, "ph_state change %x", cs->dc.isac.ph_state); isac_interrupt()
269 schedule_event(cs, D_L1STATECHANGE); isac_interrupt()
272 exval = cs->readisac(cs, ISAC_CIR1); isac_interrupt()
273 if (cs->debug & L1_DEB_ISAC) isac_interrupt()
274 debugl1(cs, "ISAC CIR1 %02X", exval); isac_interrupt()
279 if (cs->debug & L1_DEB_WARN) isac_interrupt()
280 debugl1(cs, "ISAC SIN interrupt"); isac_interrupt()
283 exval = cs->readisac(cs, ISAC_EXIR); isac_interrupt()
284 if (cs->debug & L1_DEB_WARN) isac_interrupt()
285 debugl1(cs, "ISAC EXIR %02x", exval); isac_interrupt()
287 debugl1(cs, "ISAC XMR"); isac_interrupt()
291 debugl1(cs, "ISAC XDU"); isac_interrupt()
294 cs->err_tx++; isac_interrupt()
296 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) isac_interrupt()
297 del_timer(&cs->dbusytimer); isac_interrupt()
298 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) isac_interrupt()
299 schedule_event(cs, D_CLEARBUSY); isac_interrupt()
300 if (cs->tx_skb) { /* Restart frame */ isac_interrupt()
301 skb_push(cs->tx_skb, cs->tx_cnt); isac_interrupt()
302 cs->tx_cnt = 0; isac_interrupt()
303 isac_fill_fifo(cs); isac_interrupt()
306 debugl1(cs, "ISAC XDU no skb"); isac_interrupt()
310 v1 = cs->readisac(cs, ISAC_MOSR); isac_interrupt()
311 if (cs->debug & L1_DEB_MONITOR) isac_interrupt()
312 debugl1(cs, "ISAC MOSR %02x", v1); isac_interrupt()
315 if (!cs->dc.isac.mon_rx) { isac_interrupt()
316 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { isac_interrupt()
317 if (cs->debug & L1_DEB_WARN) isac_interrupt()
318 debugl1(cs, "ISAC MON RX out of memory!"); isac_interrupt()
319 cs->dc.isac.mocr &= 0xf0; isac_interrupt()
320 cs->dc.isac.mocr |= 0x0a; isac_interrupt()
321 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
324 cs->dc.isac.mon_rxp = 0; isac_interrupt()
326 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) { isac_interrupt()
327 cs->dc.isac.mocr &= 0xf0; isac_interrupt()
328 cs->dc.isac.mocr |= 0x0a; isac_interrupt()
329 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
330 cs->dc.isac.mon_rxp = 0; isac_interrupt()
331 if (cs->debug & L1_DEB_WARN) isac_interrupt()
332 debugl1(cs, "ISAC MON RX overflow!"); isac_interrupt()
335 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0); isac_interrupt()
336 if (cs->debug & L1_DEB_MONITOR) isac_interrupt()
337 debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]); isac_interrupt()
338 if (cs->dc.isac.mon_rxp == 1) { isac_interrupt()
339 cs->dc.isac.mocr |= 0x04; isac_interrupt()
340 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
345 if (!cs->dc.isac.mon_rx) { isac_interrupt()
346 if (!(cs->dc.isac.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { isac_interrupt()
347 if (cs->debug & L1_DEB_WARN) isac_interrupt()
348 debugl1(cs, "ISAC MON RX out of memory!"); isac_interrupt()
349 cs->dc.isac.mocr &= 0x0f; isac_interrupt()
350 cs->dc.isac.mocr |= 0xa0; isac_interrupt()
351 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
354 cs->dc.isac.mon_rxp = 0; isac_interrupt()
356 if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) { isac_interrupt()
357 cs->dc.isac.mocr &= 0x0f; isac_interrupt()
358 cs->dc.isac.mocr |= 0xa0; isac_interrupt()
359 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
360 cs->dc.isac.mon_rxp = 0; isac_interrupt()
361 if (cs->debug & L1_DEB_WARN) isac_interrupt()
362 debugl1(cs, "ISAC MON RX overflow!"); isac_interrupt()
365 cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1); isac_interrupt()
366 if (cs->debug & L1_DEB_MONITOR) isac_interrupt()
367 debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp - 1]); isac_interrupt()
368 cs->dc.isac.mocr |= 0x40; isac_interrupt()
369 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
373 cs->dc.isac.mocr &= 0xf0; isac_interrupt()
374 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
375 cs->dc.isac.mocr |= 0x0a; isac_interrupt()
376 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
377 schedule_event(cs, D_RX_MON0); isac_interrupt()
380 cs->dc.isac.mocr &= 0x0f; isac_interrupt()
381 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
382 cs->dc.isac.mocr |= 0xa0; isac_interrupt()
383 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
384 schedule_event(cs, D_RX_MON1); isac_interrupt()
387 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc && isac_interrupt()
388 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) && isac_interrupt()
390 cs->dc.isac.mocr &= 0xf0; isac_interrupt()
391 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
392 cs->dc.isac.mocr |= 0x0a; isac_interrupt()
393 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
394 if (cs->dc.isac.mon_txc && isac_interrupt()
395 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) isac_interrupt()
396 schedule_event(cs, D_TX_MON0); isac_interrupt()
399 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) { isac_interrupt()
400 schedule_event(cs, D_TX_MON0); isac_interrupt()
403 cs->writeisac(cs, ISAC_MOX0, isac_interrupt()
404 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]); isac_interrupt()
405 if (cs->debug & L1_DEB_MONITOR) isac_interrupt()
406 debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]); isac_interrupt()
410 if ((!cs->dc.isac.mon_tx) || (cs->dc.isac.mon_txc && isac_interrupt()
411 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) && isac_interrupt()
413 cs->dc.isac.mocr &= 0x0f; isac_interrupt()
414 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
415 cs->dc.isac.mocr |= 0xa0; isac_interrupt()
416 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); isac_interrupt()
417 if (cs->dc.isac.mon_txc && isac_interrupt()
418 (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) isac_interrupt()
419 schedule_event(cs, D_TX_MON1); isac_interrupt()
422 if (cs->dc.isac.mon_txc && (cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc)) { isac_interrupt()
423 schedule_event(cs, D_TX_MON1); isac_interrupt()
426 cs->writeisac(cs, ISAC_MOX1, isac_interrupt()
427 cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]); isac_interrupt()
428 if (cs->debug & L1_DEB_MONITOR) isac_interrupt()
429 debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp - 1]); isac_interrupt()
440 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; ISAC_l1hw() local
447 if (cs->debug & DEB_DLOG_HEX) ISAC_l1hw()
448 LogFrame(cs, skb->data, skb->len); ISAC_l1hw()
449 if (cs->debug & DEB_DLOG_VERBOSE) ISAC_l1hw()
450 dlogframe(cs, skb, 0); ISAC_l1hw()
451 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
452 if (cs->tx_skb) { ISAC_l1hw()
453 skb_queue_tail(&cs->sq, skb); ISAC_l1hw()
455 if (cs->debug & L1_DEB_LAPD) ISAC_l1hw()
456 Logl2Frame(cs, skb, "PH_DATA Queued", 0); ISAC_l1hw()
459 cs->tx_skb = skb; ISAC_l1hw()
460 cs->tx_cnt = 0; ISAC_l1hw()
462 if (cs->debug & L1_DEB_LAPD) ISAC_l1hw()
463 Logl2Frame(cs, skb, "PH_DATA", 0); ISAC_l1hw()
465 isac_fill_fifo(cs); ISAC_l1hw()
467 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
470 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
471 if (cs->tx_skb) { ISAC_l1hw()
472 if (cs->debug & L1_DEB_WARN) ISAC_l1hw()
473 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); ISAC_l1hw()
474 skb_queue_tail(&cs->sq, skb); ISAC_l1hw()
476 if (cs->debug & DEB_DLOG_HEX) ISAC_l1hw()
477 LogFrame(cs, skb->data, skb->len); ISAC_l1hw()
478 if (cs->debug & DEB_DLOG_VERBOSE) ISAC_l1hw()
479 dlogframe(cs, skb, 0); ISAC_l1hw()
480 cs->tx_skb = skb; ISAC_l1hw()
481 cs->tx_cnt = 0; ISAC_l1hw()
483 if (cs->debug & L1_DEB_LAPD) ISAC_l1hw()
484 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); ISAC_l1hw()
486 isac_fill_fifo(cs); ISAC_l1hw()
488 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
492 if (cs->debug & L1_DEB_LAPD) ISAC_l1hw()
493 debugl1(cs, "-> PH_REQUEST_PULL"); ISAC_l1hw()
495 if (!cs->tx_skb) { ISAC_l1hw()
502 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
503 if ((cs->dc.isac.ph_state == ISAC_IND_EI) || ISAC_l1hw()
504 (cs->dc.isac.ph_state == ISAC_IND_DR) || ISAC_l1hw()
505 (cs->dc.isac.ph_state == ISAC_IND_RS)) ISAC_l1hw()
506 ph_command(cs, ISAC_CMD_TIM); ISAC_l1hw()
508 ph_command(cs, ISAC_CMD_RS); ISAC_l1hw()
509 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
512 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
513 ph_command(cs, ISAC_CMD_TIM); ISAC_l1hw()
514 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
517 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
518 ph_command(cs, ISAC_CMD_AR8); ISAC_l1hw()
519 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
522 spin_lock_irqsave(&cs->lock, flags); ISAC_l1hw()
528 if (test_bit(HW_IOM1, &cs->HW_Flags)) { ISAC_l1hw()
531 cs->writeisac(cs, ISAC_SPCR, 0xa); ISAC_l1hw()
532 cs->writeisac(cs, ISAC_ADF1, 0x2); ISAC_l1hw()
534 cs->writeisac(cs, ISAC_SPCR, val); ISAC_l1hw()
535 cs->writeisac(cs, ISAC_ADF1, 0xa); ISAC_l1hw()
539 cs->writeisac(cs, ISAC_SPCR, val); ISAC_l1hw()
541 cs->writeisac(cs, ISAC_ADF1, 0x8); ISAC_l1hw()
543 cs->writeisac(cs, ISAC_ADF1, 0x0); ISAC_l1hw()
545 spin_unlock_irqrestore(&cs->lock, flags); ISAC_l1hw()
548 skb_queue_purge(&cs->rq); ISAC_l1hw()
549 skb_queue_purge(&cs->sq); ISAC_l1hw()
550 if (cs->tx_skb) { ISAC_l1hw()
551 dev_kfree_skb_any(cs->tx_skb); ISAC_l1hw()
552 cs->tx_skb = NULL; ISAC_l1hw()
554 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) ISAC_l1hw()
555 del_timer(&cs->dbusytimer); ISAC_l1hw()
556 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) ISAC_l1hw()
557 schedule_event(cs, D_CLEARBUSY); ISAC_l1hw()
560 if (cs->debug & L1_DEB_WARN) ISAC_l1hw()
561 debugl1(cs, "isac_l1hw unknown %04x", pr); ISAC_l1hw()
567 setstack_isac(struct PStack *st, struct IsdnCardState *cs) setstack_isac() argument
573 DC_Close_isac(struct IsdnCardState *cs) DC_Close_isac() argument
575 kfree(cs->dc.isac.mon_rx); DC_Close_isac()
576 cs->dc.isac.mon_rx = NULL; DC_Close_isac()
577 kfree(cs->dc.isac.mon_tx); DC_Close_isac()
578 cs->dc.isac.mon_tx = NULL; DC_Close_isac()
582 dbusy_timer_handler(struct IsdnCardState *cs) dbusy_timer_handler() argument
587 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dbusy_timer_handler()
588 rbch = cs->readisac(cs, ISAC_RBCH); dbusy_timer_handler()
589 star = cs->readisac(cs, ISAC_STAR); dbusy_timer_handler()
590 if (cs->debug) dbusy_timer_handler()
591 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x", dbusy_timer_handler()
594 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags); dbusy_timer_handler()
595 stptr = cs->stlist; dbusy_timer_handler()
602 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); dbusy_timer_handler()
603 if (cs->tx_skb) { dbusy_timer_handler()
604 dev_kfree_skb_any(cs->tx_skb); dbusy_timer_handler()
605 cs->tx_cnt = 0; dbusy_timer_handler()
606 cs->tx_skb = NULL; dbusy_timer_handler()
609 debugl1(cs, "D-Channel Busy no skb"); dbusy_timer_handler()
611 cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */ dbusy_timer_handler()
612 cs->irq_func(cs->irq, cs); dbusy_timer_handler()
617 void initisac(struct IsdnCardState *cs) initisac() argument
619 cs->setstack_d = setstack_isac; initisac()
620 cs->DC_Close = DC_Close_isac; initisac()
621 cs->dc.isac.mon_tx = NULL; initisac()
622 cs->dc.isac.mon_rx = NULL; initisac()
623 cs->writeisac(cs, ISAC_MASK, 0xff); initisac()
624 cs->dc.isac.mocr = 0xaa; initisac()
625 if (test_bit(HW_IOM1, &cs->HW_Flags)) { initisac()
627 cs->writeisac(cs, ISAC_ADF2, 0x0); initisac()
628 cs->writeisac(cs, ISAC_SPCR, 0xa); initisac()
629 cs->writeisac(cs, ISAC_ADF1, 0x2); initisac()
630 cs->writeisac(cs, ISAC_STCR, 0x70); initisac()
631 cs->writeisac(cs, ISAC_MODE, 0xc9); initisac()
634 if (!cs->dc.isac.adf2) initisac()
635 cs->dc.isac.adf2 = 0x80; initisac()
636 cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2); initisac()
637 cs->writeisac(cs, ISAC_SQXR, 0x2f); initisac()
638 cs->writeisac(cs, ISAC_SPCR, 0x00); initisac()
639 cs->writeisac(cs, ISAC_STCR, 0x70); initisac()
640 cs->writeisac(cs, ISAC_MODE, 0xc9); initisac()
641 cs->writeisac(cs, ISAC_TIMR, 0x00); initisac()
642 cs->writeisac(cs, ISAC_ADF1, 0x00); initisac()
644 ph_command(cs, ISAC_CMD_RS); initisac()
645 cs->writeisac(cs, ISAC_MASK, 0x0); initisac()
648 void clear_pending_isac_ints(struct IsdnCardState *cs) clear_pending_isac_ints() argument
652 val = cs->readisac(cs, ISAC_STAR); clear_pending_isac_ints()
653 debugl1(cs, "ISAC STAR %x", val); clear_pending_isac_ints()
654 val = cs->readisac(cs, ISAC_MODE); clear_pending_isac_ints()
655 debugl1(cs, "ISAC MODE %x", val); clear_pending_isac_ints()
656 val = cs->readisac(cs, ISAC_ADF2); clear_pending_isac_ints()
657 debugl1(cs, "ISAC ADF2 %x", val); clear_pending_isac_ints()
658 val = cs->readisac(cs, ISAC_ISTA); clear_pending_isac_ints()
659 debugl1(cs, "ISAC ISTA %x", val); clear_pending_isac_ints()
661 eval = cs->readisac(cs, ISAC_EXIR); clear_pending_isac_ints()
662 debugl1(cs, "ISAC EXIR %x", eval); clear_pending_isac_ints()
664 val = cs->readisac(cs, ISAC_CIR0); clear_pending_isac_ints()
665 debugl1(cs, "ISAC CIR0 %x", val); clear_pending_isac_ints()
666 cs->dc.isac.ph_state = (val >> 2) & 0xf; clear_pending_isac_ints()
667 schedule_event(cs, D_L1STATECHANGE); clear_pending_isac_ints()
669 cs->writeisac(cs, ISAC_MASK, 0xFF); clear_pending_isac_ints()
672 void setup_isac(struct IsdnCardState *cs) setup_isac() argument
674 INIT_WORK(&cs->tqueue, isac_bh); setup_isac()
675 cs->dbusytimer.function = (void *) dbusy_timer_handler; setup_isac()
676 cs->dbusytimer.data = (long) cs; setup_isac()
677 init_timer(&cs->dbusytimer); setup_isac()
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| H A D | arcofi.c | 22 add_arcofi_timer(struct IsdnCardState *cs) { add_arcofi_timer() argument
23 if (test_and_set_bit(FLG_ARCOFI_TIMER, &cs->HW_Flags)) { add_arcofi_timer()
24 del_timer(&cs->dc.isac.arcofitimer); add_arcofi_timer()
26 init_timer(&cs->dc.isac.arcofitimer); add_arcofi_timer()
27 cs->dc.isac.arcofitimer.expires = jiffies + ((ARCOFI_TIMER_VALUE * HZ) / 1000); add_arcofi_timer()
28 add_timer(&cs->dc.isac.arcofitimer); add_arcofi_timer()
32 send_arcofi(struct IsdnCardState *cs) { send_arcofi() argument
33 add_arcofi_timer(cs); send_arcofi()
34 cs->dc.isac.mon_txp = 0; send_arcofi()
35 cs->dc.isac.mon_txc = cs->dc.isac.arcofi_list->len; send_arcofi()
36 memcpy(cs->dc.isac.mon_tx, cs->dc.isac.arcofi_list->msg, cs->dc.isac.mon_txc); send_arcofi()
37 switch (cs->dc.isac.arcofi_bc) { send_arcofi()
39 case 1: cs->dc.isac.mon_tx[1] |= 0x40; send_arcofi()
43 cs->dc.isac.mocr &= 0x0f; send_arcofi()
44 cs->dc.isac.mocr |= 0xa0; send_arcofi()
45 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); send_arcofi()
46 (void) cs->readisac(cs, ISAC_MOSR); send_arcofi()
47 cs->writeisac(cs, ISAC_MOX1, cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]); send_arcofi()
48 cs->dc.isac.mocr |= 0x10; send_arcofi()
49 cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr); send_arcofi()
53 arcofi_fsm(struct IsdnCardState *cs, int event, void *data) { arcofi_fsm() argument
54 if (cs->debug & L1_DEB_MONITOR) { arcofi_fsm()
55 debugl1(cs, "arcofi state %d event %d", cs->dc.isac.arcofi_state, event); arcofi_fsm()
58 cs->dc.isac.arcofi_state = ARCOFI_NOP; arcofi_fsm()
59 test_and_set_bit(FLG_ARCOFI_ERROR, &cs->HW_Flags); arcofi_fsm()
60 wake_up(&cs->dc.isac.arcofi_wait); arcofi_fsm()
63 switch (cs->dc.isac.arcofi_state) { arcofi_fsm()
66 cs->dc.isac.arcofi_list = data; arcofi_fsm()
67 cs->dc.isac.arcofi_state = ARCOFI_TRANSMIT; arcofi_fsm()
68 send_arcofi(cs); arcofi_fsm()
73 if (cs->dc.isac.arcofi_list->receive) { arcofi_fsm()
74 add_arcofi_timer(cs); arcofi_fsm()
75 cs->dc.isac.arcofi_state = ARCOFI_RECEIVE; arcofi_fsm()
77 if (cs->dc.isac.arcofi_list->next) { arcofi_fsm()
78 cs->dc.isac.arcofi_list = arcofi_fsm()
79 cs->dc.isac.arcofi_list->next; arcofi_fsm()
80 send_arcofi(cs); arcofi_fsm()
82 if (test_and_clear_bit(FLG_ARCOFI_TIMER, &cs->HW_Flags)) { arcofi_fsm()
83 del_timer(&cs->dc.isac.arcofitimer); arcofi_fsm()
85 cs->dc.isac.arcofi_state = ARCOFI_NOP; arcofi_fsm()
86 wake_up(&cs->dc.isac.arcofi_wait); arcofi_fsm()
93 if (cs->dc.isac.arcofi_list->next) { arcofi_fsm()
94 cs->dc.isac.arcofi_list = arcofi_fsm()
95 cs->dc.isac.arcofi_list->next; arcofi_fsm()
96 cs->dc.isac.arcofi_state = ARCOFI_TRANSMIT; arcofi_fsm()
97 send_arcofi(cs); arcofi_fsm()
99 if (test_and_clear_bit(FLG_ARCOFI_TIMER, &cs->HW_Flags)) { arcofi_fsm()
100 del_timer(&cs->dc.isac.arcofitimer); arcofi_fsm()
102 cs->dc.isac.arcofi_state = ARCOFI_NOP; arcofi_fsm()
103 wake_up(&cs->dc.isac.arcofi_wait); arcofi_fsm()
108 debugl1(cs, "Arcofi unknown state %x", cs->dc.isac.arcofi_state); arcofi_fsm()
115 arcofi_timer(struct IsdnCardState *cs) { arcofi_timer() argument
116 arcofi_fsm(cs, ARCOFI_TIMEOUT, NULL); arcofi_timer()
120 clear_arcofi(struct IsdnCardState *cs) { clear_arcofi() argument
121 if (test_and_clear_bit(FLG_ARCOFI_TIMER, &cs->HW_Flags)) { clear_arcofi()
122 del_timer(&cs->dc.isac.arcofitimer); clear_arcofi()
127 init_arcofi(struct IsdnCardState *cs) { init_arcofi() argument
128 cs->dc.isac.arcofitimer.function = (void *) arcofi_timer; init_arcofi()
129 cs->dc.isac.arcofitimer.data = (long) cs; init_arcofi()
130 init_timer(&cs->dc.isac.arcofitimer); init_arcofi()
131 init_waitqueue_head(&cs->dc.isac.arcofi_wait); init_arcofi()
132 test_and_set_bit(HW_ARCOFI, &cs->HW_Flags); init_arcofi()
|
| H A D | amd7930_fn.c | 64 static void Amd7930_new_ph(struct IsdnCardState *cs);
102 WriteWordAmd7930(struct IsdnCardState *cs, BYTE reg, WORD val) WriteWordAmd7930() argument
104 wByteAMD(cs, 0x00, reg); WriteWordAmd7930()
105 wByteAMD(cs, 0x01, LOBYTE(val)); WriteWordAmd7930()
106 wByteAMD(cs, 0x01, HIBYTE(val)); WriteWordAmd7930()
110 ReadWordAmd7930(struct IsdnCardState *cs, BYTE reg) ReadWordAmd7930() argument
115 res = rByteAMD(cs, reg); ReadWordAmd7930()
116 res += 256 * rByteAMD(cs, reg); ReadWordAmd7930()
120 wByteAMD(cs, 0x00, reg); ReadWordAmd7930()
121 res = rByteAMD(cs, 0x01); ReadWordAmd7930()
122 res += 256 * rByteAMD(cs, 0x01); ReadWordAmd7930()
129 Amd7930_ph_command(struct IsdnCardState *cs, u_char command, char *s) Amd7930_ph_command() argument
131 if (cs->debug & L1_DEB_ISAC) Amd7930_ph_command()
132 debugl1(cs, "AMD7930: %s: ph_command 0x%02X", s, command); Amd7930_ph_command()
134 cs->dc.amd7930.lmr1 = command; Amd7930_ph_command()
135 wByteAMD(cs, 0xA3, command); Amd7930_ph_command()
160 Amd7930_get_state(struct IsdnCardState *cs) { Amd7930_get_state() argument
161 BYTE lsr = rByteAMD(cs, 0xA1); Amd7930_get_state()
162 cs->dc.amd7930.ph_state = (lsr & 0x7) + 2; Amd7930_get_state()
163 Amd7930_new_ph(cs); Amd7930_get_state()
169 Amd7930_new_ph(struct IsdnCardState *cs) Amd7930_new_ph() argument
171 u_char index = stateHelper[cs->dc.amd7930.old_state] * 8 + stateHelper[cs->dc.amd7930.ph_state] - 1; Amd7930_new_ph()
174 if (cs->debug & L1_DEB_ISAC) Amd7930_new_ph()
175 debugl1(cs, "AMD7930: new_ph %d, old_ph %d, message %d, index %d", Amd7930_new_ph()
176 cs->dc.amd7930.ph_state, cs->dc.amd7930.old_state, message & 0x0f, index); Amd7930_new_ph()
178 cs->dc.amd7930.old_state = cs->dc.amd7930.ph_state; Amd7930_new_ph()
181 if ((message & 0xf0) && (cs->tx_skb)) { Amd7930_new_ph()
182 wByteAMD(cs, 0x21, 0xC2); Amd7930_new_ph()
183 wByteAMD(cs, 0x21, 0x02); Amd7930_new_ph()
189 l1_msg(cs, HW_RESET | INDICATION, NULL); Amd7930_new_ph()
190 Amd7930_get_state(cs); Amd7930_new_ph()
193 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); Amd7930_new_ph()
196 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); Amd7930_new_ph()
199 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); Amd7930_new_ph()
200 Amd7930_ph_command(cs, 0x50, "HW_ENABLE REQUEST"); Amd7930_new_ph()
203 l1_msg(cs, HW_RSYNC | INDICATION, NULL); Amd7930_new_ph()
206 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); Amd7930_new_ph()
209 l1_msg(cs, HW_RSYNC | INDICATION, NULL); Amd7930_new_ph()
210 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); Amd7930_new_ph()
213 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); Amd7930_new_ph()
216 Amd7930_ph_command(cs, 0x40, "HW_ENABLE REQ cleared if set"); Amd7930_new_ph()
217 l1_msg(cs, HW_RSYNC | INDICATION, NULL); Amd7930_new_ph()
218 l1_msg(cs, HW_INFO2 | INDICATION, NULL); Amd7930_new_ph()
219 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); Amd7930_new_ph()
222 Amd7930_ph_command(cs, 0x40, "T3 expired, HW_ENABLE REQ cleared"); Amd7930_new_ph()
223 cs->dc.amd7930.old_state = 3; Amd7930_new_ph()
226 l1_msg(cs, HW_INFO2 | INDICATION, NULL); Amd7930_new_ph()
238 struct IsdnCardState *cs = Amd7930_bh() local
242 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { Amd7930_bh()
243 if (cs->debug) Amd7930_bh()
244 debugl1(cs, "Amd7930: bh, D-Channel Busy cleared"); Amd7930_bh()
245 stptr = cs->stlist; Amd7930_bh()
251 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { Amd7930_bh()
252 if (cs->debug & L1_DEB_ISAC) Amd7930_bh()
253 debugl1(cs, "AMD7930: bh, D_L1STATECHANGE"); Amd7930_bh()
254 Amd7930_new_ph(cs); Amd7930_bh()
257 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) { Amd7930_bh()
258 if (cs->debug & L1_DEB_ISAC) Amd7930_bh()
259 debugl1(cs, "AMD7930: bh, D_RCVBUFREADY"); Amd7930_bh()
260 DChannel_proc_rcv(cs); Amd7930_bh()
263 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) { Amd7930_bh()
264 if (cs->debug & L1_DEB_ISAC) Amd7930_bh()
265 debugl1(cs, "AMD7930: bh, D_XMTBUFREADY"); Amd7930_bh()
266 DChannel_proc_xmt(cs); Amd7930_bh()
271 Amd7930_empty_Dfifo(struct IsdnCardState *cs, int flag) Amd7930_empty_Dfifo() argument
279 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) Amd7930_empty_Dfifo()
280 debugl1(cs, "Amd7930: empty_Dfifo"); Amd7930_empty_Dfifo()
283 ptr = cs->rcvbuf + cs->rcvidx; Amd7930_empty_Dfifo()
286 AmdIrqOff(cs); Amd7930_empty_Dfifo()
289 stat = rByteAMD(cs, 0x07); // DSR2 Amd7930_empty_Dfifo()
292 while ((stat & 2) && ((ptr-cs->rcvbuf) < MAX_DFRAME_LEN_L1)) { Amd7930_empty_Dfifo()
293 *ptr = rByteAMD(cs, 0x04); // DCRB Amd7930_empty_Dfifo()
295 stat = rByteAMD(cs, 0x07); // DSR2 Amd7930_empty_Dfifo()
296 cs->rcvidx = ptr - cs->rcvbuf; Amd7930_empty_Dfifo()
301 der = rWordAMD(cs, 0x03); Amd7930_empty_Dfifo()
305 rWordAMD(cs, 0x89); // clear DRCR Amd7930_empty_Dfifo()
307 if ((cs->rcvidx) > 0) { Amd7930_empty_Dfifo()
308 if (!(skb = alloc_skb(cs->rcvidx, GFP_ATOMIC))) Amd7930_empty_Dfifo()
312 if (cs->debug & L1_DEB_ISAC_FIFO) { Amd7930_empty_Dfifo()
313 char *t = cs->dlog; Amd7930_empty_Dfifo()
315 t += sprintf(t, "Amd7930: empty_Dfifo cnt: %d |", cs->rcvidx); Amd7930_empty_Dfifo()
316 QuickHex(t, cs->rcvbuf, cs->rcvidx); Amd7930_empty_Dfifo()
317 debugl1(cs, "%s", cs->dlog); Amd7930_empty_Dfifo()
320 memcpy(skb_put(skb, cs->rcvidx), cs->rcvbuf, cs->rcvidx); Amd7930_empty_Dfifo()
321 skb_queue_tail(&cs->rq, skb); Amd7930_empty_Dfifo()
327 ptr = cs->rcvbuf; Amd7930_empty_Dfifo()
328 cs->rcvidx = 0; Amd7930_empty_Dfifo()
329 schedule_event(cs, D_RCVBUFREADY); Amd7930_empty_Dfifo()
333 if (cs->rcvidx >= MAX_DFRAME_LEN_L1) { Amd7930_empty_Dfifo()
334 if (cs->debug & L1_DEB_WARN) Amd7930_empty_Dfifo()
335 debugl1(cs, "AMD7930: empty_Dfifo L2-Framelength overrun"); Amd7930_empty_Dfifo()
336 cs->rcvidx = 0; Amd7930_empty_Dfifo()
340 AmdIrqOn(cs); Amd7930_empty_Dfifo()
345 Amd7930_fill_Dfifo(struct IsdnCardState *cs) Amd7930_fill_Dfifo() argument
352 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) Amd7930_fill_Dfifo()
353 debugl1(cs, "Amd7930: fill_Dfifo"); Amd7930_fill_Dfifo()
355 if ((!cs->tx_skb) || (cs->tx_skb->len <= 0)) Amd7930_fill_Dfifo()
359 if (!cs->dc.amd7930.tx_xmtlen) Amd7930_fill_Dfifo()
361 len = dtcrw = cs->tx_skb->len; Amd7930_fill_Dfifo()
363 else len = cs->dc.amd7930.tx_xmtlen; Amd7930_fill_Dfifo()
367 AmdIrqOff(cs); Amd7930_fill_Dfifo()
369 deb_ptr = ptr = cs->tx_skb->data; Amd7930_fill_Dfifo()
373 while ((txstat & 0x10) && (cs->tx_cnt < len)) { Amd7930_fill_Dfifo()
374 wByteAMD(cs, 0x04, *ptr); Amd7930_fill_Dfifo()
376 cs->tx_cnt++; Amd7930_fill_Dfifo()
377 txstat = rByteAMD(cs, 0x07); Amd7930_fill_Dfifo()
379 count = ptr - cs->tx_skb->data; Amd7930_fill_Dfifo()
380 skb_pull(cs->tx_skb, count); Amd7930_fill_Dfifo()
383 dtcrr = rWordAMD(cs, 0x85); // DTCR Amd7930_fill_Dfifo()
384 dmr3 = rByteAMD(cs, 0x8E); Amd7930_fill_Dfifo()
386 if (cs->debug & L1_DEB_ISAC) { Amd7930_fill_Dfifo()
387 debugl1(cs, "Amd7930: fill_Dfifo, DMR3: 0x%02X, DTCR read: 0x%04X write: 0x%02X 0x%02X", dmr3, dtcrr, LOBYTE(dtcrw), HIBYTE(dtcrw)); Amd7930_fill_Dfifo()
391 if (!cs->dc.amd7930.tx_xmtlen) { Amd7930_fill_Dfifo()
392 wWordAMD(cs, 0x85, dtcrw); Amd7930_fill_Dfifo()
393 cs->dc.amd7930.tx_xmtlen = dtcrw; Amd7930_fill_Dfifo()
396 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { Amd7930_fill_Dfifo()
397 debugl1(cs, "Amd7930: fill_Dfifo dbusytimer running"); Amd7930_fill_Dfifo()
398 del_timer(&cs->dbusytimer); Amd7930_fill_Dfifo()
400 init_timer(&cs->dbusytimer); Amd7930_fill_Dfifo()
401 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000); Amd7930_fill_Dfifo()
402 add_timer(&cs->dbusytimer); Amd7930_fill_Dfifo()
404 if (cs->debug & L1_DEB_ISAC_FIFO) { Amd7930_fill_Dfifo()
405 char *t = cs->dlog; Amd7930_fill_Dfifo()
409 debugl1(cs, "%s", cs->dlog); Amd7930_fill_Dfifo()
412 AmdIrqOn(cs); Amd7930_fill_Dfifo()
416 void Amd7930_interrupt(struct IsdnCardState *cs, BYTE irflags) Amd7930_interrupt() argument
424 dsr1 = rByteAMD(cs, 0x02); Amd7930_interrupt()
425 der = rWordAMD(cs, 0x03); Amd7930_interrupt()
426 dsr2 = rByteAMD(cs, 0x07); Amd7930_interrupt()
427 lsr = rByteAMD(cs, 0xA1); Amd7930_interrupt()
429 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
430 debugl1(cs, "Amd7930: interrupt: flags: 0x%02X, DSR1: 0x%02X, DSR2: 0x%02X, LSR: 0x%02X, DER=0x%04X", irflags, dsr1, dsr2, lsr, der); Amd7930_interrupt()
435 if (cs->debug & L1_DEB_WARN) Amd7930_interrupt()
436 debugl1(cs, "Amd7930: interrupt: D error DER=0x%04X", der); Amd7930_interrupt()
440 wByteAMD(cs, 0x21, 0xC2); Amd7930_interrupt()
441 wByteAMD(cs, 0x21, 0x02); Amd7930_interrupt()
442 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) Amd7930_interrupt()
443 del_timer(&cs->dbusytimer); Amd7930_interrupt()
444 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) Amd7930_interrupt()
445 schedule_event(cs, D_CLEARBUSY); Amd7930_interrupt()
447 if (cs->tx_skb) { Amd7930_interrupt()
448 skb_push(cs->tx_skb, cs->tx_cnt); Amd7930_interrupt()
449 cs->tx_cnt = 0; Amd7930_interrupt()
450 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_interrupt()
451 Amd7930_fill_Dfifo(cs); Amd7930_interrupt()
454 debugl1(cs, "Amd7930: interrupt: D-Collision, no skb"); Amd7930_interrupt()
458 Amd7930_empty_Dfifo(cs, 1); Amd7930_interrupt()
460 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) Amd7930_interrupt()
461 del_timer(&cs->dbusytimer); Amd7930_interrupt()
462 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) Amd7930_interrupt()
463 schedule_event(cs, D_CLEARBUSY); Amd7930_interrupt()
465 if (cs->tx_skb) { Amd7930_interrupt()
466 skb_push(cs->tx_skb, cs->tx_cnt); Amd7930_interrupt()
467 cs->tx_cnt = 0; Amd7930_interrupt()
468 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_interrupt()
469 Amd7930_fill_Dfifo(cs); Amd7930_interrupt()
475 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
476 debugl1(cs, "Amd7930: interrupt: clear Timer and fill D-TX-FIFO if data"); Amd7930_interrupt()
479 AmdIrqOff(cs); Amd7930_interrupt()
481 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) Amd7930_interrupt()
482 del_timer(&cs->dbusytimer); Amd7930_interrupt()
483 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) Amd7930_interrupt()
484 schedule_event(cs, D_CLEARBUSY); Amd7930_interrupt()
485 if (cs->tx_skb) { Amd7930_interrupt()
486 if (cs->tx_skb->len) Amd7930_interrupt()
487 Amd7930_fill_Dfifo(cs); Amd7930_interrupt()
490 AmdIrqOn(cs); Amd7930_interrupt()
496 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
497 debugl1(cs, "Amd7930: interrupt: empty D-FIFO"); Amd7930_interrupt()
498 Amd7930_empty_Dfifo(cs, 0); Amd7930_interrupt()
504 if (cs->debug & L1_DEB_ISAC) { Amd7930_interrupt()
505 debugl1(cs, "Amd7930: interrupt: transmit packet ready"); Amd7930_interrupt()
508 AmdIrqOff(cs); Amd7930_interrupt()
510 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) Amd7930_interrupt()
511 del_timer(&cs->dbusytimer); Amd7930_interrupt()
512 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) Amd7930_interrupt()
513 schedule_event(cs, D_CLEARBUSY); Amd7930_interrupt()
515 if (cs->tx_skb) { Amd7930_interrupt()
516 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
517 debugl1(cs, "Amd7930: interrupt: TX-Packet ready, freeing skb"); Amd7930_interrupt()
518 dev_kfree_skb_irq(cs->tx_skb); Amd7930_interrupt()
519 cs->tx_cnt = 0; Amd7930_interrupt()
520 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_interrupt()
521 cs->tx_skb = NULL; Amd7930_interrupt()
523 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { Amd7930_interrupt()
524 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
525 debugl1(cs, "Amd7930: interrupt: TX-Packet ready, next packet dequeued"); Amd7930_interrupt()
526 cs->tx_cnt = 0; Amd7930_interrupt()
527 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_interrupt()
528 Amd7930_fill_Dfifo(cs); Amd7930_interrupt()
531 schedule_event(cs, D_XMTBUFREADY); Amd7930_interrupt()
533 AmdIrqOn(cs); Amd7930_interrupt()
539 AmdIrqOff(cs); Amd7930_interrupt()
541 if (cs->debug & L1_DEB_ISAC) Amd7930_interrupt()
542 debugl1(cs, "Amd: interrupt: LSR=0x%02X, LIU is in state %d", lsr, ((lsr & 0x7) + 2)); Amd7930_interrupt()
544 cs->dc.amd7930.ph_state = (lsr & 0x7) + 2; Amd7930_interrupt()
546 schedule_event(cs, D_L1STATECHANGE); Amd7930_interrupt()
548 AmdIrqOn(cs); Amd7930_interrupt()
552 irflags = rByteAMD(cs, 0x00); Amd7930_interrupt()
560 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; Amd7930_l1hw() local
564 if (cs->debug & L1_DEB_ISAC) Amd7930_l1hw()
565 debugl1(cs, "Amd7930: l1hw called, pr: 0x%04X", pr); Amd7930_l1hw()
569 if (cs->debug & DEB_DLOG_HEX) Amd7930_l1hw()
570 LogFrame(cs, skb->data, skb->len); Amd7930_l1hw()
571 if (cs->debug & DEB_DLOG_VERBOSE) Amd7930_l1hw()
572 dlogframe(cs, skb, 0); Amd7930_l1hw()
573 spin_lock_irqsave(&cs->lock, flags); Amd7930_l1hw()
574 if (cs->tx_skb) { Amd7930_l1hw()
575 skb_queue_tail(&cs->sq, skb); Amd7930_l1hw()
577 if (cs->debug & L1_DEB_LAPD) Amd7930_l1hw()
578 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA Queued", 0); Amd7930_l1hw()
581 cs->tx_skb = skb; Amd7930_l1hw()
582 cs->tx_cnt = 0; Amd7930_l1hw()
583 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_l1hw()
585 if (cs->debug & L1_DEB_LAPD) Amd7930_l1hw()
586 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA", 0); Amd7930_l1hw()
588 Amd7930_fill_Dfifo(cs); Amd7930_l1hw()
590 spin_unlock_irqrestore(&cs->lock, flags); Amd7930_l1hw()
593 spin_lock_irqsave(&cs->lock, flags); Amd7930_l1hw()
594 if (cs->tx_skb) { Amd7930_l1hw()
595 if (cs->debug & L1_DEB_WARN) Amd7930_l1hw()
596 debugl1(cs, "Amd7930: l1hw: l2l1 tx_skb exist this shouldn't happen"); Amd7930_l1hw()
597 skb_queue_tail(&cs->sq, skb); Amd7930_l1hw()
598 spin_unlock_irqrestore(&cs->lock, flags); Amd7930_l1hw()
601 if (cs->debug & DEB_DLOG_HEX) Amd7930_l1hw()
602 LogFrame(cs, skb->data, skb->len); Amd7930_l1hw()
603 if (cs->debug & DEB_DLOG_VERBOSE) Amd7930_l1hw()
604 dlogframe(cs, skb, 0); Amd7930_l1hw()
605 cs->tx_skb = skb; Amd7930_l1hw()
606 cs->tx_cnt = 0; Amd7930_l1hw()
607 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_l1hw()
609 if (cs->debug & L1_DEB_LAPD) Amd7930_l1hw()
610 Logl2Frame(cs, skb, "Amd7930: l1hw: PH_DATA_PULLED", 0); Amd7930_l1hw()
612 Amd7930_fill_Dfifo(cs); Amd7930_l1hw()
613 spin_unlock_irqrestore(&cs->lock, flags); Amd7930_l1hw()
617 if (cs->debug & L1_DEB_LAPD) Amd7930_l1hw()
618 debugl1(cs, "Amd7930: l1hw: -> PH_REQUEST_PULL, skb: %s", (cs->tx_skb) ? "yes" : "no"); Amd7930_l1hw()
620 if (!cs->tx_skb) { Amd7930_l1hw()
627 spin_lock_irqsave(&cs->lock, flags); Amd7930_l1hw()
628 if ((cs->dc.amd7930.ph_state == 8)) { Amd7930_l1hw()
631 Amd7930_ph_command(cs, 0x20, "HW_RESET REQUEST"); //LMR1 bit 5 Amd7930_l1hw()
632 spin_unlock_irqrestore(&cs->lock, flags); Amd7930_l1hw()
634 Amd7930_ph_command(cs, 0x40, "HW_RESET REQUEST"); Amd7930_l1hw()
635 cs->dc.amd7930.ph_state = 2; Amd7930_l1hw()
636 spin_unlock_irqrestore(&cs->lock, flags); Amd7930_l1hw()
637 Amd7930_new_ph(cs); Amd7930_l1hw()
641 cs->dc.amd7930.ph_state = 9; Amd7930_l1hw()
642 Amd7930_new_ph(cs); Amd7930_l1hw()
651 skb_queue_purge(&cs->rq); Amd7930_l1hw()
652 skb_queue_purge(&cs->sq); Amd7930_l1hw()
653 if (cs->tx_skb) { Amd7930_l1hw()
654 dev_kfree_skb(cs->tx_skb); Amd7930_l1hw()
655 cs->tx_skb = NULL; Amd7930_l1hw()
657 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) Amd7930_l1hw()
658 del_timer(&cs->dbusytimer); Amd7930_l1hw()
659 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) Amd7930_l1hw()
660 schedule_event(cs, D_CLEARBUSY); Amd7930_l1hw()
663 if (cs->debug & L1_DEB_WARN) Amd7930_l1hw()
664 debugl1(cs, "Amd7930: l1hw: unknown %04x", pr); Amd7930_l1hw()
670 setstack_Amd7930(struct PStack *st, struct IsdnCardState *cs) setstack_Amd7930() argument
673 if (cs->debug & L1_DEB_ISAC) setstack_Amd7930()
674 debugl1(cs, "Amd7930: setstack called"); setstack_Amd7930()
681 DC_Close_Amd7930(struct IsdnCardState *cs) { DC_Close_Amd7930() argument
682 if (cs->debug & L1_DEB_ISAC) DC_Close_Amd7930()
683 debugl1(cs, "Amd7930: DC_Close called"); DC_Close_Amd7930()
688 dbusy_timer_handler(struct IsdnCardState *cs) dbusy_timer_handler() argument
696 if (cs->debug & L1_DEB_ISAC) dbusy_timer_handler()
697 debugl1(cs, "Amd7930: dbusy_timer expired!"); dbusy_timer_handler()
699 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dbusy_timer_handler()
700 spin_lock_irqsave(&cs->lock, flags); dbusy_timer_handler()
703 dtcr = rWordAMD(cs, 0x85); dbusy_timer_handler()
704 dsr1 = rByteAMD(cs, 0x02); dbusy_timer_handler()
705 dsr2 = rByteAMD(cs, 0x07); dbusy_timer_handler()
706 der = rWordAMD(cs, 0x03); dbusy_timer_handler()
708 if (cs->debug & L1_DEB_ISAC) dbusy_timer_handler()
709 debugl1(cs, "Amd7930: dbusy_timer_handler: DSR1=0x%02X, DSR2=0x%02X, DER=0x%04X, cs->tx_skb->len=%u, tx_stat=%u, dtcr=%u, cs->tx_cnt=%u", dsr1, dsr2, der, cs->tx_skb->len, cs->dc.amd7930.tx_xmtlen, dtcr, cs->tx_cnt); dbusy_timer_handler()
711 if ((cs->dc.amd7930.tx_xmtlen - dtcr) < cs->tx_cnt) { /* D-Channel Busy */ dbusy_timer_handler()
712 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags); dbusy_timer_handler()
713 stptr = cs->stlist; dbusy_timer_handler()
714 spin_unlock_irqrestore(&cs->lock, flags); dbusy_timer_handler()
722 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); dbusy_timer_handler()
723 if (cs->tx_skb) { dbusy_timer_handler()
724 dev_kfree_skb_any(cs->tx_skb); dbusy_timer_handler()
725 cs->tx_cnt = 0; dbusy_timer_handler()
726 cs->tx_skb = NULL; dbusy_timer_handler()
727 cs->dc.amd7930.tx_xmtlen = 0; dbusy_timer_handler()
730 debugl1(cs, "Amd7930: D-Channel Busy no skb"); dbusy_timer_handler()
734 wByteAMD(cs, 0x21, 0x82); dbusy_timer_handler()
735 wByteAMD(cs, 0x21, 0x02); dbusy_timer_handler()
736 spin_unlock_irqrestore(&cs->lock, flags); dbusy_timer_handler()
737 cs->irq_func(cs->irq, cs); dbusy_timer_handler()
739 if (cs->debug & L1_DEB_ISAC) dbusy_timer_handler()
740 debugl1(cs, "Amd7930: dbusy_timer_handler: Transmitter reset"); dbusy_timer_handler()
747 void Amd7930_init(struct IsdnCardState *cs) Amd7930_init() argument
752 if (cs->debug & L1_DEB_ISAC) Amd7930_init()
753 debugl1(cs, "Amd7930: initamd called"); Amd7930_init()
755 cs->dc.amd7930.tx_xmtlen = 0; Amd7930_init()
756 cs->dc.amd7930.old_state = 0; Amd7930_init()
757 cs->dc.amd7930.lmr1 = 0x40; Amd7930_init()
758 cs->dc.amd7930.ph_command = Amd7930_ph_command; Amd7930_init()
759 cs->setstack_d = setstack_Amd7930; Amd7930_init()
760 cs->DC_Close = DC_Close_Amd7930; Amd7930_init()
770 rByteAMD(cs, cmd); Amd7930_init()
772 wByteAMD(cs, 0x00, cmd); Amd7930_init()
774 rByteAMD(cs, 0x01); Amd7930_init()
779 wByteAMD(cs, cmd, LOBYTE(*ptr++)); Amd7930_init()
782 wByteAMD(cs, 0x00, cmd); Amd7930_init()
784 wByteAMD(cs, 0x01, LOBYTE(*ptr++)); Amd7930_init()
789 void setup_Amd7930(struct IsdnCardState *cs) setup_Amd7930() argument
791 INIT_WORK(&cs->tqueue, Amd7930_bh); setup_Amd7930()
792 cs->dbusytimer.function = (void *) dbusy_timer_handler; setup_Amd7930()
793 cs->dbusytimer.data = (long) cs; setup_Amd7930()
794 init_timer(&cs->dbusytimer); setup_Amd7930()
|
| H A D | teleint.c | 103 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
105 cs->hw.hfc.cip = offset; ReadISAC()
106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); ReadISAC()
110 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
112 cs->hw.hfc.cip = offset; WriteISAC()
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); WriteISAC()
117 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
119 cs->hw.hfc.cip = 0; ReadISACfifo()
120 readfifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); ReadISACfifo()
124 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
126 cs->hw.hfc.cip = 0; WriteISACfifo()
127 writefifo(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, 0, data, size); WriteISACfifo()
131 ReadHFC(struct IsdnCardState *cs, int data, u_char reg) ReadHFC() argument
136 cs->hw.hfc.cip = reg; ReadHFC()
137 byteout(cs->hw.hfc.addr | 1, reg); ReadHFC()
138 ret = bytein(cs->hw.hfc.addr); ReadHFC()
139 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) ReadHFC()
140 debugl1(cs, "hfc RD %02x %02x", reg, ret); ReadHFC()
142 ret = bytein(cs->hw.hfc.addr | 1); ReadHFC()
147 WriteHFC(struct IsdnCardState *cs, int data, u_char reg, u_char value) WriteHFC() argument
149 byteout(cs->hw.hfc.addr | 1, reg); WriteHFC()
150 cs->hw.hfc.cip = reg; WriteHFC()
152 byteout(cs->hw.hfc.addr, value); WriteHFC()
153 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) WriteHFC()
154 debugl1(cs, "hfc W%c %02x %02x", data ? 'D' : 'C', reg, value); WriteHFC()
160 struct IsdnCardState *cs = dev_id; TeleInt_interrupt() local
164 spin_lock_irqsave(&cs->lock, flags); TeleInt_interrupt()
165 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA); TeleInt_interrupt()
168 isac_interrupt(cs, val); TeleInt_interrupt()
169 val = readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_ISTA); TeleInt_interrupt()
171 if (cs->debug & L1_DEB_ISAC) TeleInt_interrupt()
172 debugl1(cs, "ISAC IntStat after IntRoutine"); TeleInt_interrupt()
175 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF); TeleInt_interrupt()
176 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0); TeleInt_interrupt()
177 spin_unlock_irqrestore(&cs->lock, flags); TeleInt_interrupt()
182 TeleInt_Timer(struct IsdnCardState *cs) TeleInt_Timer() argument
187 spin_lock_irqsave(&cs->lock, flags); TeleInt_Timer()
188 if (cs->bcs[0].mode) { TeleInt_Timer()
190 main_irq_hfc(&cs->bcs[0]); TeleInt_Timer()
192 if (cs->bcs[1].mode) { TeleInt_Timer()
194 main_irq_hfc(&cs->bcs[1]); TeleInt_Timer()
196 spin_unlock_irqrestore(&cs->lock, flags); TeleInt_Timer()
200 cs->hw.hfc.timer.expires = jiffies + stat; TeleInt_Timer()
201 add_timer(&cs->hw.hfc.timer); TeleInt_Timer()
205 release_io_TeleInt(struct IsdnCardState *cs) release_io_TeleInt() argument
207 del_timer(&cs->hw.hfc.timer); release_io_TeleInt()
208 releasehfc(cs); release_io_TeleInt()
209 if (cs->hw.hfc.addr) release_io_TeleInt()
210 release_region(cs->hw.hfc.addr, 2); release_io_TeleInt()
214 reset_TeleInt(struct IsdnCardState *cs) reset_TeleInt() argument
217 cs->hw.hfc.cirm |= HFC_RESET; reset_TeleInt()
218 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); /* Reset On */ reset_TeleInt()
220 cs->hw.hfc.cirm &= ~HFC_RESET; reset_TeleInt()
221 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); /* Reset Off */ reset_TeleInt()
226 TeleInt_card_msg(struct IsdnCardState *cs, int mt, void *arg) TeleInt_card_msg() argument
233 spin_lock_irqsave(&cs->lock, flags); TeleInt_card_msg()
234 reset_TeleInt(cs); TeleInt_card_msg()
235 spin_unlock_irqrestore(&cs->lock, flags); TeleInt_card_msg()
238 release_io_TeleInt(cs); TeleInt_card_msg()
241 spin_lock_irqsave(&cs->lock, flags); TeleInt_card_msg()
242 reset_TeleInt(cs); TeleInt_card_msg()
243 inithfc(cs); TeleInt_card_msg()
244 clear_pending_isac_ints(cs); TeleInt_card_msg()
245 initisac(cs); TeleInt_card_msg()
247 cs->writeisac(cs, ISAC_MASK, 0); TeleInt_card_msg()
248 cs->writeisac(cs, ISAC_CMDR, 0x41); TeleInt_card_msg()
249 spin_unlock_irqrestore(&cs->lock, flags); TeleInt_card_msg()
253 cs->hw.hfc.timer.expires = jiffies + delay; TeleInt_card_msg()
254 add_timer(&cs->hw.hfc.timer); TeleInt_card_msg()
264 struct IsdnCardState *cs = card->cs; setup_TeleInt() local
269 if (cs->typ != ISDN_CTYPE_TELEINT) setup_TeleInt()
272 cs->hw.hfc.addr = card->para[1] & 0x3fe; setup_TeleInt()
273 cs->irq = card->para[0]; setup_TeleInt()
274 cs->hw.hfc.cirm = HFC_CIRM; setup_TeleInt()
275 cs->hw.hfc.isac_spcr = 0x00; setup_TeleInt()
276 cs->hw.hfc.cip = 0; setup_TeleInt()
277 cs->hw.hfc.ctmt = HFC_CTMT | HFC_CLTIMER; setup_TeleInt()
278 cs->bcs[0].hw.hfc.send = NULL; setup_TeleInt()
279 cs->bcs[1].hw.hfc.send = NULL; setup_TeleInt()
280 cs->hw.hfc.fifosize = 7 * 1024 + 512; setup_TeleInt()
281 cs->hw.hfc.timer.function = (void *) TeleInt_Timer; setup_TeleInt()
282 cs->hw.hfc.timer.data = (long) cs; setup_TeleInt()
283 init_timer(&cs->hw.hfc.timer); setup_TeleInt()
284 if (!request_region(cs->hw.hfc.addr, 2, "TeleInt isdn")) { setup_TeleInt()
287 cs->hw.hfc.addr, setup_TeleInt()
288 cs->hw.hfc.addr + 2); setup_TeleInt()
292 byteout(cs->hw.hfc.addr, cs->hw.hfc.addr & 0xff); setup_TeleInt()
293 byteout(cs->hw.hfc.addr | 1, ((cs->hw.hfc.addr & 0x300) >> 8) | 0x54); setup_TeleInt()
294 switch (cs->irq) { setup_TeleInt()
296 cs->hw.hfc.cirm |= HFC_INTA; setup_TeleInt()
299 cs->hw.hfc.cirm |= HFC_INTB; setup_TeleInt()
302 cs->hw.hfc.cirm |= HFC_INTC; setup_TeleInt()
305 cs->hw.hfc.cirm |= HFC_INTD; setup_TeleInt()
308 cs->hw.hfc.cirm |= HFC_INTE; setup_TeleInt()
311 cs->hw.hfc.cirm |= HFC_INTF; setup_TeleInt()
315 release_io_TeleInt(cs); setup_TeleInt()
318 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.cirm); setup_TeleInt()
319 byteout(cs->hw.hfc.addr | 1, cs->hw.hfc.ctmt); setup_TeleInt()
322 cs->hw.hfc.addr, cs->irq); setup_TeleInt()
324 setup_isac(cs); setup_TeleInt()
325 cs->readisac = &ReadISAC; setup_TeleInt()
326 cs->writeisac = &WriteISAC; setup_TeleInt()
327 cs->readisacfifo = &ReadISACfifo; setup_TeleInt()
328 cs->writeisacfifo = &WriteISACfifo; setup_TeleInt()
329 cs->BC_Read_Reg = &ReadHFC; setup_TeleInt()
330 cs->BC_Write_Reg = &WriteHFC; setup_TeleInt()
331 cs->cardmsg = &TeleInt_card_msg; setup_TeleInt()
332 cs->irq_func = &TeleInt_interrupt; setup_TeleInt()
333 ISACVersion(cs, "TeleInt:"); setup_TeleInt()
|
| H A D | hfcscard.c | 24 struct IsdnCardState *cs = dev_id; hfcs_interrupt() local
28 spin_lock_irqsave(&cs->lock, flags); hfcs_interrupt()
30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); hfcs_interrupt()
32 if (cs->debug & L1_DEB_ISAC) hfcs_interrupt()
33 debugl1(cs, "HFCS: stat(%02x) s1(%02x)", stat, val); hfcs_interrupt()
34 hfc2bds0_interrupt(cs, val); hfcs_interrupt()
36 if (cs->debug & L1_DEB_ISAC) hfcs_interrupt()
37 debugl1(cs, "HFCS: irq_no_irq stat(%02x)", stat); hfcs_interrupt()
39 spin_unlock_irqrestore(&cs->lock, flags); hfcs_interrupt()
44 hfcs_Timer(struct IsdnCardState *cs) hfcs_Timer() argument
46 cs->hw.hfcD.timer.expires = jiffies + 75; hfcs_Timer()
48 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt | 0x80); hfcs_Timer()
49 add_timer(&cs->hw.hfcD.timer); hfcs_Timer()
54 release_io_hfcs(struct IsdnCardState *cs) release_io_hfcs() argument
56 release2bds0(cs); release_io_hfcs()
57 del_timer(&cs->hw.hfcD.timer); release_io_hfcs()
58 if (cs->hw.hfcD.addr) release_io_hfcs()
59 release_region(cs->hw.hfcD.addr, 2); release_io_hfcs()
63 reset_hfcs(struct IsdnCardState *cs) reset_hfcs() argument
66 cs->hw.hfcD.cirm = HFCD_RESET; reset_hfcs()
67 if (cs->typ == ISDN_CTYPE_TELES3C) reset_hfcs()
68 cs->hw.hfcD.cirm |= HFCD_MEM8K; reset_hfcs()
69 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ reset_hfcs()
71 cs->hw.hfcD.cirm = 0; reset_hfcs()
72 if (cs->typ == ISDN_CTYPE_TELES3C) reset_hfcs()
73 cs->hw.hfcD.cirm |= HFCD_MEM8K; reset_hfcs()
74 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ reset_hfcs()
76 if (cs->typ == ISDN_CTYPE_TELES3C) reset_hfcs()
77 cs->hw.hfcD.cirm |= HFCD_INTB; reset_hfcs()
78 else if (cs->typ == ISDN_CTYPE_ACERP10) reset_hfcs()
79 cs->hw.hfcD.cirm |= HFCD_INTA; reset_hfcs()
80 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); reset_hfcs()
81 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e); reset_hfcs()
82 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */ reset_hfcs()
83 cs->hw.hfcD.ctmt = HFCD_TIM25 | HFCD_AUTO_TIMER; reset_hfcs()
84 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); reset_hfcs()
85 cs->hw.hfcD.int_m2 = HFCD_IRQ_ENABLE; reset_hfcs()
86 cs->hw.hfcD.int_m1 = HFCD_INTS_B1TRANS | HFCD_INTS_B2TRANS | reset_hfcs()
89 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); reset_hfcs()
91 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */ reset_hfcs()
93 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */ reset_hfcs()
94 cs->hw.hfcD.mst_m = HFCD_MASTER; reset_hfcs()
95 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */ reset_hfcs()
96 cs->hw.hfcD.sctrl = 0; reset_hfcs()
97 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); reset_hfcs()
101 hfcs_card_msg(struct IsdnCardState *cs, int mt, void *arg) hfcs_card_msg() argument
106 if (cs->debug & L1_DEB_ISAC) hfcs_card_msg()
107 debugl1(cs, "HFCS: card_msg %x", mt); hfcs_card_msg()
110 spin_lock_irqsave(&cs->lock, flags); hfcs_card_msg()
111 reset_hfcs(cs); hfcs_card_msg()
112 spin_unlock_irqrestore(&cs->lock, flags); hfcs_card_msg()
115 release_io_hfcs(cs); hfcs_card_msg()
119 mod_timer(&cs->hw.hfcD.timer, jiffies + delay); hfcs_card_msg()
120 spin_lock_irqsave(&cs->lock, flags); hfcs_card_msg()
121 reset_hfcs(cs); hfcs_card_msg()
122 init2bds0(cs); hfcs_card_msg()
123 spin_unlock_irqrestore(&cs->lock, flags); hfcs_card_msg()
126 spin_lock_irqsave(&cs->lock, flags); hfcs_card_msg()
127 cs->hw.hfcD.ctmt |= HFCD_TIM800; hfcs_card_msg()
128 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); hfcs_card_msg()
129 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); hfcs_card_msg()
130 spin_unlock_irqrestore(&cs->lock, flags); hfcs_card_msg()
170 struct IsdnCardState *cs = card->cs; setup_hfcs() local
218 cs->hw.hfcD.addr = card->para[1] & 0xfffe; setup_hfcs()
219 cs->irq = card->para[0]; setup_hfcs()
220 cs->hw.hfcD.cip = 0; setup_hfcs()
221 cs->hw.hfcD.int_s1 = 0; setup_hfcs()
222 cs->hw.hfcD.send = NULL; setup_hfcs()
223 cs->bcs[0].hw.hfc.send = NULL; setup_hfcs()
224 cs->bcs[1].hw.hfc.send = NULL; setup_hfcs()
225 cs->hw.hfcD.dfifosize = 512; setup_hfcs()
226 cs->dc.hfcd.ph_state = 0; setup_hfcs()
227 cs->hw.hfcD.fifo = 255; setup_hfcs()
228 if (cs->typ == ISDN_CTYPE_TELES3C) { setup_hfcs()
229 cs->hw.hfcD.bfifosize = 1024 + 512; setup_hfcs()
230 } else if (cs->typ == ISDN_CTYPE_ACERP10) { setup_hfcs()
231 cs->hw.hfcD.bfifosize = 7 * 1024 + 512; setup_hfcs()
234 if (!request_region(cs->hw.hfcD.addr, 2, "HFCS isdn")) { setup_hfcs()
238 cs->hw.hfcD.addr, setup_hfcs()
239 cs->hw.hfcD.addr + 2); setup_hfcs()
244 cs->hw.hfcD.addr, setup_hfcs()
245 cs->irq, HZ); setup_hfcs()
246 if (cs->typ == ISDN_CTYPE_TELES3C) { setup_hfcs()
248 outb(0x00, cs->hw.hfcD.addr); setup_hfcs()
249 outb(0x56, cs->hw.hfcD.addr | 1); setup_hfcs()
250 } else if (cs->typ == ISDN_CTYPE_ACERP10) { setup_hfcs()
252 outb(0x00, cs->hw.hfcD.addr); setup_hfcs()
253 outb(0x57, cs->hw.hfcD.addr | 1); setup_hfcs()
255 set_cs_func(cs); setup_hfcs()
256 cs->hw.hfcD.timer.function = (void *) hfcs_Timer; setup_hfcs()
257 cs->hw.hfcD.timer.data = (long) cs; setup_hfcs()
258 init_timer(&cs->hw.hfcD.timer); setup_hfcs()
259 cs->cardmsg = &hfcs_card_msg; setup_hfcs()
260 cs->irq_func = &hfcs_interrupt; setup_hfcs()
|
| H A D | saphir.c | 68 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
70 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset)); ReadISAC()
74 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
76 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); WriteISAC()
80 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
82 readfifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); ReadISACfifo()
86 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
88 writefifo(cs->hw.saphir.ale, cs->hw.saphir.isac, 0, data, size); WriteISACfifo()
92 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
94 return (readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, ReadHSCX()
99 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
101 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, WriteHSCX()
105 #define READHSCX(cs, nr, reg) readreg(cs->hw.saphir.ale, \
106 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
107 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
108 cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0), data)
110 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.saphir.ale, \
111 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
113 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.saphir.ale, \
114 cs->hw.saphir.hscx, (nr ? 0x40 : 0), ptr, cnt)
121 struct IsdnCardState *cs = dev_id; saphir_interrupt() local
125 spin_lock_irqsave(&cs->lock, flags); saphir_interrupt()
126 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt()
129 hscx_int_main(cs, val); saphir_interrupt()
130 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); saphir_interrupt()
133 isac_interrupt(cs, val); saphir_interrupt()
134 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_ISTA + 0x40); saphir_interrupt()
136 if (cs->debug & L1_DEB_HSCX) saphir_interrupt()
137 debugl1(cs, "HSCX IntStat after IntRoutine"); saphir_interrupt()
140 val = readreg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_ISTA); saphir_interrupt()
142 if (cs->debug & L1_DEB_ISAC) saphir_interrupt()
143 debugl1(cs, "ISAC IntStat after IntRoutine"); saphir_interrupt()
147 if (cs->hw.saphir.timer.function) saphir_interrupt()
148 mod_timer(&cs->hw.saphir.timer, jiffies + 1 * HZ); saphir_interrupt()
151 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); saphir_interrupt()
152 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); saphir_interrupt()
153 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); saphir_interrupt()
154 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); saphir_interrupt()
155 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); saphir_interrupt()
156 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); saphir_interrupt()
157 spin_unlock_irqrestore(&cs->lock, flags); saphir_interrupt()
162 SaphirWatchDog(struct IsdnCardState *cs) SaphirWatchDog() argument
166 spin_lock_irqsave(&cs->lock, flags); SaphirWatchDog()
168 cs->readisac(cs, ISAC_RBCH); SaphirWatchDog()
169 spin_unlock_irqrestore(&cs->lock, flags); SaphirWatchDog()
170 mod_timer(&cs->hw.saphir.timer, jiffies + 1 * HZ); SaphirWatchDog()
174 release_io_saphir(struct IsdnCardState *cs) release_io_saphir() argument
176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff); release_io_saphir()
177 del_timer(&cs->hw.saphir.timer); release_io_saphir()
178 cs->hw.saphir.timer.function = NULL; release_io_saphir()
179 if (cs->hw.saphir.cfg_reg) release_io_saphir()
180 release_region(cs->hw.saphir.cfg_reg, 6); release_io_saphir()
184 saphir_reset(struct IsdnCardState *cs) saphir_reset() argument
188 switch (cs->irq) { saphir_reset()
204 cs->irq); saphir_reset()
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); saphir_reset()
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1); saphir_reset()
210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0); saphir_reset()
212 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); saphir_reset()
213 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02); saphir_reset()
218 saphir_card_msg(struct IsdnCardState *cs, int mt, void *arg) saphir_card_msg() argument
224 spin_lock_irqsave(&cs->lock, flags); saphir_card_msg()
225 saphir_reset(cs); saphir_card_msg()
226 spin_unlock_irqrestore(&cs->lock, flags); saphir_card_msg()
229 release_io_saphir(cs); saphir_card_msg()
232 spin_lock_irqsave(&cs->lock, flags); saphir_card_msg()
233 inithscxisac(cs, 3); saphir_card_msg()
234 spin_unlock_irqrestore(&cs->lock, flags); saphir_card_msg()
245 struct IsdnCardState *cs = card->cs; setup_saphir() local
250 if (cs->typ != ISDN_CTYPE_HSTSAPHIR) setup_saphir()
254 cs->hw.saphir.cfg_reg = card->para[1]; setup_saphir()
255 cs->hw.saphir.isac = card->para[1] + ISAC_DATA; setup_saphir()
256 cs->hw.saphir.hscx = card->para[1] + HSCX_DATA; setup_saphir()
257 cs->hw.saphir.ale = card->para[1] + ADDRESS_REG; setup_saphir()
258 cs->irq = card->para[0]; setup_saphir()
259 if (!request_region(cs->hw.saphir.cfg_reg, 6, "saphir")) { setup_saphir()
262 cs->hw.saphir.cfg_reg, setup_saphir()
263 cs->hw.saphir.cfg_reg + 5); setup_saphir()
268 cs->irq, cs->hw.saphir.cfg_reg); setup_saphir()
270 setup_isac(cs); setup_saphir()
271 cs->hw.saphir.timer.function = (void *) SaphirWatchDog; setup_saphir()
272 cs->hw.saphir.timer.data = (long) cs; setup_saphir()
273 init_timer(&cs->hw.saphir.timer); setup_saphir()
274 cs->hw.saphir.timer.expires = jiffies + 4 * HZ; setup_saphir()
275 add_timer(&cs->hw.saphir.timer); setup_saphir()
276 if (saphir_reset(cs)) { setup_saphir()
277 release_io_saphir(cs); setup_saphir()
280 cs->readisac = &ReadISAC; setup_saphir()
281 cs->writeisac = &WriteISAC; setup_saphir()
282 cs->readisacfifo = &ReadISACfifo; setup_saphir()
283 cs->writeisacfifo = &WriteISACfifo; setup_saphir()
284 cs->BC_Read_Reg = &ReadHSCX; setup_saphir()
285 cs->BC_Write_Reg = &WriteHSCX; setup_saphir()
286 cs->BC_Send_Data = &hscx_fill_fifo; setup_saphir()
287 cs->cardmsg = &saphir_card_msg; setup_saphir()
288 cs->irq_func = &saphir_interrupt; setup_saphir()
289 ISACVersion(cs, "saphir:"); setup_saphir()
290 if (HscxVersion(cs, "saphir:")) { setup_saphir()
293 release_io_saphir(cs); setup_saphir()
|
| H A D | hscx.c | 26 HscxVersion(struct IsdnCardState *cs, char *s) HscxVersion() argument
30 verA = cs->BC_Read_Reg(cs, 0, HSCX_VSTR) & 0xf; HscxVersion()
31 verB = cs->BC_Read_Reg(cs, 1, HSCX_VSTR) & 0xf; HscxVersion()
43 struct IsdnCardState *cs = bcs->cs; modehscx() local
46 if (cs->debug & L1_DEB_HSCX) modehscx()
47 debugl1(cs, "hscx %c mode %d ichan %d", modehscx()
51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); modehscx()
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); modehscx()
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx()
57 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x82 : 0x85); modehscx()
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); modehscx()
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); modehscx()
60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7); modehscx()
63 if (test_bit(HW_IOM1, &cs->HW_Flags) && (hscx == 0)) modehscx()
67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, modehscx()
68 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); modehscx()
69 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, modehscx()
70 test_bit(HW_IOM1, &cs->HW_Flags) ? 0x7 : bcs->hw.hscx.tsaxr0); modehscx()
72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1); modehscx()
73 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1); modehscx()
77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f); modehscx()
78 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f); modehscx()
79 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84); modehscx()
82 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4); modehscx()
85 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx()
86 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x8a : 0x8d); modehscx()
87 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c); modehscx()
91 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41); modehscx()
92 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00); modehscx()
104 spin_lock_irqsave(&bcs->cs->lock, flags); hscx_l2l1()
111 bcs->cs->BC_Send_Data(bcs); hscx_l2l1()
113 spin_unlock_irqrestore(&bcs->cs->lock, flags); hscx_l2l1()
116 spin_lock_irqsave(&bcs->cs->lock, flags); hscx_l2l1()
123 bcs->cs->BC_Send_Data(bcs); hscx_l2l1()
125 spin_unlock_irqrestore(&bcs->cs->lock, flags); hscx_l2l1()
135 spin_lock_irqsave(&bcs->cs->lock, flags); hscx_l2l1()
138 spin_unlock_irqrestore(&bcs->cs->lock, flags); hscx_l2l1()
145 spin_lock_irqsave(&bcs->cs->lock, flags); hscx_l2l1()
149 spin_unlock_irqrestore(&bcs->cs->lock, flags); hscx_l2l1()
175 open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs) open_hscxstate() argument
218 clear_pending_hscx_ints(struct IsdnCardState *cs) clear_pending_hscx_ints() argument
222 val = cs->BC_Read_Reg(cs, 1, HSCX_ISTA); clear_pending_hscx_ints()
223 debugl1(cs, "HSCX B ISTA %x", val); clear_pending_hscx_ints()
225 eval = cs->BC_Read_Reg(cs, 1, HSCX_EXIR); clear_pending_hscx_ints()
226 debugl1(cs, "HSCX B EXIR %x", eval); clear_pending_hscx_ints()
229 eval = cs->BC_Read_Reg(cs, 0, HSCX_EXIR); clear_pending_hscx_ints()
230 debugl1(cs, "HSCX A EXIR %x", eval); clear_pending_hscx_ints()
232 val = cs->BC_Read_Reg(cs, 0, HSCX_ISTA); clear_pending_hscx_ints()
233 debugl1(cs, "HSCX A ISTA %x", val); clear_pending_hscx_ints()
234 val = cs->BC_Read_Reg(cs, 1, HSCX_STAR); clear_pending_hscx_ints()
235 debugl1(cs, "HSCX B STAR %x", val); clear_pending_hscx_ints()
236 val = cs->BC_Read_Reg(cs, 0, HSCX_STAR); clear_pending_hscx_ints()
237 debugl1(cs, "HSCX A STAR %x", val); clear_pending_hscx_ints()
239 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF); clear_pending_hscx_ints()
240 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF); clear_pending_hscx_ints()
244 inithscx(struct IsdnCardState *cs) inithscx() argument
246 cs->bcs[0].BC_SetStack = setstack_hscx; inithscx()
247 cs->bcs[1].BC_SetStack = setstack_hscx; inithscx()
248 cs->bcs[0].BC_Close = close_hscxstate; inithscx()
249 cs->bcs[1].BC_Close = close_hscxstate; inithscx()
250 cs->bcs[0].hw.hscx.hscx = 0; inithscx()
251 cs->bcs[1].hw.hscx.hscx = 1; inithscx()
252 cs->bcs[0].hw.hscx.tsaxr0 = 0x2f; inithscx()
253 cs->bcs[0].hw.hscx.tsaxr1 = 3; inithscx()
254 cs->bcs[1].hw.hscx.tsaxr0 = 0x2f; inithscx()
255 cs->bcs[1].hw.hscx.tsaxr1 = 3; inithscx()
256 modehscx(cs->bcs, 0, 0); inithscx()
257 modehscx(cs->bcs + 1, 0, 0); inithscx()
261 inithscxisac(struct IsdnCardState *cs, int part) inithscxisac() argument
264 clear_pending_isac_ints(cs); inithscxisac()
265 clear_pending_hscx_ints(cs); inithscxisac()
266 initisac(cs); inithscxisac()
267 inithscx(cs); inithscxisac()
271 cs->writeisac(cs, ISAC_MASK, 0); inithscxisac()
272 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0); inithscxisac()
273 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0); inithscxisac()
275 cs->writeisac(cs, ISAC_CMDR, 0x41); inithscxisac()
|
| H A D | hfc_sx.c | 62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); Read_hfc()
83 fifo_select(struct IsdnCardState *cs, u_char fifo) fifo_select() argument
85 if (fifo == cs->hw.hfcsx.last_fifo) fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); fifo_select()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ fifo_select()
101 reset_fifo(struct IsdnCardState *cs, u_char fifo) reset_fifo() argument
103 fifo_select(cs, fifo); /* first select the fifo */ reset_fifo()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ reset_fifo()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ reset_fifo()
117 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) write_fifo() argument
126 fifo_select(cs, fifo); write_fifo()
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ write_fifo()
137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); write_fifo()
138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); write_fifo()
142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); write_fifo()
143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); write_fifo()
153 Write_hfc(cs, HFCSX_FIF_DWR, *src++); write_fifo()
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; write_fifo()
159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; write_fifo()
160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; write_fifo()
166 if (cs->debug & L1_DEB_ISAC_FIFO) write_fifo()
167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1); write_fifo()
173 if (cs->debug & L1_DEB_ISAC_FIFO) write_fifo()
174 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)", write_fifo()
181 if (cs->debug & L1_DEB_ISAC_FIFO) write_fifo()
182 debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)", write_fifo()
185 if (cs->debug & L1_DEB_ISAC_FIFO) write_fifo()
186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); write_fifo()
193 Write_hfc(cs, HFCSX_FIF_DWR, *src++); write_fifo()
195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ write_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ write_fifo()
207 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) read_fifo() argument
213 fifo_select(cs, fifo); read_fifo()
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ read_fifo()
226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); read_fifo()
227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); read_fifo()
228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); read_fifo()
229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); read_fifo()
241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); read_fifo()
248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; read_fifo()
249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; read_fifo()
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); read_fifo()
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); read_fifo()
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); read_fifo()
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); read_fifo()
258 if (cs->debug & L1_DEB_ISAC_FIFO) read_fifo()
259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)", read_fifo()
267 if (cs->debug & L1_DEB_ISAC_FIFO) read_fifo()
268 debugl1(cs, "hfcsx_read_fifo %d count %u)", read_fifo()
272 if (cs->debug & L1_DEB_WARN) read_fifo()
273 debugl1(cs, "hfcsx_read_fifo %d packet inv. len %d ", fifo , count); read_fifo()
276 Read_hfc(cs, HFCSX_FIF_DRD); read_fifo()
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); read_fifo()
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */ read_fifo()
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */ read_fifo()
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) { read_fifo()
291 if (cs->debug & L1_DEB_ISAC_FIFO) read_fifo()
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); read_fifo()
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ read_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ read_fifo()
312 release_io_hfcsx(struct IsdnCardState *cs) release_io_hfcsx() argument
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ release_io_hfcsx()
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); release_io_hfcsx()
316 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ release_io_hfcsx()
318 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ release_io_hfcsx()
319 del_timer(&cs->hw.hfcsx.timer); release_io_hfcsx()
320 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ release_io_hfcsx()
321 kfree(cs->hw.hfcsx.extra); release_io_hfcsx()
322 cs->hw.hfcsx.extra = NULL; release_io_hfcsx()
329 static int set_fifo_size(struct IsdnCardState *cs) set_fifo_size() argument
332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */ set_fifo_size()
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { set_fifo_size()
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; set_fifo_size()
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; set_fifo_size()
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ set_fifo_size()
350 reset_hfcsx(struct IsdnCardState *cs) reset_hfcsx() argument
352 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ reset_hfcsx()
353 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); reset_hfcsx()
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */ reset_hfcsx()
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ reset_hfcsx()
361 if (Read_hfc(cs, HFCSX_STATUS) & 2) reset_hfcsx()
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ reset_hfcsx()
364 if (!set_fifo_size(cs)) continue; reset_hfcsx()
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ reset_hfcsx()
369 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); reset_hfcsx()
371 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ reset_hfcsx()
372 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; reset_hfcsx()
373 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ reset_hfcsx()
374 cs->hw.hfcsx.bswapped = 0; /* no exchange */ reset_hfcsx()
375 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ reset_hfcsx()
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; reset_hfcsx()
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); reset_hfcsx()
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | reset_hfcsx()
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); reset_hfcsx()
384 if (Read_hfc(cs, HFCSX_INT_S1)); reset_hfcsx()
386 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ reset_hfcsx()
388 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ reset_hfcsx()
389 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ reset_hfcsx()
391 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); reset_hfcsx()
392 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ reset_hfcsx()
393 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); reset_hfcsx()
394 cs->hw.hfcsx.sctrl_r = 0; reset_hfcsx()
395 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); reset_hfcsx()
404 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ reset_hfcsx()
405 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); reset_hfcsx()
406 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ reset_hfcsx()
407 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ reset_hfcsx()
408 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ reset_hfcsx()
409 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ reset_hfcsx()
412 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; reset_hfcsx()
413 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); reset_hfcsx()
414 if (Read_hfc(cs, HFCSX_INT_S2)); reset_hfcsx()
421 hfcsx_Timer(struct IsdnCardState *cs) hfcsx_Timer() argument
423 cs->hw.hfcsx.timer.expires = jiffies + 75; hfcsx_Timer()
425 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80); hfcsx_Timer()
426 add_timer(&cs->hw.hfcsx.timer); hfcsx_Timer()
435 Sel_BCS(struct IsdnCardState *cs, int channel) Sel_BCS() argument
437 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) Sel_BCS()
438 return (&cs->bcs[0]); Sel_BCS()
439 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) Sel_BCS()
440 return (&cs->bcs[1]); Sel_BCS()
450 receive_dmsg(struct IsdnCardState *cs) receive_dmsg() argument
455 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { receive_dmsg()
456 debugl1(cs, "rec_dmsg blocked"); receive_dmsg()
461 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); receive_dmsg()
463 skb_queue_tail(&cs->rq, skb); receive_dmsg()
464 schedule_event(cs, D_RCVBUFREADY); receive_dmsg()
468 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); receive_dmsg()
478 struct IsdnCardState *cs = bcs->cs; main_rec_hfcsx() local
484 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { main_rec_hfcsx()
485 debugl1(cs, "rec_data %d blocked", bcs->channel); main_rec_hfcsx()
488 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? main_rec_hfcsx()
498 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); main_rec_hfcsx()
508 hfcsx_fill_dfifo(struct IsdnCardState *cs) hfcsx_fill_dfifo() argument
510 if (!cs->tx_skb) hfcsx_fill_dfifo()
512 if (cs->tx_skb->len <= 0) hfcsx_fill_dfifo()
515 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { hfcsx_fill_dfifo()
516 dev_kfree_skb_any(cs->tx_skb); hfcsx_fill_dfifo()
517 cs->tx_skb = NULL; hfcsx_fill_dfifo()
528 struct IsdnCardState *cs = bcs->cs; hfcsx_fill_fifo() local
535 if (write_fifo(cs, bcs->tx_skb, hfcsx_fill_fifo()
536 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? hfcsx_fill_fifo()
562 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; dch_nt_l2l1() local
575 debugl1(cs, "PH_TEST_LOOP B1"); dch_nt_l2l1()
577 debugl1(cs, "PH_TEST_LOOP B2"); dch_nt_l2l1()
579 debugl1(cs, "PH_TEST_LOOP DISABLED"); dch_nt_l2l1()
583 if (cs->debug) dch_nt_l2l1()
584 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); dch_nt_l2l1()
595 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) hfcsx_auxcmd() argument
601 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) { hfcsx_auxcmd()
602 spin_lock_irqsave(&cs->lock, flags); hfcsx_auxcmd()
603 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ hfcsx_auxcmd()
605 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; hfcsx_auxcmd()
606 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ hfcsx_auxcmd()
608 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ hfcsx_auxcmd()
610 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); hfcsx_auxcmd()
611 cs->dc.hfcsx.ph_state = 1; hfcsx_auxcmd()
612 cs->hw.hfcsx.nt_mode = 1; hfcsx_auxcmd()
613 cs->hw.hfcsx.nt_timer = 0; hfcsx_auxcmd()
614 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_auxcmd()
615 cs->stlist->l2.l2l1 = dch_nt_l2l1; hfcsx_auxcmd()
616 debugl1(cs, "NT mode activated"); hfcsx_auxcmd()
619 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || hfcsx_auxcmd()
620 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) hfcsx_auxcmd()
624 cs->logecho = 1; hfcsx_auxcmd()
625 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ hfcsx_auxcmd()
626 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; hfcsx_auxcmd()
629 cs->logecho = 0; hfcsx_auxcmd()
630 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ hfcsx_auxcmd()
631 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; hfcsx_auxcmd()
633 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; hfcsx_auxcmd()
634 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; hfcsx_auxcmd()
635 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ hfcsx_auxcmd()
636 cs->hw.hfcsx.ctmt &= ~2; hfcsx_auxcmd()
637 spin_lock_irqsave(&cs->lock, flags); hfcsx_auxcmd()
638 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); hfcsx_auxcmd()
639 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); hfcsx_auxcmd()
640 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); hfcsx_auxcmd()
641 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); hfcsx_auxcmd()
642 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); hfcsx_auxcmd()
643 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_auxcmd()
644 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_auxcmd()
652 receive_emsg(struct IsdnCardState *cs) receive_emsg() argument
658 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { receive_emsg()
659 debugl1(cs, "echo_rec_data blocked"); receive_emsg()
663 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); receive_emsg()
665 if (cs->debug & DEB_DLOG_HEX) { receive_emsg()
666 ptr = cs->dlog; receive_emsg()
677 HiSax_putstatus(cs, NULL, "%s", cs->dlog); receive_emsg()
679 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); receive_emsg()
685 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); receive_emsg()
696 struct IsdnCardState *cs = dev_id; hfcsx_interrupt() local
703 if (!(cs->hw.hfcsx.int_m2 & 0x08)) hfcsx_interrupt()
706 spin_lock_irqsave(&cs->lock, flags); hfcsx_interrupt()
707 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) { hfcsx_interrupt()
708 val = Read_hfc(cs, HFCSX_INT_S1); hfcsx_interrupt()
709 if (cs->debug & L1_DEB_ISAC) hfcsx_interrupt()
710 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val); hfcsx_interrupt()
712 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_interrupt()
715 if (cs->debug & L1_DEB_ISAC) hfcsx_interrupt()
716 debugl1(cs, "HFC-SX irq %x %s", val, hfcsx_interrupt()
717 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? hfcsx_interrupt()
719 val &= cs->hw.hfcsx.int_m1; hfcsx_interrupt()
721 exval = Read_hfc(cs, HFCSX_STATES) & 0xf; hfcsx_interrupt()
722 if (cs->debug & L1_DEB_ISAC) hfcsx_interrupt()
723 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, hfcsx_interrupt()
725 cs->dc.hfcsx.ph_state = exval; hfcsx_interrupt()
726 schedule_event(cs, D_L1STATECHANGE); hfcsx_interrupt()
730 if (cs->hw.hfcsx.nt_mode) { hfcsx_interrupt()
731 if ((--cs->hw.hfcsx.nt_timer) < 0) hfcsx_interrupt()
732 schedule_event(cs, D_L1STATECHANGE); hfcsx_interrupt()
735 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_interrupt()
738 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
739 cs->hw.hfcsx.int_s1 |= val; hfcsx_interrupt()
740 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_interrupt()
743 if (cs->hw.hfcsx.int_s1 & 0x18) { hfcsx_interrupt()
745 val = cs->hw.hfcsx.int_s1; hfcsx_interrupt()
746 cs->hw.hfcsx.int_s1 = exval; hfcsx_interrupt()
749 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { hfcsx_interrupt()
750 if (cs->debug) hfcsx_interrupt()
751 debugl1(cs, "hfcsx spurious 0x08 IRQ"); hfcsx_interrupt()
756 if (cs->logecho) hfcsx_interrupt()
757 receive_emsg(cs); hfcsx_interrupt()
758 else if (!(bcs = Sel_BCS(cs, 1))) { hfcsx_interrupt()
759 if (cs->debug) hfcsx_interrupt()
760 debugl1(cs, "hfcsx spurious 0x10 IRQ"); hfcsx_interrupt()
765 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { hfcsx_interrupt()
766 if (cs->debug) hfcsx_interrupt()
767 debugl1(cs, "hfcsx spurious 0x01 IRQ"); hfcsx_interrupt()
770 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
772 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
774 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcsx_interrupt()
777 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
779 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
781 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcsx_interrupt()
789 if (!(bcs = Sel_BCS(cs, 1))) { hfcsx_interrupt()
790 if (cs->debug) hfcsx_interrupt()
791 debugl1(cs, "hfcsx spurious 0x02 IRQ"); hfcsx_interrupt()
794 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
796 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
798 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcsx_interrupt()
801 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
803 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
805 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcsx_interrupt()
813 receive_dmsg(cs); hfcsx_interrupt()
816 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) hfcsx_interrupt()
817 del_timer(&cs->dbusytimer); hfcsx_interrupt()
818 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) hfcsx_interrupt()
819 schedule_event(cs, D_CLEARBUSY); hfcsx_interrupt()
820 if (cs->tx_skb) { hfcsx_interrupt()
821 if (cs->tx_skb->len) { hfcsx_interrupt()
822 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
823 hfcsx_fill_dfifo(cs); hfcsx_interrupt()
824 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
826 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); hfcsx_interrupt()
830 dev_kfree_skb_irq(cs->tx_skb); hfcsx_interrupt()
831 cs->tx_cnt = 0; hfcsx_interrupt()
832 cs->tx_skb = NULL; hfcsx_interrupt()
835 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { hfcsx_interrupt()
836 cs->tx_cnt = 0; hfcsx_interrupt()
837 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_interrupt()
838 hfcsx_fill_dfifo(cs); hfcsx_interrupt()
839 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_interrupt()
841 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); hfcsx_interrupt()
844 schedule_event(cs, D_XMTBUFREADY); hfcsx_interrupt()
847 if (cs->hw.hfcsx.int_s1 && count--) { hfcsx_interrupt()
848 val = cs->hw.hfcsx.int_s1; hfcsx_interrupt()
849 cs->hw.hfcsx.int_s1 = 0; hfcsx_interrupt()
850 if (cs->debug & L1_DEB_ISAC) hfcsx_interrupt()
851 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count); hfcsx_interrupt()
855 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_interrupt()
863 hfcsx_dbusy_timer(struct IsdnCardState *cs) hfcsx_dbusy_timer() argument
873 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; HFCSX_l1hw() local
879 if (cs->debug & DEB_DLOG_HEX) HFCSX_l1hw()
880 LogFrame(cs, skb->data, skb->len); HFCSX_l1hw()
881 if (cs->debug & DEB_DLOG_VERBOSE) HFCSX_l1hw()
882 dlogframe(cs, skb, 0); HFCSX_l1hw()
883 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
884 if (cs->tx_skb) { HFCSX_l1hw()
885 skb_queue_tail(&cs->sq, skb); HFCSX_l1hw()
887 if (cs->debug & L1_DEB_LAPD) HFCSX_l1hw()
888 Logl2Frame(cs, skb, "PH_DATA Queued", 0); HFCSX_l1hw()
891 cs->tx_skb = skb; HFCSX_l1hw()
892 cs->tx_cnt = 0; HFCSX_l1hw()
894 if (cs->debug & L1_DEB_LAPD) HFCSX_l1hw()
895 Logl2Frame(cs, skb, "PH_DATA", 0); HFCSX_l1hw()
897 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCSX_l1hw()
898 hfcsx_fill_dfifo(cs); HFCSX_l1hw()
899 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCSX_l1hw()
901 debugl1(cs, "hfcsx_fill_dfifo blocked"); HFCSX_l1hw()
904 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
907 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
908 if (cs->tx_skb) { HFCSX_l1hw()
909 if (cs->debug & L1_DEB_WARN) HFCSX_l1hw()
910 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); HFCSX_l1hw()
911 skb_queue_tail(&cs->sq, skb); HFCSX_l1hw()
912 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
915 if (cs->debug & DEB_DLOG_HEX) HFCSX_l1hw()
916 LogFrame(cs, skb->data, skb->len); HFCSX_l1hw()
917 if (cs->debug & DEB_DLOG_VERBOSE) HFCSX_l1hw()
918 dlogframe(cs, skb, 0); HFCSX_l1hw()
919 cs->tx_skb = skb; HFCSX_l1hw()
920 cs->tx_cnt = 0; HFCSX_l1hw()
922 if (cs->debug & L1_DEB_LAPD) HFCSX_l1hw()
923 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); HFCSX_l1hw()
925 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCSX_l1hw()
926 hfcsx_fill_dfifo(cs); HFCSX_l1hw()
927 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCSX_l1hw()
929 debugl1(cs, "hfcsx_fill_dfifo blocked"); HFCSX_l1hw()
930 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
934 if (cs->debug & L1_DEB_LAPD) HFCSX_l1hw()
935 debugl1(cs, "-> PH_REQUEST_PULL"); HFCSX_l1hw()
937 if (!cs->tx_skb) { HFCSX_l1hw()
944 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
945 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ HFCSX_l1hw()
947 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ HFCSX_l1hw()
948 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; HFCSX_l1hw()
949 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
950 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); HFCSX_l1hw()
951 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
952 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); HFCSX_l1hw()
955 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
956 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); HFCSX_l1hw()
957 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
960 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
961 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; HFCSX_l1hw()
962 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
963 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
966 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
967 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; HFCSX_l1hw()
968 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); HFCSX_l1hw()
969 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
972 spin_lock_irqsave(&cs->lock, flags); HFCSX_l1hw()
975 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ HFCSX_l1hw()
976 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ HFCSX_l1hw()
977 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; HFCSX_l1hw()
978 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); HFCSX_l1hw()
981 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ HFCSX_l1hw()
982 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ HFCSX_l1hw()
983 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; HFCSX_l1hw()
984 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); HFCSX_l1hw()
987 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
988 if (cs->debug & L1_DEB_WARN) HFCSX_l1hw()
989 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg); HFCSX_l1hw()
992 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ HFCSX_l1hw()
993 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); HFCSX_l1hw()
994 spin_unlock_irqrestore(&cs->lock, flags); HFCSX_l1hw()
997 if (cs->debug & L1_DEB_WARN) HFCSX_l1hw()
998 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); HFCSX_l1hw()
1007 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs) setstack_hfcsx() argument
1018 struct IsdnCardState *cs = bcs->cs; hfcsx_send_data() local
1020 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcsx_send_data()
1022 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcsx_send_data()
1024 debugl1(cs, "send_data %d blocked", bcs->channel); hfcsx_send_data()
1033 struct IsdnCardState *cs = bcs->cs; mode_hfcsx() local
1036 if (cs->debug & L1_DEB_HSCX) mode_hfcsx()
1037 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d", mode_hfcsx()
1042 if (cs->chanlimit > 1) { mode_hfcsx()
1043 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1044 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1048 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcsx()
1049 cs->hw.hfcsx.sctrl_e |= 0x80; mode_hfcsx()
1051 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1052 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1056 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcsx()
1057 cs->hw.hfcsx.sctrl_e &= ~0x80; mode_hfcsx()
1063 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; mode_hfcsx()
1064 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; mode_hfcsx()
1066 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; mode_hfcsx()
1067 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; mode_hfcsx()
1070 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1072 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1077 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1078 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1080 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1081 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1084 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1085 cs->hw.hfcsx.ctmt |= 2; mode_hfcsx()
1086 cs->hw.hfcsx.conn &= ~0x18; mode_hfcsx()
1088 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1089 cs->hw.hfcsx.ctmt |= 1; mode_hfcsx()
1090 cs->hw.hfcsx.conn &= ~0x03; mode_hfcsx()
1095 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1096 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1098 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1099 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1102 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1103 cs->hw.hfcsx.ctmt &= ~2; mode_hfcsx()
1104 cs->hw.hfcsx.conn &= ~0x18; mode_hfcsx()
1106 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1107 cs->hw.hfcsx.ctmt &= ~1; mode_hfcsx()
1108 cs->hw.hfcsx.conn &= ~0x03; mode_hfcsx()
1113 cs->hw.hfcsx.conn |= 0x10; mode_hfcsx()
1114 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; mode_hfcsx()
1115 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; mode_hfcsx()
1116 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); mode_hfcsx()
1118 cs->hw.hfcsx.conn |= 0x02; mode_hfcsx()
1119 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; mode_hfcsx()
1120 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; mode_hfcsx()
1121 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); mode_hfcsx()
1125 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); mode_hfcsx()
1126 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); mode_hfcsx()
1127 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); mode_hfcsx()
1128 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); mode_hfcsx()
1129 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); mode_hfcsx()
1130 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); mode_hfcsx()
1132 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); mode_hfcsx()
1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); mode_hfcsx()
1149 spin_lock_irqsave(&bcs->cs->lock, flags); hfcsx_l2l1()
1155 bcs->cs->BC_Send_Data(bcs); hfcsx_l2l1()
1157 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcsx_l2l1()
1160 spin_lock_irqsave(&bcs->cs->lock, flags); hfcsx_l2l1()
1167 bcs->cs->BC_Send_Data(bcs); hfcsx_l2l1()
1169 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcsx_l2l1()
1179 spin_lock_irqsave(&bcs->cs->lock, flags); hfcsx_l2l1()
1182 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcsx_l2l1()
1189 spin_lock_irqsave(&bcs->cs->lock, flags); hfcsx_l2l1()
1193 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcsx_l2l1()
1221 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs) open_hfcsxstate() argument
1257 struct IsdnCardState *cs = hfcsx_bh() local
1261 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { hfcsx_bh()
1262 if (!cs->hw.hfcsx.nt_mode) hfcsx_bh()
1263 switch (cs->dc.hfcsx.ph_state) { hfcsx_bh()
1265 l1_msg(cs, HW_RESET | INDICATION, NULL); hfcsx_bh()
1268 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); hfcsx_bh()
1271 l1_msg(cs, HW_RSYNC | INDICATION, NULL); hfcsx_bh()
1274 l1_msg(cs, HW_INFO2 | INDICATION, NULL); hfcsx_bh()
1277 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); hfcsx_bh()
1282 switch (cs->dc.hfcsx.ph_state) { hfcsx_bh()
1284 spin_lock_irqsave(&cs->lock, flags); hfcsx_bh()
1285 if (cs->hw.hfcsx.nt_timer < 0) { hfcsx_bh()
1286 cs->hw.hfcsx.nt_timer = 0; hfcsx_bh()
1287 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_bh()
1288 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1290 if (Read_hfc(cs, HFCSX_INT_S1)); hfcsx_bh()
1292 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); hfcsx_bh()
1294 Write_hfc(cs, HFCSX_STATES, 4); hfcsx_bh()
1295 cs->dc.hfcsx.ph_state = 4; hfcsx_bh()
1297 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; hfcsx_bh()
1298 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1299 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; hfcsx_bh()
1300 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; hfcsx_bh()
1301 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_bh()
1302 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); hfcsx_bh()
1303 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; hfcsx_bh()
1304 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ hfcsx_bh()
1306 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_bh()
1311 spin_lock_irqsave(&cs->lock, flags); hfcsx_bh()
1312 cs->hw.hfcsx.nt_timer = 0; hfcsx_bh()
1313 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_bh()
1314 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_bh()
1315 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_bh()
1322 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) hfcsx_bh()
1323 DChannel_proc_rcv(cs); hfcsx_bh()
1324 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) hfcsx_bh()
1325 DChannel_proc_xmt(cs); hfcsx_bh()
1332 static void inithfcsx(struct IsdnCardState *cs) inithfcsx() argument
1334 cs->setstack_d = setstack_hfcsx; inithfcsx()
1335 cs->BC_Send_Data = &hfcsx_send_data; inithfcsx()
1336 cs->bcs[0].BC_SetStack = setstack_2b; inithfcsx()
1337 cs->bcs[1].BC_SetStack = setstack_2b; inithfcsx()
1338 cs->bcs[0].BC_Close = close_hfcsx; inithfcsx()
1339 cs->bcs[1].BC_Close = close_hfcsx; inithfcsx()
1340 mode_hfcsx(cs->bcs, 0, 0); inithfcsx()
1341 mode_hfcsx(cs->bcs + 1, 0, 1); inithfcsx()
1350 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg) hfcsx_card_msg() argument
1354 if (cs->debug & L1_DEB_ISAC) hfcsx_card_msg()
1355 debugl1(cs, "HFCSX: card_msg %x", mt); hfcsx_card_msg()
1358 spin_lock_irqsave(&cs->lock, flags); hfcsx_card_msg()
1359 reset_hfcsx(cs); hfcsx_card_msg()
1360 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_card_msg()
1363 release_io_hfcsx(cs); hfcsx_card_msg()
1366 spin_lock_irqsave(&cs->lock, flags); hfcsx_card_msg()
1367 inithfcsx(cs); hfcsx_card_msg()
1368 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_card_msg()
1371 spin_lock_irqsave(&cs->lock, flags); hfcsx_card_msg()
1372 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; hfcsx_card_msg()
1373 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); hfcsx_card_msg()
1375 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); hfcsx_card_msg()
1376 spin_unlock_irqrestore(&cs->lock, flags); hfcsx_card_msg()
1398 struct IsdnCardState *cs = card->cs; setup_hfcsx() local
1445 cs->hw.hfcsx.base = card->para[1] & 0xfffe; setup_hfcsx()
1446 cs->irq = card->para[0]; setup_hfcsx()
1447 cs->hw.hfcsx.int_s1 = 0; setup_hfcsx()
1448 cs->dc.hfcsx.ph_state = 0; setup_hfcsx()
1449 cs->hw.hfcsx.fifo = 255; setup_hfcsx()
1450 if ((cs->typ == ISDN_CTYPE_HFC_SX) || setup_hfcsx()
1451 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { setup_hfcsx()
1452 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { setup_hfcsx()
1455 cs->hw.hfcsx.base); setup_hfcsx()
1458 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); setup_hfcsx()
1459 byteout(cs->hw.hfcsx.base + 1, setup_hfcsx()
1460 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); setup_hfcsx()
1462 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID); setup_hfcsx()
1463 switch (cs->hw.hfcsx.chip >> 4) { setup_hfcsx()
1473 cs->hw.hfcsx.chip >> 4); setup_hfcsx()
1474 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1477 if (!ccd_sp_irqtab[cs->irq & 0xF]) { setup_hfcsx()
1479 "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF); setup_hfcsx()
1480 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1483 if (!(cs->hw.hfcsx.extra = setup_hfcsx()
1485 release_region(cs->hw.hfcsx.base, 2); setup_hfcsx()
1490 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); setup_hfcsx()
1491 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ setup_hfcsx()
1492 cs->hw.hfcsx.int_m1 = 0; setup_hfcsx()
1493 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); setup_hfcsx()
1494 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); setup_hfcsx()
1498 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer; setup_hfcsx()
1499 cs->dbusytimer.data = (long) cs; setup_hfcsx()
1500 init_timer(&cs->dbusytimer); setup_hfcsx()
1501 INIT_WORK(&cs->tqueue, hfcsx_bh); setup_hfcsx()
1502 cs->readisac = NULL; setup_hfcsx()
1503 cs->writeisac = NULL; setup_hfcsx()
1504 cs->readisacfifo = NULL; setup_hfcsx()
1505 cs->writeisacfifo = NULL; setup_hfcsx()
1506 cs->BC_Read_Reg = NULL; setup_hfcsx()
1507 cs->BC_Write_Reg = NULL; setup_hfcsx()
1508 cs->irq_func = &hfcsx_interrupt; setup_hfcsx()
1510 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; setup_hfcsx()
1511 cs->hw.hfcsx.timer.data = (long) cs; setup_hfcsx()
1512 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ setup_hfcsx()
1513 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ setup_hfcsx()
1514 init_timer(&cs->hw.hfcsx.timer); setup_hfcsx()
1516 reset_hfcsx(cs); setup_hfcsx()
1517 cs->cardmsg = &hfcsx_card_msg; setup_hfcsx()
1518 cs->auxcmd = &hfcsx_auxcmd; setup_hfcsx()
|
| H A D | w6692.c | 51 W6692Version(struct IsdnCardState *cs, char *s) W6692Version() argument
55 val = cs->readW6692(cs, W_D_RBCH); W6692Version()
60 ph_command(struct IsdnCardState *cs, unsigned int command) ph_command() argument
62 if (cs->debug & L1_DEB_ISAC) ph_command()
63 debugl1(cs, "ph_command %x", command); ph_command()
64 cs->writeisac(cs, W_CIX, command); ph_command()
69 W6692_new_ph(struct IsdnCardState *cs) W6692_new_ph() argument
71 switch (cs->dc.w6692.ph_state) { W6692_new_ph()
73 ph_command(cs, W_L1CMD_DRC); W6692_new_ph()
74 l1_msg(cs, HW_RESET | INDICATION, NULL); W6692_new_ph()
77 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); W6692_new_ph()
80 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); W6692_new_ph()
83 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); W6692_new_ph()
86 l1_msg(cs, HW_RSYNC | INDICATION, NULL); W6692_new_ph()
89 l1_msg(cs, HW_INFO2 | INDICATION, NULL); W6692_new_ph()
92 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); W6692_new_ph()
95 l1_msg(cs, HW_INFO4_P10 | INDICATION, NULL); W6692_new_ph()
105 struct IsdnCardState *cs = W6692_bh() local
109 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { W6692_bh()
110 if (cs->debug) W6692_bh()
111 debugl1(cs, "D-Channel Busy cleared"); W6692_bh()
112 stptr = cs->stlist; W6692_bh()
118 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) W6692_bh()
119 W6692_new_ph(cs); W6692_bh()
120 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) W6692_bh()
121 DChannel_proc_rcv(cs); W6692_bh()
122 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) W6692_bh()
123 DChannel_proc_xmt(cs); W6692_bh()
125 if (test_and_clear_bit(D_RX_MON1, &cs->event)) W6692_bh()
126 arcofi_fsm(cs, ARCOFI_RX_END, NULL); W6692_bh()
127 if (test_and_clear_bit(D_TX_MON1, &cs->event)) W6692_bh()
128 arcofi_fsm(cs, ARCOFI_TX_END, NULL); W6692_bh()
133 W6692_empty_fifo(struct IsdnCardState *cs, int count) W6692_empty_fifo() argument
137 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) W6692_empty_fifo()
138 debugl1(cs, "W6692_empty_fifo"); W6692_empty_fifo()
140 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { W6692_empty_fifo()
141 if (cs->debug & L1_DEB_WARN) W6692_empty_fifo()
142 debugl1(cs, "W6692_empty_fifo overrun %d", W6692_empty_fifo()
143 cs->rcvidx + count); W6692_empty_fifo()
144 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK); W6692_empty_fifo()
145 cs->rcvidx = 0; W6692_empty_fifo()
148 ptr = cs->rcvbuf + cs->rcvidx; W6692_empty_fifo()
149 cs->rcvidx += count; W6692_empty_fifo()
150 cs->readW6692fifo(cs, ptr, count); W6692_empty_fifo()
151 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK); W6692_empty_fifo()
152 if (cs->debug & L1_DEB_ISAC_FIFO) { W6692_empty_fifo()
153 char *t = cs->dlog; W6692_empty_fifo()
157 debugl1(cs, "%s", cs->dlog); W6692_empty_fifo()
162 W6692_fill_fifo(struct IsdnCardState *cs) W6692_fill_fifo() argument
167 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) W6692_fill_fifo()
168 debugl1(cs, "W6692_fill_fifo"); W6692_fill_fifo()
170 if (!cs->tx_skb) W6692_fill_fifo()
173 count = cs->tx_skb->len; W6692_fill_fifo()
182 ptr = cs->tx_skb->data; W6692_fill_fifo()
183 skb_pull(cs->tx_skb, count); W6692_fill_fifo()
184 cs->tx_cnt += count; W6692_fill_fifo()
185 cs->writeW6692fifo(cs, ptr, count); W6692_fill_fifo()
186 cs->writeW6692(cs, W_D_CMDR, more ? W_D_CMDR_XMS : (W_D_CMDR_XMS | W_D_CMDR_XME)); W6692_fill_fifo()
187 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { W6692_fill_fifo()
188 debugl1(cs, "W6692_fill_fifo dbusytimer running"); W6692_fill_fifo()
189 del_timer(&cs->dbusytimer); W6692_fill_fifo()
191 init_timer(&cs->dbusytimer); W6692_fill_fifo()
192 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ) / 1000); W6692_fill_fifo()
193 add_timer(&cs->dbusytimer); W6692_fill_fifo()
194 if (cs->debug & L1_DEB_ISAC_FIFO) { W6692_fill_fifo()
195 char *t = cs->dlog; W6692_fill_fifo()
199 debugl1(cs, "%s", cs->dlog); W6692_fill_fifo()
207 struct IsdnCardState *cs = bcs->cs; W6692B_empty_fifo() local
209 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) W6692B_empty_fifo()
210 debugl1(cs, "W6692B_empty_fifo"); W6692B_empty_fifo()
213 if (cs->debug & L1_DEB_WARN) W6692B_empty_fifo()
214 debugl1(cs, "W6692B_empty_fifo: incoming packet too large"); W6692B_empty_fifo()
215 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); W6692B_empty_fifo()
221 READW6692BFIFO(cs, bcs->channel, ptr, count); W6692B_empty_fifo()
222 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); W6692B_empty_fifo()
223 if (cs->debug & L1_DEB_HSCX_FIFO) { W6692B_empty_fifo()
229 debugl1(cs, "%s", bcs->blog); W6692B_empty_fifo()
236 struct IsdnCardState *cs = bcs->cs; W6692B_fill_fifo() local
252 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) W6692B_fill_fifo()
253 debugl1(cs, "W6692B_fill_fifo%s%d", (more ? " " : " last "), count); W6692B_fill_fifo()
259 WRITEW6692BFIFO(cs, bcs->channel, ptr, count); W6692B_fill_fifo()
260 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACT | W_B_CMDR_XMS | (more ? 0 : W_B_CMDR_XME)); W6692B_fill_fifo()
261 if (cs->debug & L1_DEB_HSCX_FIFO) { W6692B_fill_fifo()
267 debugl1(cs, "%s", bcs->blog); W6692B_fill_fifo()
272 W6692B_interrupt(struct IsdnCardState *cs, u_char bchan) W6692B_interrupt() argument
280 bcs = (cs->bcs->channel == bchan) ? cs->bcs : (cs->bcs + 1); W6692B_interrupt()
281 val = cs->BC_Read_Reg(cs, bchan, W_B_EXIR); W6692B_interrupt()
282 debugl1(cs, "W6692B chan %d B_EXIR 0x%02X", bchan, val); W6692B_interrupt()
285 debugl1(cs, "W6692B not INIT yet"); W6692B_interrupt()
289 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR); W6692B_interrupt()
291 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
292 debugl1(cs, "W6692 B STAR %x", r); W6692B_interrupt()
294 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
295 debugl1(cs, "W6692 B RDOV mode=%d", W6692B_interrupt()
298 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
299 debugl1(cs, "W6692 B CRC error"); W6692B_interrupt()
300 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT); W6692B_interrupt()
302 count = cs->BC_Read_Reg(cs, bchan, W_B_RBCL) & (W_B_FIFO_THRESH - 1); W6692B_interrupt()
307 if (cs->debug & L1_DEB_HSCX_FIFO) W6692B_interrupt()
308 debugl1(cs, "W6692 Bchan Frame %d", count); W6692B_interrupt()
322 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR); W6692B_interrupt()
324 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
325 debugl1(cs, "W6692 B RDOV(RMR) mode=%d", bcs->mode); W6692B_interrupt()
326 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT); W6692B_interrupt()
343 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT); W6692B_interrupt()
344 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
345 debugl1(cs, "W6692 B EXIR %x Lost TX", val); W6692B_interrupt()
361 r = cs->BC_Read_Reg(cs, bchan, W_B_STAR); W6692B_interrupt()
363 if (cs->debug & L1_DEB_WARN) W6692B_interrupt()
364 debugl1(cs, "W6692 B STAR %x XDOW", r); W6692B_interrupt()
365 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT); W6692B_interrupt()
404 struct IsdnCardState *cs = dev_id; W6692_interrupt() local
411 spin_lock_irqsave(&cs->lock, flags); W6692_interrupt()
412 val = cs->readW6692(cs, W_ISTA); W6692_interrupt()
414 spin_unlock_irqrestore(&cs->lock, flags); W6692_interrupt()
418 if (cs->debug & L1_DEB_ISAC) W6692_interrupt()
419 debugl1(cs, "W6692 ISTA %x", val); W6692_interrupt()
422 exval = cs->readW6692(cs, W_D_RSTA); W6692_interrupt()
425 if (cs->debug & L1_DEB_WARN) W6692_interrupt()
426 debugl1(cs, "W6692 RDOV"); W6692_interrupt()
428 if (cs->debug & L1_DEB_WARN) W6692_interrupt()
429 debugl1(cs, "W6692 D-channel CRC error"); W6692_interrupt()
431 if (cs->debug & L1_DEB_WARN) W6692_interrupt()
432 debugl1(cs, "W6692 D-channel ABORT"); W6692_interrupt()
433 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RACK | W_D_CMDR_RRST); W6692_interrupt()
435 count = cs->readW6692(cs, W_D_RBCL) & (W_D_FIFO_THRESH - 1); W6692_interrupt()
438 W6692_empty_fifo(cs, count); W6692_interrupt()
439 if ((count = cs->rcvidx) > 0) { W6692_interrupt()
440 cs->rcvidx = 0; W6692_interrupt()
444 memcpy(skb_put(skb, count), cs->rcvbuf, count); W6692_interrupt()
445 skb_queue_tail(&cs->rq, skb); W6692_interrupt()
449 cs->rcvidx = 0; W6692_interrupt()
450 schedule_event(cs, D_RCVBUFREADY); W6692_interrupt()
453 W6692_empty_fifo(cs, W_D_FIFO_THRESH); W6692_interrupt()
456 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) W6692_interrupt()
457 del_timer(&cs->dbusytimer); W6692_interrupt()
458 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) W6692_interrupt()
459 schedule_event(cs, D_CLEARBUSY); W6692_interrupt()
460 if (cs->tx_skb) { W6692_interrupt()
461 if (cs->tx_skb->len) { W6692_interrupt()
462 W6692_fill_fifo(cs); W6692_interrupt()
465 dev_kfree_skb_irq(cs->tx_skb); W6692_interrupt()
466 cs->tx_cnt = 0; W6692_interrupt()
467 cs->tx_skb = NULL; W6692_interrupt()
470 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { W6692_interrupt()
471 cs->tx_cnt = 0; W6692_interrupt()
472 W6692_fill_fifo(cs); W6692_interrupt()
474 schedule_event(cs, D_XMTBUFREADY); W6692_interrupt()
478 if (cs->debug & L1_DEB_ISAC) W6692_interrupt()
479 debugl1(cs, "W6692 spurious XINT!"); W6692_interrupt()
482 exval = cs->readW6692(cs, W_D_EXIR); W6692_interrupt()
483 if (cs->debug & L1_DEB_WARN) W6692_interrupt()
484 debugl1(cs, "W6692 D_EXIR %02x", exval); W6692_interrupt()
486 debugl1(cs, "W6692 D-chan underrun/collision"); W6692_interrupt()
488 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) W6692_interrupt()
489 del_timer(&cs->dbusytimer); W6692_interrupt()
490 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) W6692_interrupt()
491 schedule_event(cs, D_CLEARBUSY); W6692_interrupt()
492 if (cs->tx_skb) { /* Restart frame */ W6692_interrupt()
493 skb_push(cs->tx_skb, cs->tx_cnt); W6692_interrupt()
494 cs->tx_cnt = 0; W6692_interrupt()
495 W6692_fill_fifo(cs); W6692_interrupt()
498 debugl1(cs, "W6692 XDUN/XCOL no skb"); W6692_interrupt()
499 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_XRST); W6692_interrupt()
503 debugl1(cs, "W6692 D-channel RDOV"); W6692_interrupt()
505 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RRST); W6692_interrupt()
508 debugl1(cs, "W6692 spurious TIN2 interrupt"); W6692_interrupt()
511 debugl1(cs, "W6692 spurious MOC interrupt"); W6692_interrupt()
512 v1 = cs->readW6692(cs, W_MOSR); W6692_interrupt()
513 debugl1(cs, "W6692 MOSR %02x", v1); W6692_interrupt()
516 v1 = cs->readW6692(cs, W_CIR); W6692_interrupt()
517 if (cs->debug & L1_DEB_ISAC) W6692_interrupt()
518 debugl1(cs, "W6692 ISC CIR=0x%02X", v1); W6692_interrupt()
520 cs->dc.w6692.ph_state = v1 & W_CIR_COD_MASK; W6692_interrupt()
521 if (cs->debug & L1_DEB_ISAC) W6692_interrupt()
522 debugl1(cs, "ph_state_change %x", cs->dc.w6692.ph_state); W6692_interrupt()
523 schedule_event(cs, D_L1STATECHANGE); W6692_interrupt()
526 v1 = cs->readW6692(cs, W_SQR); W6692_interrupt()
527 debugl1(cs, "W6692 SCC SQR=0x%02X", v1); W6692_interrupt()
531 debugl1(cs, "W6692 spurious WEXP interrupt!"); W6692_interrupt()
534 debugl1(cs, "W6692 spurious TEXP interrupt!"); W6692_interrupt()
538 debugl1(cs, "W6692 B channel 1 interrupt"); W6692_interrupt()
539 W6692B_interrupt(cs, 0); W6692_interrupt()
542 debugl1(cs, "W6692 B channel 2 interrupt"); W6692_interrupt()
543 W6692B_interrupt(cs, 1); W6692_interrupt()
545 val = cs->readW6692(cs, W_ISTA); W6692_interrupt()
552 cs->writeW6692(cs, W_IMASK, 0xff); W6692_interrupt()
554 spin_unlock_irqrestore(&cs->lock, flags); W6692_interrupt()
561 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; W6692_l1hw() local
568 if (cs->debug & DEB_DLOG_HEX) W6692_l1hw()
569 LogFrame(cs, skb->data, skb->len); W6692_l1hw()
570 if (cs->debug & DEB_DLOG_VERBOSE) W6692_l1hw()
571 dlogframe(cs, skb, 0); W6692_l1hw()
572 spin_lock_irqsave(&cs->lock, flags); W6692_l1hw()
573 if (cs->tx_skb) { W6692_l1hw()
574 skb_queue_tail(&cs->sq, skb); W6692_l1hw()
576 if (cs->debug & L1_DEB_LAPD) W6692_l1hw()
577 Logl2Frame(cs, skb, "PH_DATA Queued", 0); W6692_l1hw()
580 cs->tx_skb = skb; W6692_l1hw()
581 cs->tx_cnt = 0; W6692_l1hw()
583 if (cs->debug & L1_DEB_LAPD) W6692_l1hw()
584 Logl2Frame(cs, skb, "PH_DATA", 0); W6692_l1hw()
586 W6692_fill_fifo(cs); W6692_l1hw()
588 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
591 spin_lock_irqsave(&cs->lock, flags); W6692_l1hw()
592 if (cs->tx_skb) { W6692_l1hw()
593 if (cs->debug & L1_DEB_WARN) W6692_l1hw()
594 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); W6692_l1hw()
595 skb_queue_tail(&cs->sq, skb); W6692_l1hw()
596 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
599 if (cs->debug & DEB_DLOG_HEX) W6692_l1hw()
600 LogFrame(cs, skb->data, skb->len); W6692_l1hw()
601 if (cs->debug & DEB_DLOG_VERBOSE) W6692_l1hw()
602 dlogframe(cs, skb, 0); W6692_l1hw()
603 cs->tx_skb = skb; W6692_l1hw()
604 cs->tx_cnt = 0; W6692_l1hw()
606 if (cs->debug & L1_DEB_LAPD) W6692_l1hw()
607 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); W6692_l1hw()
609 W6692_fill_fifo(cs); W6692_l1hw()
610 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
614 if (cs->debug & L1_DEB_LAPD) W6692_l1hw()
615 debugl1(cs, "-> PH_REQUEST_PULL"); W6692_l1hw()
617 if (!cs->tx_skb) { W6692_l1hw()
624 spin_lock_irqsave(&cs->lock, flags); W6692_l1hw()
625 if ((cs->dc.w6692.ph_state == W_L1IND_DRD)) { W6692_l1hw()
626 ph_command(cs, W_L1CMD_ECK); W6692_l1hw()
627 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
629 ph_command(cs, W_L1CMD_RST); W6692_l1hw()
630 cs->dc.w6692.ph_state = W_L1CMD_RST; W6692_l1hw()
631 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
632 W6692_new_ph(cs); W6692_l1hw()
636 spin_lock_irqsave(&cs->lock, flags); W6692_l1hw()
637 ph_command(cs, W_L1CMD_ECK); W6692_l1hw()
638 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
641 spin_lock_irqsave(&cs->lock, flags); W6692_l1hw()
642 ph_command(cs, W_L1CMD_AR8); W6692_l1hw()
643 spin_unlock_irqrestore(&cs->lock, flags); W6692_l1hw()
654 skb_queue_purge(&cs->rq); W6692_l1hw()
655 skb_queue_purge(&cs->sq); W6692_l1hw()
656 if (cs->tx_skb) { W6692_l1hw()
657 dev_kfree_skb_any(cs->tx_skb); W6692_l1hw()
658 cs->tx_skb = NULL; W6692_l1hw()
660 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) W6692_l1hw()
661 del_timer(&cs->dbusytimer); W6692_l1hw()
662 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) W6692_l1hw()
663 schedule_event(cs, D_CLEARBUSY); W6692_l1hw()
666 if (cs->debug & L1_DEB_WARN) W6692_l1hw()
667 debugl1(cs, "W6692_l1hw unknown %04x", pr); W6692_l1hw()
673 setstack_W6692(struct PStack *st, struct IsdnCardState *cs) setstack_W6692() argument
679 DC_Close_W6692(struct IsdnCardState *cs) DC_Close_W6692() argument
684 dbusy_timer_handler(struct IsdnCardState *cs) dbusy_timer_handler() argument
690 spin_lock_irqsave(&cs->lock, flags); dbusy_timer_handler()
691 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dbusy_timer_handler()
692 rbch = cs->readW6692(cs, W_D_RBCH); dbusy_timer_handler()
693 star = cs->readW6692(cs, W_D_STAR); dbusy_timer_handler()
694 if (cs->debug) dbusy_timer_handler()
695 debugl1(cs, "D-Channel Busy D_RBCH %02x D_STAR %02x", dbusy_timer_handler()
698 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags); dbusy_timer_handler()
699 stptr = cs->stlist; dbusy_timer_handler()
706 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); dbusy_timer_handler()
707 if (cs->tx_skb) { dbusy_timer_handler()
708 dev_kfree_skb_any(cs->tx_skb); dbusy_timer_handler()
709 cs->tx_cnt = 0; dbusy_timer_handler()
710 cs->tx_skb = NULL; dbusy_timer_handler()
713 debugl1(cs, "D-Channel Busy no skb"); dbusy_timer_handler()
715 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_XRST); /* Transmitter reset */ dbusy_timer_handler()
716 spin_unlock_irqrestore(&cs->lock, flags); dbusy_timer_handler()
717 cs->irq_func(cs->irq, cs); dbusy_timer_handler()
721 spin_unlock_irqrestore(&cs->lock, flags); dbusy_timer_handler()
727 struct IsdnCardState *cs = bcs->cs; W6692Bmode() local
729 if (cs->debug & L1_DEB_HSCX) W6692Bmode()
730 debugl1(cs, "w6692 %c mode %d ichan %d", W6692Bmode()
738 cs->BC_Write_Reg(cs, bchan, W_B_MODE, 0); W6692Bmode()
741 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_MMS); W6692Bmode()
744 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_ITF); W6692Bmode()
745 cs->BC_Write_Reg(cs, bchan, W_B_ADM1, 0xff); W6692Bmode()
746 cs->BC_Write_Reg(cs, bchan, W_B_ADM2, 0xff); W6692Bmode()
750 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RRST | W6692Bmode()
752 cs->BC_Write_Reg(cs, bchan, W_B_EXIM, 0x00); W6692Bmode()
764 spin_lock_irqsave(&bcs->cs->lock, flags); W6692_l2l1()
771 bcs->cs->BC_Send_Data(bcs); W6692_l2l1()
773 spin_unlock_irqrestore(&bcs->cs->lock, flags); W6692_l2l1()
780 spin_lock_irqsave(&bcs->cs->lock, flags); W6692_l2l1()
784 bcs->cs->BC_Send_Data(bcs); W6692_l2l1()
785 spin_unlock_irqrestore(&bcs->cs->lock, flags); W6692_l2l1()
795 spin_lock_irqsave(&bcs->cs->lock, flags); W6692_l2l1()
798 spin_unlock_irqrestore(&bcs->cs->lock, flags); W6692_l2l1()
805 spin_lock_irqsave(&bcs->cs->lock, flags); W6692_l2l1()
809 spin_unlock_irqrestore(&bcs->cs->lock, flags); W6692_l2l1()
835 open_w6692state(struct IsdnCardState *cs, struct BCState *bcs) open_w6692state() argument
877 static void resetW6692(struct IsdnCardState *cs) resetW6692() argument
879 cs->writeW6692(cs, W_D_CTL, W_D_CTL_SRST); resetW6692()
881 cs->writeW6692(cs, W_D_CTL, 0x00); resetW6692()
883 cs->writeW6692(cs, W_IMASK, 0xff); resetW6692()
884 cs->writeW6692(cs, W_D_SAM, 0xff); resetW6692()
885 cs->writeW6692(cs, W_D_TAM, 0xff); resetW6692()
886 cs->writeW6692(cs, W_D_EXIM, 0x00); resetW6692()
887 cs->writeW6692(cs, W_D_MODE, W_D_MODE_RACT); resetW6692()
888 cs->writeW6692(cs, W_IMASK, 0x18); resetW6692()
889 if (cs->subtyp == W6692_USR) { resetW6692()
894 cs->writeW6692(cs, W_PCTL, 0x80); resetW6692()
895 cs->writeW6692(cs, W_XDATA, 0x00); resetW6692()
899 static void initW6692(struct IsdnCardState *cs, int part) initW6692() argument
902 cs->setstack_d = setstack_W6692; initW6692()
903 cs->DC_Close = DC_Close_W6692; initW6692()
904 cs->dbusytimer.function = (void *) dbusy_timer_handler; initW6692()
905 cs->dbusytimer.data = (long) cs; initW6692()
906 init_timer(&cs->dbusytimer); initW6692()
907 resetW6692(cs); initW6692()
908 ph_command(cs, W_L1CMD_RST); initW6692()
909 cs->dc.w6692.ph_state = W_L1CMD_RST; initW6692()
910 W6692_new_ph(cs); initW6692()
911 ph_command(cs, W_L1CMD_ECK); initW6692()
913 cs->bcs[0].BC_SetStack = setstack_w6692; initW6692()
914 cs->bcs[1].BC_SetStack = setstack_w6692; initW6692()
915 cs->bcs[0].BC_Close = close_w6692state; initW6692()
916 cs->bcs[1].BC_Close = close_w6692state; initW6692()
917 W6692Bmode(cs->bcs, 0, 0); initW6692()
918 W6692Bmode(cs->bcs + 1, 0, 0); initW6692()
922 cs->writeW6692(cs, W_IMASK, 0x18); initW6692()
923 cs->writeW6692(cs, W_D_EXIM, 0x00); initW6692()
924 cs->BC_Write_Reg(cs, 0, W_B_EXIM, 0x00); initW6692()
925 cs->BC_Write_Reg(cs, 1, W_B_EXIM, 0x00); initW6692()
927 cs->writeW6692(cs, W_D_CMDR, W_D_CMDR_RRST | W_D_CMDR_XRST); initW6692()
934 ReadW6692(struct IsdnCardState *cs, u_char offset) ReadW6692() argument
936 return (inb(cs->hw.w6692.iobase + offset)); ReadW6692()
940 WriteW6692(struct IsdnCardState *cs, u_char offset, u_char value) WriteW6692() argument
942 outb(value, cs->hw.w6692.iobase + offset); WriteW6692()
946 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
948 insb(cs->hw.w6692.iobase + W_D_RFIFO, data, size); ReadISACfifo()
952 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
954 outsb(cs->hw.w6692.iobase + W_D_XFIFO, data, size); WriteISACfifo()
958 ReadW6692B(struct IsdnCardState *cs, int bchan, u_char offset) ReadW6692B() argument
960 return (inb(cs->hw.w6692.iobase + (bchan ? 0x40 : 0) + offset)); ReadW6692B()
964 WriteW6692B(struct IsdnCardState *cs, int bchan, u_char offset, u_char value) WriteW6692B() argument
966 outb(value, cs->hw.w6692.iobase + (bchan ? 0x40 : 0) + offset); WriteW6692B()
970 w6692_card_msg(struct IsdnCardState *cs, int mt, void *arg) w6692_card_msg() argument
974 resetW6692(cs); w6692_card_msg()
977 cs->writeW6692(cs, W_IMASK, 0xff); w6692_card_msg()
978 release_region(cs->hw.w6692.iobase, 256); w6692_card_msg()
979 if (cs->subtyp == W6692_USR) { w6692_card_msg()
980 cs->writeW6692(cs, W_XDATA, 0x04); w6692_card_msg()
984 initW6692(cs, 3); w6692_card_msg()
998 struct IsdnCardState *cs = card->cs; setup_w6692() local
1006 if (cs->typ != ISDN_CTYPE_W6692) setup_w6692()
1016 cs->subtyp = id_idx; setup_w6692()
1028 if (cs->subtyp == W6692_WINBOND) { setup_w6692()
1031 cs->subtyp = W6692_USR; setup_w6692()
1039 cs->irq = pci_irq; setup_w6692()
1040 if (!cs->irq) { setup_w6692()
1048 cs->hw.w6692.iobase = pci_ioaddr; setup_w6692()
1050 id_list[cs->subtyp].vendor_name, id_list[cs->subtyp].card_name, setup_w6692()
1052 if (!request_region(cs->hw.w6692.iobase, 256, id_list[cs->subtyp].card_name)) { setup_w6692()
1055 id_list[cs->subtyp].card_name, setup_w6692()
1056 cs->hw.w6692.iobase, setup_w6692()
1057 cs->hw.w6692.iobase + 255); setup_w6692()
1063 id_list[cs->subtyp].card_name, cs->irq, setup_w6692()
1064 cs->hw.w6692.iobase); setup_w6692()
1066 INIT_WORK(&cs->tqueue, W6692_bh); setup_w6692()
1067 cs->readW6692 = &ReadW6692; setup_w6692()
1068 cs->writeW6692 = &WriteW6692; setup_w6692()
1069 cs->readisacfifo = &ReadISACfifo; setup_w6692()
1070 cs->writeisacfifo = &WriteISACfifo; setup_w6692()
1071 cs->BC_Read_Reg = &ReadW6692B; setup_w6692()
1072 cs->BC_Write_Reg = &WriteW6692B; setup_w6692()
1073 cs->BC_Send_Data = &W6692B_fill_fifo; setup_w6692()
1074 cs->cardmsg = &w6692_card_msg; setup_w6692()
1075 cs->irq_func = &W6692_interrupt; setup_w6692()
1076 cs->irq_flags |= IRQF_SHARED; setup_w6692()
1077 W6692Version(cs, "W6692:"); setup_w6692()
1078 printk(KERN_INFO "W6692 ISTA=0x%X\n", ReadW6692(cs, W_ISTA)); setup_w6692()
1079 printk(KERN_INFO "W6692 IMASK=0x%X\n", ReadW6692(cs, W_IMASK)); setup_w6692()
1080 printk(KERN_INFO "W6692 D_EXIR=0x%X\n", ReadW6692(cs, W_D_EXIR)); setup_w6692()
1081 printk(KERN_INFO "W6692 D_EXIM=0x%X\n", ReadW6692(cs, W_D_EXIM)); setup_w6692()
1082 printk(KERN_INFO "W6692 D_RSTA=0x%X\n", ReadW6692(cs, W_D_RSTA)); setup_w6692()
|
| H A D | hfc_2bds0.c | 29 dummyf(struct IsdnCardState *cs, u_char *data, int size) dummyf() argument
35 ReadReg(struct IsdnCardState *cs, int data, u_char reg) ReadReg() argument
40 if (cs->hw.hfcD.cip != reg) { ReadReg()
41 cs->hw.hfcD.cip = reg; ReadReg()
42 byteout(cs->hw.hfcD.addr | 1, reg); ReadReg()
44 ret = bytein(cs->hw.hfcD.addr); ReadReg()
46 if (cs->debug & L1_DEB_HSCX_FIFO && (data != 2)) ReadReg()
47 debugl1(cs, "t3c RD %02x %02x", reg, ret); ReadReg()
50 ret = bytein(cs->hw.hfcD.addr | 1); ReadReg()
55 WriteReg(struct IsdnCardState *cs, int data, u_char reg, u_char value) WriteReg() argument
57 if (cs->hw.hfcD.cip != reg) { WriteReg()
58 cs->hw.hfcD.cip = reg; WriteReg()
59 byteout(cs->hw.hfcD.addr | 1, reg); WriteReg()
62 byteout(cs->hw.hfcD.addr, value); WriteReg()
64 if (cs->debug & L1_DEB_HSCX_FIFO && (data != HFCD_DATA_NODEB)) WriteReg()
65 debugl1(cs, "t3c W%c %02x %02x", data ? 'D' : 'C', reg, value); WriteReg()
72 readreghfcd(struct IsdnCardState *cs, u_char offset) readreghfcd() argument
74 return (ReadReg(cs, HFCD_DATA, offset)); readreghfcd()
78 writereghfcd(struct IsdnCardState *cs, u_char offset, u_char value) writereghfcd() argument
80 WriteReg(cs, HFCD_DATA, offset, value); writereghfcd()
84 WaitForBusy(struct IsdnCardState *cs) WaitForBusy() argument
88 while (!(ReadReg(cs, HFCD_DATA, HFCD_STAT) & HFCD_BUSY) && to) { WaitForBusy()
98 WaitNoBusy(struct IsdnCardState *cs) WaitNoBusy() argument
102 while ((ReadReg(cs, HFCD_STATUS, HFCD_STATUS) & HFCD_BUSY) && to) { WaitNoBusy()
112 SelFiFo(struct IsdnCardState *cs, u_char FiFo) SelFiFo() argument
116 if (cs->hw.hfcD.fifo == FiFo) SelFiFo()
132 debugl1(cs, "SelFiFo Error"); SelFiFo()
135 cs->hw.hfcD.fifo = FiFo; SelFiFo()
136 WaitNoBusy(cs); SelFiFo()
137 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0); SelFiFo()
138 WaitForBusy(cs); SelFiFo()
148 return (bcs->cs->hw.hfcD.bfifosize); GetFreeFifoBytes_B()
151 s += bcs->cs->hw.hfcD.bfifosize; GetFreeFifoBytes_B()
152 s = bcs->cs->hw.hfcD.bfifosize - s; GetFreeFifoBytes_B()
157 GetFreeFifoBytes_D(struct IsdnCardState *cs) GetFreeFifoBytes_D() argument
161 if (cs->hw.hfcD.f1 == cs->hw.hfcD.f2) GetFreeFifoBytes_D()
162 return (cs->hw.hfcD.dfifosize); GetFreeFifoBytes_D()
163 s = cs->hw.hfcD.send[cs->hw.hfcD.f1] - cs->hw.hfcD.send[cs->hw.hfcD.f2]; GetFreeFifoBytes_D()
165 s += cs->hw.hfcD.dfifosize; GetFreeFifoBytes_D()
166 s = cs->hw.hfcD.dfifosize - s; GetFreeFifoBytes_D()
171 ReadZReg(struct IsdnCardState *cs, u_char reg) ReadZReg() argument
175 WaitNoBusy(cs); ReadZReg()
176 val = 256 * ReadReg(cs, HFCD_DATA, reg | HFCB_Z_HIGH); ReadZReg()
177 WaitNoBusy(cs); ReadZReg()
178 val += ReadReg(cs, HFCD_DATA, reg | HFCB_Z_LOW); ReadZReg()
187 struct IsdnCardState *cs = bcs->cs; hfc_empty_fifo() local
192 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hfc_empty_fifo()
193 debugl1(cs, "hfc_empty_fifo"); hfc_empty_fifo()
196 if (cs->debug & L1_DEB_WARN) hfc_empty_fifo()
197 debugl1(cs, "hfc_empty_fifo: incoming packet too large"); hfc_empty_fifo()
200 WaitNoBusy(cs); hfc_empty_fifo()
201 ReadReg(cs, HFCD_DATA_NODEB, cip); hfc_empty_fifo()
205 if (cs->debug & L1_DEB_WARN) hfc_empty_fifo()
206 debugl1(cs, "hfc_empty_fifo: incoming packet too small"); hfc_empty_fifo()
211 while ((idx++ < count) && WaitNoBusy(cs)) hfc_empty_fifo()
212 ReadReg(cs, HFCD_DATA_NODEB, cip); hfc_empty_fifo()
221 if (!WaitNoBusy(cs)) hfc_empty_fifo()
223 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip); hfc_empty_fifo()
228 debugl1(cs, "RFIFO BUSY error"); hfc_empty_fifo()
233 WaitNoBusy(cs); hfc_empty_fifo()
234 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); hfc_empty_fifo()
235 WaitNoBusy(cs); hfc_empty_fifo()
236 chksum += ReadReg(cs, HFCD_DATA, cip); hfc_empty_fifo()
237 WaitNoBusy(cs); hfc_empty_fifo()
238 stat = ReadReg(cs, HFCD_DATA, cip); hfc_empty_fifo()
239 if (cs->debug & L1_DEB_HSCX) hfc_empty_fifo()
240 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x", hfc_empty_fifo()
243 debugl1(cs, "FIFO CRC error"); hfc_empty_fifo()
252 WaitForBusy(cs); hfc_empty_fifo()
253 WaitNoBusy(cs); hfc_empty_fifo()
254 stat = ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F2_INC | hfc_empty_fifo()
256 WaitForBusy(cs); hfc_empty_fifo()
263 struct IsdnCardState *cs = bcs->cs; hfc_fill_fifo() local
272 SelFiFo(cs, HFCB_SEND | HFCB_CHANNEL(bcs->channel)); hfc_fill_fifo()
274 WaitNoBusy(cs); hfc_fill_fifo()
275 bcs->hw.hfc.f1 = ReadReg(cs, HFCD_DATA, cip); hfc_fill_fifo()
276 WaitNoBusy(cs); hfc_fill_fifo()
278 WaitNoBusy(cs); hfc_fill_fifo()
279 bcs->hw.hfc.f2 = ReadReg(cs, HFCD_DATA, cip); hfc_fill_fifo()
280 bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_SEND | HFCB_CHANNEL(bcs->channel)); hfc_fill_fifo()
281 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
282 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)", hfc_fill_fifo()
289 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
290 debugl1(cs, "hfc_fill_fifo more as 30 frames"); hfc_fill_fifo()
294 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
295 debugl1(cs, "hfc_fill_fifo %d count(%u/%d),%lx", hfc_fill_fifo()
299 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
300 debugl1(cs, "hfc_fill_fifo no fifo mem"); hfc_fill_fifo()
305 WaitForBusy(cs); hfc_fill_fifo()
306 WaitNoBusy(cs); hfc_fill_fifo()
307 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx++]); hfc_fill_fifo()
309 if (!WaitNoBusy(cs)) hfc_fill_fifo()
311 WriteReg(cs, HFCD_DATA_NODEB, cip, bcs->tx_skb->data[idx]); hfc_fill_fifo()
315 debugl1(cs, "FIFO Send BUSY error"); hfc_fill_fifo()
330 WaitForBusy(cs); hfc_fill_fifo()
331 WaitNoBusy(cs); hfc_fill_fifo()
332 ReadReg(cs, HFCD_DATA, HFCB_FIFO | HFCB_F1_INC | HFCB_SEND | HFCB_CHANNEL(bcs->channel)); hfc_fill_fifo()
333 WaitForBusy(cs); hfc_fill_fifo()
341 struct IsdnCardState *cs = bcs->cs; hfc_send_data() local
343 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc_send_data()
345 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc_send_data()
347 debugl1(cs, "send_data %d blocked", bcs->channel); hfc_send_data()
353 struct IsdnCardState *cs = bcs->cs; main_rec_2bds0() local
361 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { main_rec_2bds0()
362 debugl1(cs, "rec_data %d blocked", bcs->channel); main_rec_2bds0()
365 SelFiFo(cs, HFCB_REC | HFCB_CHANNEL(bcs->channel)); main_rec_2bds0()
367 WaitNoBusy(cs); main_rec_2bds0()
368 f1 = ReadReg(cs, HFCD_DATA, cip); main_rec_2bds0()
370 WaitNoBusy(cs); main_rec_2bds0()
371 f2 = ReadReg(cs, HFCD_DATA, cip); main_rec_2bds0()
373 if (cs->debug & L1_DEB_HSCX) main_rec_2bds0()
374 debugl1(cs, "hfc rec %d f1(%d) f2(%d)", main_rec_2bds0()
376 z1 = ReadZReg(cs, HFCB_FIFO | HFCB_Z1 | HFCB_REC | HFCB_CHANNEL(bcs->channel)); main_rec_2bds0()
377 z2 = ReadZReg(cs, HFCB_FIFO | HFCB_Z2 | HFCB_REC | HFCB_CHANNEL(bcs->channel)); main_rec_2bds0()
380 rcnt += cs->hw.hfcD.bfifosize; main_rec_2bds0()
382 if (cs->debug & L1_DEB_HSCX) main_rec_2bds0()
383 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)", main_rec_2bds0()
398 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); main_rec_2bds0()
407 struct IsdnCardState *cs = bcs->cs; mode_2bs0() local
409 if (cs->debug & L1_DEB_HSCX) mode_2bs0()
410 debugl1(cs, "HFCD bchannel mode %d bchan %d/%d", mode_2bs0()
417 cs->hw.hfcD.conn |= 0x18; mode_2bs0()
418 cs->hw.hfcD.sctrl &= ~SCTRL_B2_ENA; mode_2bs0()
420 cs->hw.hfcD.conn |= 0x3; mode_2bs0()
421 cs->hw.hfcD.sctrl &= ~SCTRL_B1_ENA; mode_2bs0()
426 cs->hw.hfcD.ctmt |= 2; mode_2bs0()
427 cs->hw.hfcD.conn &= ~0x18; mode_2bs0()
428 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA; mode_2bs0()
430 cs->hw.hfcD.ctmt |= 1; mode_2bs0()
431 cs->hw.hfcD.conn &= ~0x3; mode_2bs0()
432 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA; mode_2bs0()
437 cs->hw.hfcD.ctmt &= ~2; mode_2bs0()
438 cs->hw.hfcD.conn &= ~0x18; mode_2bs0()
439 cs->hw.hfcD.sctrl |= SCTRL_B2_ENA; mode_2bs0()
441 cs->hw.hfcD.ctmt &= ~1; mode_2bs0()
442 cs->hw.hfcD.conn &= ~0x3; mode_2bs0()
443 cs->hw.hfcD.sctrl |= SCTRL_B1_ENA; mode_2bs0()
447 WriteReg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); mode_2bs0()
448 WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); mode_2bs0()
449 WriteReg(cs, HFCD_DATA, HFCD_CONN, cs->hw.hfcD.conn); mode_2bs0()
461 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
467 bcs->cs->BC_Send_Data(bcs); hfc_l2l1()
469 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
472 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
478 bcs->cs->BC_Send_Data(bcs); hfc_l2l1()
480 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
490 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
493 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
500 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
504 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
526 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs) open_hfcstate() argument
556 struct IsdnCardState *cs = hfcd_bh() local
559 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { hfcd_bh()
560 switch (cs->dc.hfcd.ph_state) { hfcd_bh()
562 l1_msg(cs, HW_RESET | INDICATION, NULL); hfcd_bh()
565 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); hfcd_bh()
568 l1_msg(cs, HW_RSYNC | INDICATION, NULL); hfcd_bh()
571 l1_msg(cs, HW_INFO2 | INDICATION, NULL); hfcd_bh()
574 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); hfcd_bh()
580 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) hfcd_bh()
581 DChannel_proc_rcv(cs); hfcd_bh()
582 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) hfcd_bh()
583 DChannel_proc_xmt(cs); hfcd_bh()
587 int receive_dmsg(struct IsdnCardState *cs) receive_dmsg() argument
597 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { receive_dmsg()
598 debugl1(cs, "rec_dmsg blocked"); receive_dmsg()
601 SelFiFo(cs, 4 | HFCD_REC); receive_dmsg()
603 WaitNoBusy(cs); receive_dmsg()
604 f1 = cs->readisac(cs, cip) & 0xf; receive_dmsg()
606 WaitNoBusy(cs); receive_dmsg()
607 f2 = cs->readisac(cs, cip) & 0xf; receive_dmsg()
609 z1 = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_REC); receive_dmsg()
610 z2 = ReadZReg(cs, HFCD_FIFO | HFCD_Z2 | HFCD_REC); receive_dmsg()
613 rcnt += cs->hw.hfcD.dfifosize; receive_dmsg()
615 if (cs->debug & L1_DEB_ISAC) receive_dmsg()
616 debugl1(cs, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)", receive_dmsg()
621 if (cs->debug & L1_DEB_WARN) receive_dmsg()
622 debugl1(cs, "empty_fifo d: incoming packet too large"); receive_dmsg()
624 if (!(WaitNoBusy(cs))) receive_dmsg()
626 ReadReg(cs, HFCD_DATA_NODEB, cip); receive_dmsg()
630 if (cs->debug & L1_DEB_WARN) receive_dmsg()
631 debugl1(cs, "empty_fifo d: incoming packet too small"); receive_dmsg()
632 while ((idx++ < rcnt) && WaitNoBusy(cs)) receive_dmsg()
633 ReadReg(cs, HFCD_DATA_NODEB, cip); receive_dmsg()
637 if (!(WaitNoBusy(cs))) receive_dmsg()
639 *ptr = ReadReg(cs, HFCD_DATA_NODEB, cip); receive_dmsg()
644 debugl1(cs, "RFIFO D BUSY error"); receive_dmsg()
649 cs->err_rx++; receive_dmsg()
652 WaitNoBusy(cs); receive_dmsg()
653 chksum = (ReadReg(cs, HFCD_DATA, cip) << 8); receive_dmsg()
654 WaitNoBusy(cs); receive_dmsg()
655 chksum += ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
656 WaitNoBusy(cs); receive_dmsg()
657 stat = ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
658 if (cs->debug & L1_DEB_ISAC) receive_dmsg()
659 debugl1(cs, "empty_dfifo chksum %x stat %x", receive_dmsg()
662 debugl1(cs, "FIFO CRC error"); receive_dmsg()
666 cs->err_crc++; receive_dmsg()
669 skb_queue_tail(&cs->rq, skb); receive_dmsg()
670 schedule_event(cs, D_RCVBUFREADY); receive_dmsg()
675 WaitForBusy(cs); receive_dmsg()
677 WaitNoBusy(cs); receive_dmsg()
678 stat = ReadReg(cs, HFCD_DATA, cip); receive_dmsg()
679 WaitForBusy(cs); receive_dmsg()
681 WaitNoBusy(cs); receive_dmsg()
682 f2 = cs->readisac(cs, cip) & 0xf; receive_dmsg()
684 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); receive_dmsg()
689 hfc_fill_dfifo(struct IsdnCardState *cs) hfc_fill_dfifo() argument
695 if (!cs->tx_skb) hfc_fill_dfifo()
697 if (cs->tx_skb->len <= 0) hfc_fill_dfifo()
700 SelFiFo(cs, 4 | HFCD_SEND); hfc_fill_dfifo()
702 WaitNoBusy(cs); hfc_fill_dfifo()
703 cs->hw.hfcD.f1 = ReadReg(cs, HFCD_DATA, cip) & 0xf; hfc_fill_dfifo()
704 WaitNoBusy(cs); hfc_fill_dfifo()
706 cs->hw.hfcD.f2 = ReadReg(cs, HFCD_DATA, cip) & 0xf; hfc_fill_dfifo()
707 cs->hw.hfcD.send[cs->hw.hfcD.f1] = ReadZReg(cs, HFCD_FIFO | HFCD_Z1 | HFCD_SEND); hfc_fill_dfifo()
708 if (cs->debug & L1_DEB_ISAC) hfc_fill_dfifo()
709 debugl1(cs, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)", hfc_fill_dfifo()
710 cs->hw.hfcD.f1, cs->hw.hfcD.f2, hfc_fill_dfifo()
711 cs->hw.hfcD.send[cs->hw.hfcD.f1]); hfc_fill_dfifo()
712 fcnt = cs->hw.hfcD.f1 - cs->hw.hfcD.f2; hfc_fill_dfifo()
716 if (cs->debug & L1_DEB_HSCX) hfc_fill_dfifo()
717 debugl1(cs, "hfc_fill_Dfifo more as 14 frames"); hfc_fill_dfifo()
720 count = GetFreeFifoBytes_D(cs); hfc_fill_dfifo()
721 if (cs->debug & L1_DEB_ISAC) hfc_fill_dfifo()
722 debugl1(cs, "hfc_fill_Dfifo count(%u/%d)", hfc_fill_dfifo()
723 cs->tx_skb->len, count); hfc_fill_dfifo()
724 if (count < cs->tx_skb->len) { hfc_fill_dfifo()
725 if (cs->debug & L1_DEB_ISAC) hfc_fill_dfifo()
726 debugl1(cs, "hfc_fill_Dfifo no fifo mem"); hfc_fill_dfifo()
731 WaitForBusy(cs); hfc_fill_dfifo()
732 WaitNoBusy(cs); hfc_fill_dfifo()
733 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx++]); hfc_fill_dfifo()
734 while (idx < cs->tx_skb->len) { hfc_fill_dfifo()
735 if (!(WaitNoBusy(cs))) hfc_fill_dfifo()
737 WriteReg(cs, HFCD_DATA_NODEB, cip, cs->tx_skb->data[idx]); hfc_fill_dfifo()
740 if (idx != cs->tx_skb->len) { hfc_fill_dfifo()
741 debugl1(cs, "DFIFO Send BUSY error"); hfc_fill_dfifo()
744 WaitForBusy(cs); hfc_fill_dfifo()
745 WaitNoBusy(cs); hfc_fill_dfifo()
746 ReadReg(cs, HFCD_DATA, HFCD_FIFO | HFCD_F1_INC | HFCD_SEND); hfc_fill_dfifo()
747 dev_kfree_skb_any(cs->tx_skb); hfc_fill_dfifo()
748 cs->tx_skb = NULL; hfc_fill_dfifo()
749 WaitForBusy(cs); hfc_fill_dfifo()
754 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel) Sel_BCS() argument
756 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) Sel_BCS()
757 return (&cs->bcs[0]); Sel_BCS()
758 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) Sel_BCS()
759 return (&cs->bcs[1]); Sel_BCS()
765 hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val) hfc2bds0_interrupt() argument
771 if (cs->debug & L1_DEB_ISAC) hfc2bds0_interrupt()
772 debugl1(cs, "HFCD irq %x %s", val, hfc2bds0_interrupt()
773 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? hfc2bds0_interrupt()
775 val &= cs->hw.hfcD.int_m1; hfc2bds0_interrupt()
777 exval = cs->readisac(cs, HFCD_STATES) & 0xf; hfc2bds0_interrupt()
778 if (cs->debug & L1_DEB_ISAC) hfc2bds0_interrupt()
779 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcd.ph_state, hfc2bds0_interrupt()
781 cs->dc.hfcd.ph_state = exval; hfc2bds0_interrupt()
782 schedule_event(cs, D_L1STATECHANGE); hfc2bds0_interrupt()
786 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
787 cs->hw.hfcD.int_s1 |= val; hfc2bds0_interrupt()
790 if (cs->hw.hfcD.int_s1 & 0x18) { hfc2bds0_interrupt()
792 val = cs->hw.hfcD.int_s1; hfc2bds0_interrupt()
793 cs->hw.hfcD.int_s1 = exval; hfc2bds0_interrupt()
796 if (!(bcs = Sel_BCS(cs, 0))) { hfc2bds0_interrupt()
797 if (cs->debug) hfc2bds0_interrupt()
798 debugl1(cs, "hfcd spurious 0x08 IRQ"); hfc2bds0_interrupt()
803 if (!(bcs = Sel_BCS(cs, 1))) { hfc2bds0_interrupt()
804 if (cs->debug) hfc2bds0_interrupt()
805 debugl1(cs, "hfcd spurious 0x10 IRQ"); hfc2bds0_interrupt()
810 if (!(bcs = Sel_BCS(cs, 0))) { hfc2bds0_interrupt()
811 if (cs->debug) hfc2bds0_interrupt()
812 debugl1(cs, "hfcd spurious 0x01 IRQ"); hfc2bds0_interrupt()
815 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
817 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
819 debugl1(cs, "fill_data %d blocked", bcs->channel); hfc2bds0_interrupt()
822 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
824 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
826 debugl1(cs, "fill_data %d blocked", bcs->channel); hfc2bds0_interrupt()
834 if (!(bcs = Sel_BCS(cs, 1))) { hfc2bds0_interrupt()
835 if (cs->debug) hfc2bds0_interrupt()
836 debugl1(cs, "hfcd spurious 0x02 IRQ"); hfc2bds0_interrupt()
839 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
841 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
843 debugl1(cs, "fill_data %d blocked", bcs->channel); hfc2bds0_interrupt()
846 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
848 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
850 debugl1(cs, "fill_data %d blocked", bcs->channel); hfc2bds0_interrupt()
858 receive_dmsg(cs); hfc2bds0_interrupt()
861 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) hfc2bds0_interrupt()
862 del_timer(&cs->dbusytimer); hfc2bds0_interrupt()
863 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) hfc2bds0_interrupt()
864 schedule_event(cs, D_CLEARBUSY); hfc2bds0_interrupt()
865 if (cs->tx_skb) { hfc2bds0_interrupt()
866 if (cs->tx_skb->len) { hfc2bds0_interrupt()
867 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
868 hfc_fill_dfifo(cs); hfc2bds0_interrupt()
869 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
871 debugl1(cs, "hfc_fill_dfifo irq blocked"); hfc2bds0_interrupt()
875 dev_kfree_skb_irq(cs->tx_skb); hfc2bds0_interrupt()
876 cs->tx_cnt = 0; hfc2bds0_interrupt()
877 cs->tx_skb = NULL; hfc2bds0_interrupt()
880 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { hfc2bds0_interrupt()
881 cs->tx_cnt = 0; hfc2bds0_interrupt()
882 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfc2bds0_interrupt()
883 hfc_fill_dfifo(cs); hfc2bds0_interrupt()
884 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfc2bds0_interrupt()
886 debugl1(cs, "hfc_fill_dfifo irq blocked"); hfc2bds0_interrupt()
889 schedule_event(cs, D_XMTBUFREADY); hfc2bds0_interrupt()
892 if (cs->hw.hfcD.int_s1 && count--) { hfc2bds0_interrupt()
893 val = cs->hw.hfcD.int_s1; hfc2bds0_interrupt()
894 cs->hw.hfcD.int_s1 = 0; hfc2bds0_interrupt()
895 if (cs->debug & L1_DEB_ISAC) hfc2bds0_interrupt()
896 debugl1(cs, "HFCD irq %x loop %d", val, 15-count); hfc2bds0_interrupt()
905 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; HFCD_l1hw() local
911 if (cs->debug & DEB_DLOG_HEX) HFCD_l1hw()
912 LogFrame(cs, skb->data, skb->len); HFCD_l1hw()
913 if (cs->debug & DEB_DLOG_VERBOSE) HFCD_l1hw()
914 dlogframe(cs, skb, 0); HFCD_l1hw()
915 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
916 if (cs->tx_skb) { HFCD_l1hw()
917 skb_queue_tail(&cs->sq, skb); HFCD_l1hw()
919 if (cs->debug & L1_DEB_LAPD) HFCD_l1hw()
920 Logl2Frame(cs, skb, "PH_DATA Queued", 0); HFCD_l1hw()
923 cs->tx_skb = skb; HFCD_l1hw()
924 cs->tx_cnt = 0; HFCD_l1hw()
926 if (cs->debug & L1_DEB_LAPD) HFCD_l1hw()
927 Logl2Frame(cs, skb, "PH_DATA", 0); HFCD_l1hw()
929 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCD_l1hw()
930 hfc_fill_dfifo(cs); HFCD_l1hw()
931 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCD_l1hw()
933 debugl1(cs, "hfc_fill_dfifo blocked"); HFCD_l1hw()
936 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
939 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
940 if (cs->tx_skb) { HFCD_l1hw()
941 if (cs->debug & L1_DEB_WARN) HFCD_l1hw()
942 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); HFCD_l1hw()
943 skb_queue_tail(&cs->sq, skb); HFCD_l1hw()
944 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
947 if (cs->debug & DEB_DLOG_HEX) HFCD_l1hw()
948 LogFrame(cs, skb->data, skb->len); HFCD_l1hw()
949 if (cs->debug & DEB_DLOG_VERBOSE) HFCD_l1hw()
950 dlogframe(cs, skb, 0); HFCD_l1hw()
951 cs->tx_skb = skb; HFCD_l1hw()
952 cs->tx_cnt = 0; HFCD_l1hw()
954 if (cs->debug & L1_DEB_LAPD) HFCD_l1hw()
955 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); HFCD_l1hw()
957 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCD_l1hw()
958 hfc_fill_dfifo(cs); HFCD_l1hw()
959 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCD_l1hw()
961 debugl1(cs, "hfc_fill_dfifo blocked"); HFCD_l1hw()
962 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
966 if (cs->debug & L1_DEB_LAPD) HFCD_l1hw()
967 debugl1(cs, "-> PH_REQUEST_PULL"); HFCD_l1hw()
969 if (!cs->tx_skb) { HFCD_l1hw()
976 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
977 cs->writeisac(cs, HFCD_STATES, HFCD_LOAD_STATE | 3); /* HFC ST 3 */ HFCD_l1hw()
979 cs->writeisac(cs, HFCD_STATES, 3); /* HFC ST 2 */ HFCD_l1hw()
980 cs->hw.hfcD.mst_m |= HFCD_MASTER; HFCD_l1hw()
981 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); HFCD_l1hw()
982 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION); HFCD_l1hw()
983 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
984 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); HFCD_l1hw()
987 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
988 cs->writeisac(cs, HFCD_STATES, HFCD_ACTIVATE | HFCD_DO_ACTION); HFCD_l1hw()
989 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
992 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
993 cs->hw.hfcD.mst_m &= ~HFCD_MASTER; HFCD_l1hw()
994 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); HFCD_l1hw()
995 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
998 spin_lock_irqsave(&cs->lock, flags); HFCD_l1hw()
999 cs->hw.hfcD.mst_m |= HFCD_MASTER; HFCD_l1hw()
1000 cs->writeisac(cs, HFCD_MST_MODE, cs->hw.hfcD.mst_m); HFCD_l1hw()
1001 spin_unlock_irqrestore(&cs->lock, flags); HFCD_l1hw()
1004 if (cs->debug & L1_DEB_WARN) HFCD_l1hw()
1005 debugl1(cs, "hfcd_l1hw unknown pr %4x", pr); HFCD_l1hw()
1011 setstack_hfcd(struct PStack *st, struct IsdnCardState *cs) setstack_hfcd() argument
1017 hfc_dbusy_timer(struct IsdnCardState *cs) hfc_dbusy_timer() argument
1038 init2bds0(struct IsdnCardState *cs) init2bds0() argument
1040 cs->setstack_d = setstack_hfcd; init2bds0()
1041 if (!cs->hw.hfcD.send) init2bds0()
1042 cs->hw.hfcD.send = init_send_hfcd(16); init2bds0()
1043 if (!cs->bcs[0].hw.hfc.send) init2bds0()
1044 cs->bcs[0].hw.hfc.send = init_send_hfcd(32); init2bds0()
1045 if (!cs->bcs[1].hw.hfc.send) init2bds0()
1046 cs->bcs[1].hw.hfc.send = init_send_hfcd(32); init2bds0()
1047 cs->BC_Send_Data = &hfc_send_data; init2bds0()
1048 cs->bcs[0].BC_SetStack = setstack_2b; init2bds0()
1049 cs->bcs[1].BC_SetStack = setstack_2b; init2bds0()
1050 cs->bcs[0].BC_Close = close_2bs0; init2bds0()
1051 cs->bcs[1].BC_Close = close_2bs0; init2bds0()
1052 mode_2bs0(cs->bcs, 0, 0); init2bds0()
1053 mode_2bs0(cs->bcs + 1, 0, 1); init2bds0()
1057 release2bds0(struct IsdnCardState *cs) release2bds0() argument
1059 kfree(cs->bcs[0].hw.hfc.send); release2bds0()
1060 cs->bcs[0].hw.hfc.send = NULL; release2bds0()
1061 kfree(cs->bcs[1].hw.hfc.send); release2bds0()
1062 cs->bcs[1].hw.hfc.send = NULL; release2bds0()
1063 kfree(cs->hw.hfcD.send); release2bds0()
1064 cs->hw.hfcD.send = NULL; release2bds0()
1068 set_cs_func(struct IsdnCardState *cs) set_cs_func() argument
1070 cs->readisac = &readreghfcd; set_cs_func()
1071 cs->writeisac = &writereghfcd; set_cs_func()
1072 cs->readisacfifo = &dummyf; set_cs_func()
1073 cs->writeisacfifo = &dummyf; set_cs_func()
1074 cs->BC_Read_Reg = &ReadReg; set_cs_func()
1075 cs->BC_Write_Reg = &WriteReg; set_cs_func()
1076 cs->dbusytimer.function = (void *) hfc_dbusy_timer; set_cs_func()
1077 cs->dbusytimer.data = (long) cs; set_cs_func()
1078 init_timer(&cs->dbusytimer); set_cs_func()
1079 INIT_WORK(&cs->tqueue, hfcd_bh); set_cs_func()
|
| H A D | diva.c | 132 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
134 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset)); ReadISAC()
138 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
140 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); WriteISAC()
144 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
146 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); ReadISACfifo()
150 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
152 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0, data, size); WriteISACfifo()
156 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) ReadISAC_IPAC() argument
158 return (readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset + 0x80)); ReadISAC_IPAC()
162 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC_IPAC() argument
164 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset | 0x80, value); WriteISAC_IPAC()
168 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo_IPAC() argument
170 readfifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); ReadISACfifo_IPAC()
174 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo_IPAC() argument
176 writefifo(cs->hw.diva.isac_adr, cs->hw.diva.isac, 0x80, data, size); WriteISACfifo_IPAC()
180 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
182 return (readreg(cs->hw.diva.hscx_adr, ReadHSCX()
183 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
187 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
189 writereg(cs->hw.diva.hscx_adr, WriteHSCX()
190 cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
194 MemReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) MemReadISAC_IPAC() argument
196 return (memreadreg(cs->hw.diva.cfg_reg, offset + 0x80)); MemReadISAC_IPAC()
200 MemWriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value) MemWriteISAC_IPAC() argument
202 memwritereg(cs->hw.diva.cfg_reg, offset | 0x80, value); MemWriteISAC_IPAC()
206 MemReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) MemReadISACfifo_IPAC() argument
209 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80); MemReadISACfifo_IPAC()
213 MemWriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) MemWriteISACfifo_IPAC() argument
216 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++); MemWriteISACfifo_IPAC()
220 MemReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) MemReadHSCX() argument
222 return (memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); MemReadHSCX()
226 MemWriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) MemWriteHSCX() argument
228 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); MemWriteHSCX()
233 MemReadISAC_IPACX(struct IsdnCardState *cs, u_char offset) MemReadISAC_IPACX() argument
235 return (memreadreg(cs->hw.diva.cfg_reg, offset)); MemReadISAC_IPACX()
239 MemWriteISAC_IPACX(struct IsdnCardState *cs, u_char offset, u_char value) MemWriteISAC_IPACX() argument
241 memwritereg(cs->hw.diva.cfg_reg, offset, value); MemWriteISAC_IPACX()
245 MemReadISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size) MemReadISACfifo_IPACX() argument
248 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0); MemReadISACfifo_IPACX()
252 MemWriteISACfifo_IPACX(struct IsdnCardState *cs, u_char *data, int size) MemWriteISACfifo_IPACX() argument
255 memwritereg(cs->hw.diva.cfg_reg, 0, *data++); MemWriteISACfifo_IPACX()
259 MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset) MemReadHSCX_IPACX() argument
261 return (memreadreg(cs->hw.diva.cfg_reg, offset + MemReadHSCX_IPACX()
266 MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) MemWriteHSCX_IPACX() argument
268 memwritereg(cs->hw.diva.cfg_reg, offset + MemWriteHSCX_IPACX()
276 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
277 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
278 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
281 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
282 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
284 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
285 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
292 struct IsdnCardState *cs = dev_id; diva_interrupt() local
297 spin_lock_irqsave(&cs->lock, flags); diva_interrupt()
298 while (((sval = bytein(cs->hw.diva.ctrl)) & DIVA_IRQ_REQ) && cnt) { diva_interrupt()
299 val = readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_ISTA + 0x40); diva_interrupt()
301 hscx_int_main(cs, val); diva_interrupt()
302 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA); diva_interrupt()
304 isac_interrupt(cs, val); diva_interrupt()
309 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); diva_interrupt()
310 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); diva_interrupt()
311 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); diva_interrupt()
312 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); diva_interrupt()
313 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); diva_interrupt()
314 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0x0); diva_interrupt()
315 spin_unlock_irqrestore(&cs->lock, flags); diva_interrupt()
322 struct IsdnCardState *cs = dev_id; diva_irq_ipac_isa() local
327 spin_lock_irqsave(&cs->lock, flags); diva_irq_ipac_isa()
328 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); diva_irq_ipac_isa()
330 if (cs->debug & L1_DEB_IPAC) diva_irq_ipac_isa()
331 debugl1(cs, "IPAC ISTA %02X", ista); diva_irq_ipac_isa()
333 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, HSCX_ISTA + 0x40); diva_irq_ipac_isa()
341 hscx_int_main(cs, val); diva_irq_ipac_isa()
344 val = 0xfe & readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_ISTA + 0x80); diva_irq_ipac_isa()
346 isac_interrupt(cs, val); diva_irq_ipac_isa()
351 isac_interrupt(cs, val); diva_irq_ipac_isa()
353 ista = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ISTA); diva_irq_ipac_isa()
360 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xFF); diva_irq_ipac_isa()
361 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xC0); diva_irq_ipac_isa()
362 spin_unlock_irqrestore(&cs->lock, flags); diva_irq_ipac_isa()
367 MemwaitforCEC(struct IsdnCardState *cs, int hscx) MemwaitforCEC() argument
371 while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { MemwaitforCEC()
381 MemwaitforXFW(struct IsdnCardState *cs, int hscx) MemwaitforXFW() argument
385 while (((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { MemwaitforXFW()
394 MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) MemWriteHSCXCMDR() argument
396 MemwaitforCEC(cs, hscx); MemWriteHSCXCMDR()
397 MemWriteHSCX(cs, hscx, HSCX_CMDR, data); MemWriteHSCXCMDR()
404 struct IsdnCardState *cs = bcs->cs; Memhscx_empty_fifo() local
407 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) Memhscx_empty_fifo()
408 debugl1(cs, "hscx_empty_fifo"); Memhscx_empty_fifo()
411 if (cs->debug & L1_DEB_WARN) Memhscx_empty_fifo()
412 debugl1(cs, "hscx_empty_fifo: incoming packet too large"); Memhscx_empty_fifo()
413 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo()
420 *ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0); Memhscx_empty_fifo()
421 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); Memhscx_empty_fifo()
424 if (cs->debug & L1_DEB_HSCX_FIFO) { Memhscx_empty_fifo()
430 debugl1(cs, "%s", bcs->blog); Memhscx_empty_fifo()
437 struct IsdnCardState *cs = bcs->cs; Memhscx_fill_fifo() local
439 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32; Memhscx_fill_fifo()
442 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) Memhscx_fill_fifo()
443 debugl1(cs, "hscx_fill_fifo"); Memhscx_fill_fifo()
457 MemwaitforXFW(cs, bcs->hw.hscx.hscx); Memhscx_fill_fifo()
463 memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0, Memhscx_fill_fifo()
465 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa); Memhscx_fill_fifo()
466 if (cs->debug & L1_DEB_HSCX_FIFO) { Memhscx_fill_fifo()
472 debugl1(cs, "%s", bcs->blog); Memhscx_fill_fifo()
477 Memhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx) Memhscx_interrupt() argument
480 struct BCState *bcs = cs->bcs + hscx; Memhscx_interrupt()
482 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32; Memhscx_interrupt()
489 r = MemReadHSCX(cs, hscx, HSCX_RSTA); Memhscx_interrupt()
492 if (cs->debug & L1_DEB_WARN) Memhscx_interrupt()
493 debugl1(cs, "HSCX invalid frame"); Memhscx_interrupt()
495 if (cs->debug & L1_DEB_WARN) Memhscx_interrupt()
496 debugl1(cs, "HSCX RDO mode=%d", Memhscx_interrupt()
499 if (cs->debug & L1_DEB_WARN) Memhscx_interrupt()
500 debugl1(cs, "HSCX CRC error"); Memhscx_interrupt()
501 MemWriteHSCXCMDR(cs, hscx, 0x80); Memhscx_interrupt()
503 count = MemReadHSCX(cs, hscx, HSCX_RBCL) & ( Memhscx_interrupt()
504 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x3f : 0x1f); Memhscx_interrupt()
509 if (cs->debug & L1_DEB_HSCX_FIFO) Memhscx_interrupt()
510 debugl1(cs, "HX Frame %d", count); Memhscx_interrupt()
567 Memhscx_int_main(struct IsdnCardState *cs, u_char val) Memhscx_int_main() argument
574 bcs = cs->bcs + 1; Memhscx_int_main()
575 exval = MemReadHSCX(cs, 1, HSCX_EXIR); Memhscx_int_main()
588 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main()
589 if (cs->debug & L1_DEB_WARN) Memhscx_int_main()
590 debugl1(cs, "HSCX B EXIR %x Lost TX", exval); Memhscx_int_main()
592 } else if (cs->debug & L1_DEB_HSCX) Memhscx_int_main()
593 debugl1(cs, "HSCX B EXIR %x", exval); Memhscx_int_main()
596 if (cs->debug & L1_DEB_HSCX) Memhscx_int_main()
597 debugl1(cs, "HSCX B interrupt %x", val); Memhscx_int_main()
598 Memhscx_interrupt(cs, val, 1); Memhscx_int_main()
601 bcs = cs->bcs; Memhscx_int_main()
602 exval = MemReadHSCX(cs, 0, HSCX_EXIR); Memhscx_int_main()
615 MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); Memhscx_int_main()
616 if (cs->debug & L1_DEB_WARN) Memhscx_int_main()
617 debugl1(cs, "HSCX A EXIR %x Lost TX", exval); Memhscx_int_main()
619 } else if (cs->debug & L1_DEB_HSCX) Memhscx_int_main()
620 debugl1(cs, "HSCX A EXIR %x", exval); Memhscx_int_main()
623 exval = MemReadHSCX(cs, 0, HSCX_ISTA); Memhscx_int_main()
624 if (cs->debug & L1_DEB_HSCX) Memhscx_int_main()
625 debugl1(cs, "HSCX A interrupt %x", exval); Memhscx_int_main()
626 Memhscx_interrupt(cs, exval, 0); Memhscx_int_main()
633 struct IsdnCardState *cs = dev_id; diva_irq_ipac_pci() local
639 spin_lock_irqsave(&cs->lock, flags); diva_irq_ipac_pci()
640 cfg = (u_char *) cs->hw.diva.pci_cfg; diva_irq_ipac_pci()
643 spin_unlock_irqrestore(&cs->lock, flags); diva_irq_ipac_pci()
647 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA); diva_irq_ipac_pci()
649 if (cs->debug & L1_DEB_IPAC) diva_irq_ipac_pci()
650 debugl1(cs, "IPAC ISTA %02X", ista); diva_irq_ipac_pci()
652 val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40); diva_irq_ipac_pci()
660 Memhscx_int_main(cs, val); diva_irq_ipac_pci()
663 val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80); diva_irq_ipac_pci()
665 isac_interrupt(cs, val); diva_irq_ipac_pci()
670 isac_interrupt(cs, val); diva_irq_ipac_pci()
672 ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA); diva_irq_ipac_pci()
679 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF); diva_irq_ipac_pci()
680 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0); diva_irq_ipac_pci()
681 spin_unlock_irqrestore(&cs->lock, flags); diva_irq_ipac_pci()
688 struct IsdnCardState *cs = dev_id; diva_irq_ipacx_pci() local
693 spin_lock_irqsave(&cs->lock, flags); diva_irq_ipacx_pci()
694 cfg = (u_char *) cs->hw.diva.pci_cfg; diva_irq_ipacx_pci()
697 spin_unlock_irqrestore(&cs->lock, flags); diva_irq_ipacx_pci()
700 interrupt_ipacx(cs); // handler for chip diva_irq_ipacx_pci()
702 spin_unlock_irqrestore(&cs->lock, flags); diva_irq_ipacx_pci()
707 release_io_diva(struct IsdnCardState *cs) release_io_diva() argument
711 if ((cs->subtyp == DIVA_IPAC_PCI) || release_io_diva()
712 (cs->subtyp == DIVA_IPACX_PCI)) { release_io_diva()
713 u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg; release_io_diva()
717 if (cs->hw.diva.cfg_reg) release_io_diva()
718 iounmap((void *)cs->hw.diva.cfg_reg); release_io_diva()
719 if (cs->hw.diva.pci_cfg) release_io_diva()
720 iounmap((void *)cs->hw.diva.pci_cfg); release_io_diva()
722 } else if (cs->subtyp != DIVA_IPAC_ISA) { release_io_diva()
723 del_timer(&cs->hw.diva.tl); release_io_diva()
724 if (cs->hw.diva.cfg_reg) release_io_diva()
725 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */ release_io_diva()
727 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA)) release_io_diva()
731 if (cs->hw.diva.cfg_reg) { release_io_diva()
732 release_region(cs->hw.diva.cfg_reg, bytecnt); release_io_diva()
737 iounmap_diva(struct IsdnCardState *cs) iounmap_diva() argument
739 if ((cs->subtyp == DIVA_IPAC_PCI) || (cs->subtyp == DIVA_IPACX_PCI)) { iounmap_diva()
740 if (cs->hw.diva.cfg_reg) { iounmap_diva()
741 iounmap((void *)cs->hw.diva.cfg_reg); iounmap_diva()
742 cs->hw.diva.cfg_reg = 0; iounmap_diva()
744 if (cs->hw.diva.pci_cfg) { iounmap_diva()
745 iounmap((void *)cs->hw.diva.pci_cfg); iounmap_diva()
746 cs->hw.diva.pci_cfg = 0; iounmap_diva()
754 reset_diva(struct IsdnCardState *cs) reset_diva() argument
756 if (cs->subtyp == DIVA_IPAC_ISA) { reset_diva()
757 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20); reset_diva()
759 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00); reset_diva()
761 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0); reset_diva()
762 } else if (cs->subtyp == DIVA_IPAC_PCI) { reset_diva()
763 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg + reset_diva()
769 memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0); reset_diva()
770 } else if (cs->subtyp == DIVA_IPACX_PCI) { reset_diva()
771 unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg + reset_diva()
777 MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off reset_diva()
779 cs->hw.diva.ctrl_reg = 0; /* Reset On */ reset_diva()
780 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
782 cs->hw.diva.ctrl_reg |= DIVA_RESET; /* Reset Off */ reset_diva()
783 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
785 if (cs->subtyp == DIVA_ISA) reset_diva()
786 cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A; reset_diva()
789 byteout(cs->hw.diva.pci_cfg + 0x69, 9); reset_diva()
790 cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A; reset_diva()
792 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); reset_diva()
799 diva_led_handler(struct IsdnCardState *cs) diva_led_handler() argument
803 if ((cs->subtyp == DIVA_IPAC_ISA) || diva_led_handler()
804 (cs->subtyp == DIVA_IPAC_PCI) || diva_led_handler()
805 (cs->subtyp == DIVA_IPACX_PCI)) diva_led_handler()
807 del_timer(&cs->hw.diva.tl); diva_led_handler()
808 if (cs->hw.diva.status & DIVA_ASSIGN) diva_led_handler()
809 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
812 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
816 if (cs->hw.diva.status & 0xf000) diva_led_handler()
817 cs->hw.diva.ctrl_reg |= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
819 else if (cs->hw.diva.status & 0x0f00) { diva_led_handler()
820 cs->hw.diva.ctrl_reg ^= (DIVA_ISA == cs->subtyp) ? diva_led_handler()
824 cs->hw.diva.ctrl_reg &= ~((DIVA_ISA == cs->subtyp) ? diva_led_handler()
827 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); diva_led_handler()
829 init_timer(&cs->hw.diva.tl); diva_led_handler()
830 cs->hw.diva.tl.expires = jiffies + ((blink * HZ) / 1000); diva_led_handler()
831 add_timer(&cs->hw.diva.tl); diva_led_handler()
836 Diva_card_msg(struct IsdnCardState *cs, int mt, void *arg) Diva_card_msg() argument
843 spin_lock_irqsave(&cs->lock, flags); Diva_card_msg()
844 reset_diva(cs); Diva_card_msg()
845 spin_unlock_irqrestore(&cs->lock, flags); Diva_card_msg()
848 release_io_diva(cs); Diva_card_msg()
851 spin_lock_irqsave(&cs->lock, flags); Diva_card_msg()
852 reset_diva(cs); Diva_card_msg()
853 if (cs->subtyp == DIVA_IPACX_PCI) { Diva_card_msg()
854 ireg = (unsigned int *)cs->hw.diva.pci_cfg; Diva_card_msg()
856 init_ipacx(cs, 3); // init chip and enable interrupts Diva_card_msg()
857 spin_unlock_irqrestore(&cs->lock, flags); Diva_card_msg()
860 if (cs->subtyp == DIVA_IPAC_PCI) { Diva_card_msg()
861 ireg = (unsigned int *)cs->hw.diva.pci_cfg; Diva_card_msg()
864 inithscxisac(cs, 3); Diva_card_msg()
865 spin_unlock_irqrestore(&cs->lock, flags); Diva_card_msg()
870 cs->hw.diva.status = 0; Diva_card_msg()
873 cs->hw.diva.status |= DIVA_ASSIGN; Diva_card_msg()
877 cs->hw.diva.status |= 0x0200; Diva_card_msg()
879 cs->hw.diva.status |= 0x0100; Diva_card_msg()
883 cs->hw.diva.status |= 0x2000; Diva_card_msg()
885 cs->hw.diva.status |= 0x1000; Diva_card_msg()
889 cs->hw.diva.status &= ~0x2000; Diva_card_msg()
890 cs->hw.diva.status &= ~0x0200; Diva_card_msg()
892 cs->hw.diva.status &= ~0x1000; Diva_card_msg()
893 cs->hw.diva.status &= ~0x0100; Diva_card_msg()
897 if ((cs->subtyp != DIVA_IPAC_ISA) && Diva_card_msg()
898 (cs->subtyp != DIVA_IPAC_PCI) && Diva_card_msg()
899 (cs->subtyp != DIVA_IPACX_PCI)) { Diva_card_msg()
900 spin_lock_irqsave(&cs->lock, flags); Diva_card_msg()
901 diva_led_handler(cs); Diva_card_msg()
902 spin_unlock_irqrestore(&cs->lock, flags); Diva_card_msg()
907 static int setup_diva_common(struct IsdnCardState *cs) setup_diva_common() argument
912 if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA)) setup_diva_common()
919 (cs->subtyp == DIVA_PCI) ? "PCI" : setup_diva_common()
920 (cs->subtyp == DIVA_ISA) ? "ISA" : setup_diva_common()
921 (cs->subtyp == DIVA_IPAC_ISA) ? "IPAC ISA" : setup_diva_common()
922 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI", setup_diva_common()
923 cs->hw.diva.cfg_reg, cs->irq); setup_diva_common()
924 if ((cs->subtyp == DIVA_IPAC_PCI) || setup_diva_common()
925 (cs->subtyp == DIVA_IPACX_PCI) || setup_diva_common()
926 (cs->subtyp == DIVA_PCI)) setup_diva_common()
928 (cs->subtyp == DIVA_PCI) ? "PCI" : setup_diva_common()
929 (cs->subtyp == DIVA_IPAC_PCI) ? "IPAC PCI" : "IPACX PCI", setup_diva_common()
930 cs->hw.diva.pci_cfg); setup_diva_common()
931 if ((cs->subtyp != DIVA_IPAC_PCI) && setup_diva_common()
932 (cs->subtyp != DIVA_IPACX_PCI)) { setup_diva_common()
933 if (!request_region(cs->hw.diva.cfg_reg, bytecnt, "diva isdn")) { setup_diva_common()
937 cs->hw.diva.cfg_reg, setup_diva_common()
938 cs->hw.diva.cfg_reg + bytecnt); setup_diva_common()
939 iounmap_diva(cs); setup_diva_common()
943 cs->BC_Read_Reg = &ReadHSCX; setup_diva_common()
944 cs->BC_Write_Reg = &WriteHSCX; setup_diva_common()
945 cs->BC_Send_Data = &hscx_fill_fifo; setup_diva_common()
946 cs->cardmsg = &Diva_card_msg; setup_diva_common()
947 setup_isac(cs); setup_diva_common()
948 if (cs->subtyp == DIVA_IPAC_ISA) { setup_diva_common()
949 cs->readisac = &ReadISAC_IPAC; setup_diva_common()
950 cs->writeisac = &WriteISAC_IPAC; setup_diva_common()
951 cs->readisacfifo = &ReadISACfifo_IPAC; setup_diva_common()
952 cs->writeisacfifo = &WriteISACfifo_IPAC; setup_diva_common()
953 cs->irq_func = &diva_irq_ipac_isa; setup_diva_common()
954 val = readreg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_ID); setup_diva_common()
956 } else if (cs->subtyp == DIVA_IPAC_PCI) { setup_diva_common()
957 cs->readisac = &MemReadISAC_IPAC; setup_diva_common()
958 cs->writeisac = &MemWriteISAC_IPAC; setup_diva_common()
959 cs->readisacfifo = &MemReadISACfifo_IPAC; setup_diva_common()
960 cs->writeisacfifo = &MemWriteISACfifo_IPAC; setup_diva_common()
961 cs->BC_Read_Reg = &MemReadHSCX; setup_diva_common()
962 cs->BC_Write_Reg = &MemWriteHSCX; setup_diva_common()
963 cs->BC_Send_Data = &Memhscx_fill_fifo; setup_diva_common()
964 cs->irq_func = &diva_irq_ipac_pci; setup_diva_common()
965 val = memreadreg(cs->hw.diva.cfg_reg, IPAC_ID); setup_diva_common()
967 } else if (cs->subtyp == DIVA_IPACX_PCI) { setup_diva_common()
968 cs->readisac = &MemReadISAC_IPACX; setup_diva_common()
969 cs->writeisac = &MemWriteISAC_IPACX; setup_diva_common()
970 cs->readisacfifo = &MemReadISACfifo_IPACX; setup_diva_common()
971 cs->writeisacfifo = &MemWriteISACfifo_IPACX; setup_diva_common()
972 cs->BC_Read_Reg = &MemReadHSCX_IPACX; setup_diva_common()
973 cs->BC_Write_Reg = &MemWriteHSCX_IPACX; setup_diva_common()
974 cs->BC_Send_Data = NULL; // function located in ipacx module setup_diva_common()
975 cs->irq_func = &diva_irq_ipacx_pci; setup_diva_common()
977 MemReadISAC_IPACX(cs, IPACX_ID) & 0x3F); setup_diva_common()
979 cs->hw.diva.tl.function = (void *) diva_led_handler; setup_diva_common()
980 cs->hw.diva.tl.data = (long) cs; setup_diva_common()
981 init_timer(&cs->hw.diva.tl); setup_diva_common()
982 cs->readisac = &ReadISAC; setup_diva_common()
983 cs->writeisac = &WriteISAC; setup_diva_common()
984 cs->readisacfifo = &ReadISACfifo; setup_diva_common()
985 cs->writeisacfifo = &WriteISACfifo; setup_diva_common()
986 cs->irq_func = &diva_interrupt; setup_diva_common()
987 ISACVersion(cs, "Diva:"); setup_diva_common()
988 if (HscxVersion(cs, "Diva:")) { setup_diva_common()
991 release_io_diva(cs); setup_diva_common()
1002 struct IsdnCardState *cs = card->cs; setup_diva_isa() local
1008 cs->hw.diva.ctrl_reg = 0; setup_diva_isa()
1009 cs->hw.diva.cfg_reg = card->para[1]; setup_diva_isa()
1010 val = readreg(cs->hw.diva.cfg_reg + DIVA_IPAC_ADR, setup_diva_isa()
1011 cs->hw.diva.cfg_reg + DIVA_IPAC_DATA, IPAC_ID); setup_diva_isa()
1014 cs->subtyp = DIVA_IPAC_ISA; setup_diva_isa()
1015 cs->hw.diva.ctrl = 0; setup_diva_isa()
1016 cs->hw.diva.isac = card->para[1] + DIVA_IPAC_DATA; setup_diva_isa()
1017 cs->hw.diva.hscx = card->para[1] + DIVA_IPAC_DATA; setup_diva_isa()
1018 cs->hw.diva.isac_adr = card->para[1] + DIVA_IPAC_ADR; setup_diva_isa()
1019 cs->hw.diva.hscx_adr = card->para[1] + DIVA_IPAC_ADR; setup_diva_isa()
1020 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_diva_isa()
1022 cs->subtyp = DIVA_ISA; setup_diva_isa()
1023 cs->hw.diva.ctrl = card->para[1] + DIVA_ISA_CTRL; setup_diva_isa()
1024 cs->hw.diva.isac = card->para[1] + DIVA_ISA_ISAC_DATA; setup_diva_isa()
1025 cs->hw.diva.hscx = card->para[1] + DIVA_HSCX_DATA; setup_diva_isa()
1026 cs->hw.diva.isac_adr = card->para[1] + DIVA_ISA_ISAC_ADR; setup_diva_isa()
1027 cs->hw.diva.hscx_adr = card->para[1] + DIVA_HSCX_ADR; setup_diva_isa()
1029 cs->irq = card->para[0]; setup_diva_isa()
1071 struct IsdnCardState *cs = card->cs; setup_diva_isapnp() local
1102 cs->hw.diva.cfg_reg = card->para[1]; setup_diva_isapnp()
1103 cs->irq = card->para[0]; setup_diva_isapnp()
1105 cs->subtyp = DIVA_IPAC_ISA; setup_diva_isapnp()
1106 cs->hw.diva.ctrl = 0; setup_diva_isapnp()
1107 cs->hw.diva.isac = setup_diva_isapnp()
1109 cs->hw.diva.hscx = setup_diva_isapnp()
1111 cs->hw.diva.isac_adr = setup_diva_isapnp()
1113 cs->hw.diva.hscx_adr = setup_diva_isapnp()
1115 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_diva_isapnp()
1117 cs->subtyp = DIVA_ISA; setup_diva_isapnp()
1118 cs->hw.diva.ctrl = setup_diva_isapnp()
1120 cs->hw.diva.isac = setup_diva_isapnp()
1122 cs->hw.diva.hscx = setup_diva_isapnp()
1124 cs->hw.diva.isac_adr = setup_diva_isapnp()
1126 cs->hw.diva.hscx_adr = setup_diva_isapnp()
1159 struct IsdnCardState *cs = card->cs; setup_diva_pci() local
1161 cs->subtyp = 0; setup_diva_pci()
1166 cs->subtyp = DIVA_PCI; setup_diva_pci()
1167 cs->irq = dev_diva->irq; setup_diva_pci()
1168 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva, 2); setup_diva_pci()
1173 cs->subtyp = DIVA_PCI; setup_diva_pci()
1174 cs->irq = dev_diva_u->irq; setup_diva_pci()
1175 cs->hw.diva.cfg_reg = pci_resource_start(dev_diva_u, 2); setup_diva_pci()
1180 cs->subtyp = DIVA_IPAC_PCI; setup_diva_pci()
1181 cs->irq = dev_diva201->irq; setup_diva_pci()
1182 cs->hw.diva.pci_cfg = setup_diva_pci()
1184 cs->hw.diva.cfg_reg = setup_diva_pci()
1190 cs->subtyp = DIVA_IPACX_PCI; setup_diva_pci()
1191 cs->irq = dev_diva202->irq; setup_diva_pci()
1192 cs->hw.diva.pci_cfg = setup_diva_pci()
1194 cs->hw.diva.cfg_reg = setup_diva_pci()
1200 if (!cs->irq) { setup_diva_pci()
1202 iounmap_diva(cs); setup_diva_pci()
1206 if (!cs->hw.diva.cfg_reg) { setup_diva_pci()
1208 iounmap_diva(cs); setup_diva_pci()
1211 cs->irq_flags |= IRQF_SHARED; setup_diva_pci()
1213 if ((cs->subtyp == DIVA_IPAC_PCI) || setup_diva_pci()
1214 (cs->subtyp == DIVA_IPACX_PCI)) { setup_diva_pci()
1215 cs->hw.diva.ctrl = 0; setup_diva_pci()
1216 cs->hw.diva.isac = 0; setup_diva_pci()
1217 cs->hw.diva.hscx = 0; setup_diva_pci()
1218 cs->hw.diva.isac_adr = 0; setup_diva_pci()
1219 cs->hw.diva.hscx_adr = 0; setup_diva_pci()
1220 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_diva_pci()
1222 cs->hw.diva.ctrl = cs->hw.diva.cfg_reg + DIVA_PCI_CTRL; setup_diva_pci()
1223 cs->hw.diva.isac = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_DATA; setup_diva_pci()
1224 cs->hw.diva.hscx = cs->hw.diva.cfg_reg + DIVA_HSCX_DATA; setup_diva_pci()
1225 cs->hw.diva.isac_adr = cs->hw.diva.cfg_reg + DIVA_PCI_ISAC_ADR; setup_diva_pci()
1226 cs->hw.diva.hscx_adr = cs->hw.diva.cfg_reg + DIVA_HSCX_ADR; setup_diva_pci()
1244 struct IsdnCardState *cs = card->cs; setup_diva() local
1249 if (cs->typ != ISDN_CTYPE_DIEHLDIVA) setup_diva()
1251 cs->hw.diva.status = 0; setup_diva()
1281 return setup_diva_common(card->cs); setup_diva()
|
| H A D | jade.c | 24 JadeVersion(struct IsdnCardState *cs, char *s) JadeVersion() argument
28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); JadeVersion()
31 ver = cs->BC_Read_Reg(cs, -1, 0x60); JadeVersion()
43 ver = cs->BC_Read_Reg(cs, -1, 0x60); JadeVersion()
50 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value) jade_write_indirect() argument
56 cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value); jade_write_indirect()
58 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); jade_write_indirect()
63 ret = cs->BC_Read_Reg(cs, -1, COMM_JADE); jade_write_indirect()
80 struct IsdnCardState *cs = bcs->cs; modejade() local
83 if (cs->debug & L1_DEB_HSCX) { modejade()
84 debugl1(cs, "jade %c mode %d ichan %d", 'A' + jade, mode, bc); modejade()
89 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO : 0x00)); modejade()
90 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU | jadeCCR0_ITF)); modejade()
91 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00); modejade()
93 jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08); modejade()
94 jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08); modejade()
95 jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00); modejade()
96 jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00); modejade()
98 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07); modejade()
99 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07); modejade()
102 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00); modejade()
103 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00); modejade()
105 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04); modejade()
106 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04); modejade()
110 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO); modejade()
113 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO | jadeMODE_RAC | jadeMODE_XAC)); modejade()
116 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC | jadeMODE_XAC)); modejade()
120 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES | jadeRCMD_RMC)); modejade()
121 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES); modejade()
123 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8); modejade()
127 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00); modejade()
139 spin_lock_irqsave(&bcs->cs->lock, flags); jade_l2l1()
146 bcs->cs->BC_Send_Data(bcs); jade_l2l1()
148 spin_unlock_irqrestore(&bcs->cs->lock, flags); jade_l2l1()
151 spin_lock_irqsave(&bcs->cs->lock, flags); jade_l2l1()
158 bcs->cs->BC_Send_Data(bcs); jade_l2l1()
160 spin_unlock_irqrestore(&bcs->cs->lock, flags); jade_l2l1()
170 spin_lock_irqsave(&bcs->cs->lock, flags); jade_l2l1()
173 spin_unlock_irqrestore(&bcs->cs->lock, flags); jade_l2l1()
180 spin_lock_irqsave(&bcs->cs->lock, flags); jade_l2l1()
184 spin_unlock_irqrestore(&bcs->cs->lock, flags); jade_l2l1()
210 open_jadestate(struct IsdnCardState *cs, struct BCState *bcs) open_jadestate() argument
254 clear_pending_jade_ints(struct IsdnCardState *cs) clear_pending_jade_ints() argument
258 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); clear_pending_jade_ints()
259 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); clear_pending_jade_ints()
261 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR); clear_pending_jade_ints()
262 debugl1(cs, "jade B ISTA %x", val); clear_pending_jade_ints()
263 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR); clear_pending_jade_ints()
264 debugl1(cs, "jade A ISTA %x", val); clear_pending_jade_ints()
265 val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR); clear_pending_jade_ints()
266 debugl1(cs, "jade B STAR %x", val); clear_pending_jade_ints()
267 val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR); clear_pending_jade_ints()
268 debugl1(cs, "jade A STAR %x", val); clear_pending_jade_ints()
270 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8); clear_pending_jade_ints()
271 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8); clear_pending_jade_ints()
275 initjade(struct IsdnCardState *cs) initjade() argument
277 cs->bcs[0].BC_SetStack = setstack_jade; initjade()
278 cs->bcs[1].BC_SetStack = setstack_jade; initjade()
279 cs->bcs[0].BC_Close = close_jadestate; initjade()
280 cs->bcs[1].BC_Close = close_jadestate; initjade()
281 cs->bcs[0].hw.hscx.hscx = 0; initjade()
282 cs->bcs[1].hw.hscx.hscx = 1; initjade()
285 jade_write_indirect(cs, 0x11, 0x0f); initjade()
286 jade_write_indirect(cs, 0x17, 0x2f); initjade()
289 cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO); initjade()
290 cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO); initjade()
292 cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00); initjade()
293 cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00); initjade()
295 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); initjade()
296 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); initjade()
298 jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1 | jadeINDIRECT_HAH2)); initjade()
300 cs->BC_Write_Reg(cs, -1, jade_INT, (jadeINT_HDLC1 | jadeINT_HDLC2)); initjade()
303 modejade(cs->bcs, 0, 0); initjade()
304 modejade(cs->bcs + 1, 0, 0); initjade()
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| H A D | isurf.c | 37 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
39 return (readb(cs->hw.isurf.isac + offset)); ReadISAC()
43 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
45 writeb(value, cs->hw.isurf.isac + offset); mb(); WriteISAC()
49 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
53 data[i] = readb(cs->hw.isurf.isac); ReadISACfifo()
57 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
61 writeb(data[i], cs->hw.isurf.isac); mb(); WriteISACfifo()
72 ReadISAR(struct IsdnCardState *cs, int mode, u_char offset) ReadISAR() argument
74 return (readb(cs->hw.isurf.isar + offset)); ReadISAR()
78 WriteISAR(struct IsdnCardState *cs, int mode, u_char offset, u_char value) WriteISAR() argument
80 writeb(value, cs->hw.isurf.isar + offset); mb(); WriteISAR()
86 struct IsdnCardState *cs = dev_id; isurf_interrupt() local
91 spin_lock_irqsave(&cs->lock, flags); isurf_interrupt()
92 val = readb(cs->hw.isurf.isar + ISAR_IRQBIT); isurf_interrupt()
95 isar_int_main(cs); isurf_interrupt()
96 val = readb(cs->hw.isurf.isac + ISAC_ISTA); isurf_interrupt()
99 isac_interrupt(cs, val); isurf_interrupt()
100 val = readb(cs->hw.isurf.isar + ISAR_IRQBIT); isurf_interrupt()
102 if (cs->debug & L1_DEB_HSCX) isurf_interrupt()
103 debugl1(cs, "ISAR IntStat after IntRoutine"); isurf_interrupt()
106 val = readb(cs->hw.isurf.isac + ISAC_ISTA); isurf_interrupt()
108 if (cs->debug & L1_DEB_ISAC) isurf_interrupt()
109 debugl1(cs, "ISAC IntStat after IntRoutine"); isurf_interrupt()
115 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); isurf_interrupt()
116 writeb(0xFF, cs->hw.isurf.isac + ISAC_MASK); mb(); isurf_interrupt()
117 writeb(0, cs->hw.isurf.isac + ISAC_MASK); mb(); isurf_interrupt()
118 writeb(ISAR_IRQMSK, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); isurf_interrupt()
119 spin_unlock_irqrestore(&cs->lock, flags); isurf_interrupt()
124 release_io_isurf(struct IsdnCardState *cs) release_io_isurf() argument
126 release_region(cs->hw.isurf.reset, 1); release_io_isurf()
127 iounmap(cs->hw.isurf.isar); release_io_isurf()
128 release_mem_region(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE); release_io_isurf()
132 reset_isurf(struct IsdnCardState *cs, u_char chips) reset_isurf() argument
136 byteout(cs->hw.isurf.reset, chips); /* Reset On */ reset_isurf()
138 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */ reset_isurf()
143 ISurf_card_msg(struct IsdnCardState *cs, int mt, void *arg) ISurf_card_msg() argument
149 spin_lock_irqsave(&cs->lock, flags); ISurf_card_msg()
150 reset_isurf(cs, ISURF_RESET); ISurf_card_msg()
151 spin_unlock_irqrestore(&cs->lock, flags); ISurf_card_msg()
154 release_io_isurf(cs); ISurf_card_msg()
157 spin_lock_irqsave(&cs->lock, flags); ISurf_card_msg()
158 reset_isurf(cs, ISURF_RESET); ISurf_card_msg()
159 clear_pending_isac_ints(cs); ISurf_card_msg()
160 writeb(0, cs->hw.isurf.isar + ISAR_IRQBIT); mb(); ISurf_card_msg()
161 initisac(cs); ISurf_card_msg()
162 initisar(cs); ISurf_card_msg()
164 cs->writeisac(cs, ISAC_MASK, 0); ISurf_card_msg()
166 cs->writeisac(cs, ISAC_CMDR, 0x41); ISurf_card_msg()
167 spin_unlock_irqrestore(&cs->lock, flags); ISurf_card_msg()
176 isurf_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) { isurf_auxcmd() argument
181 ret = isar_auxcmd(cs, ic); isurf_auxcmd()
182 spin_lock_irqsave(&cs->lock, flags); isurf_auxcmd()
184 reset_isurf(cs, ISURF_ISAR_EA | ISURF_ISAC_RESET | isurf_auxcmd()
186 initisac(cs); isurf_auxcmd()
187 cs->writeisac(cs, ISAC_MASK, 0); isurf_auxcmd()
188 cs->writeisac(cs, ISAC_CMDR, 0x41); isurf_auxcmd()
190 spin_unlock_irqrestore(&cs->lock, flags); isurf_auxcmd()
193 return (isar_auxcmd(cs, ic)); isurf_auxcmd()
203 struct IsdnCardState *cs = card->cs; setup_isurf() local
209 if (cs->typ != ISDN_CTYPE_ISURF) setup_isurf()
212 cs->hw.isurf.reset = card->para[1]; setup_isurf()
213 cs->hw.isurf.phymem = card->para[2]; setup_isurf()
214 cs->irq = card->para[0]; setup_isurf()
221 cs->subtyp = 0; setup_isurf()
238 cs->hw.isurf.reset = pnp_port_start(pnp_d, 0); setup_isurf()
239 cs->hw.isurf.phymem = pnp_mem_start(pnp_d, 1); setup_isurf()
240 cs->irq = pnp_irq(pnp_d, 0); setup_isurf()
241 if (!cs->irq || !cs->hw.isurf.reset || !cs->hw.isurf.phymem) { setup_isurf()
243 cs->irq, cs->hw.isurf.reset, cs->hw.isurf.phymem); setup_isurf()
260 if (!request_region(cs->hw.isurf.reset, 1, "isurf isdn")) { setup_isurf()
263 cs->hw.isurf.reset); setup_isurf()
266 if (!request_region(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE, "isurf iomem")) { setup_isurf()
269 cs->hw.isurf.phymem, setup_isurf()
270 cs->hw.isurf.phymem + ISURF_IOMEM_SIZE); setup_isurf()
271 release_region(cs->hw.isurf.reset, 1); setup_isurf()
274 cs->hw.isurf.isar = ioremap(cs->hw.isurf.phymem, ISURF_IOMEM_SIZE); setup_isurf()
275 cs->hw.isurf.isac = cs->hw.isurf.isar + ISURF_ISAC_OFFSET; setup_isurf()
278 cs->hw.isurf.reset, setup_isurf()
279 cs->hw.isurf.phymem, setup_isurf()
280 cs->irq); setup_isurf()
282 setup_isac(cs); setup_isurf()
283 cs->cardmsg = &ISurf_card_msg; setup_isurf()
284 cs->irq_func = &isurf_interrupt; setup_isurf()
285 cs->auxcmd = &isurf_auxcmd; setup_isurf()
286 cs->readisac = &ReadISAC; setup_isurf()
287 cs->writeisac = &WriteISAC; setup_isurf()
288 cs->readisacfifo = &ReadISACfifo; setup_isurf()
289 cs->writeisacfifo = &WriteISACfifo; setup_isurf()
290 cs->bcs[0].hw.isar.reg = &cs->hw.isurf.isar_r; setup_isurf()
291 cs->bcs[1].hw.isar.reg = &cs->hw.isurf.isar_r; setup_isurf()
292 test_and_set_bit(HW_ISAR, &cs->HW_Flags); setup_isurf()
293 ISACVersion(cs, "ISurf:"); setup_isurf()
294 cs->BC_Read_Reg = &ReadISAR; setup_isurf()
295 cs->BC_Write_Reg = &WriteISAR; setup_isurf()
296 cs->BC_Send_Data = &isar_fill_fifo; setup_isurf()
297 ver = ISARVersion(cs, "ISurf:"); setup_isurf()
301 release_io_isurf(cs); setup_isurf()
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| H A D | nj_s.c | 19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) dummywr() argument
31 struct IsdnCardState *cs = dev_id; netjet_s_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); netjet_s_interrupt()
36 s1val = bytein(cs->hw.njet.base + NETJET_IRQSTAT1); netjet_s_interrupt()
38 val = NETjet_ReadIC(cs, ISAC_ISTA); netjet_s_interrupt()
39 if (cs->debug & L1_DEB_ISAC) netjet_s_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", s1val, val); netjet_s_interrupt()
42 isac_interrupt(cs, val); netjet_s_interrupt()
43 NETjet_WriteIC(cs, ISAC_MASK, 0xFF); netjet_s_interrupt()
44 NETjet_WriteIC(cs, ISAC_MASK, 0x0); netjet_s_interrupt()
55 s0val = bytein(cs->hw.njet.base + NETJET_IRQSTAT0); netjet_s_interrupt()
57 spin_unlock_irqrestore(&cs->lock, flags); netjet_s_interrupt()
61 byteout(cs->hw.njet.base + NETJET_IRQSTAT0, s0val); netjet_s_interrupt()
64 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < netjet_s_interrupt()
65 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) netjet_s_interrupt()
70 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < netjet_s_interrupt()
71 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) netjet_s_interrupt()
76 if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */ netjet_s_interrupt()
78 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { netjet_s_interrupt()
80 cs->hw.njet.last_is0, s0val); netjet_s_interrupt()
81 spin_unlock_irqrestore(&cs->lock, flags); netjet_s_interrupt()
84 cs->hw.njet.irqstat0 = s0val; netjet_s_interrupt()
85 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != netjet_s_interrupt()
86 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) netjet_s_interrupt()
88 read_tiger(cs); netjet_s_interrupt()
89 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != netjet_s_interrupt()
90 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) netjet_s_interrupt()
92 write_tiger(cs); netjet_s_interrupt()
94 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); netjet_s_interrupt()
96 spin_unlock_irqrestore(&cs->lock, flags); netjet_s_interrupt()
101 reset_netjet_s(struct IsdnCardState *cs) reset_netjet_s() argument
103 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_s()
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_s()
108 if (cs->subtyp) /* TJ320 */ reset_netjet_s()
109 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_s()
111 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ reset_netjet_s()
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_s()
114 cs->hw.njet.auxd = 0; reset_netjet_s()
115 cs->hw.njet.dmactrl = 0; reset_netjet_s()
116 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); reset_netjet_s()
117 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); reset_netjet_s()
118 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); reset_netjet_s()
122 NETjet_S_card_msg(struct IsdnCardState *cs, int mt, void *arg) NETjet_S_card_msg() argument
128 spin_lock_irqsave(&cs->lock, flags); NETjet_S_card_msg()
129 reset_netjet_s(cs); NETjet_S_card_msg()
130 spin_unlock_irqrestore(&cs->lock, flags); NETjet_S_card_msg()
133 release_io_netjet(cs); NETjet_S_card_msg()
136 reset_netjet_s(cs); NETjet_S_card_msg()
137 inittiger(cs); NETjet_S_card_msg()
138 spin_lock_irqsave(&cs->lock, flags); NETjet_S_card_msg()
139 clear_pending_isac_ints(cs); NETjet_S_card_msg()
140 initisac(cs); NETjet_S_card_msg()
142 cs->writeisac(cs, ISAC_MASK, 0); NETjet_S_card_msg()
143 spin_unlock_irqrestore(&cs->lock, flags); NETjet_S_card_msg()
151 static int njs_pci_probe(struct pci_dev *dev_netjet, struct IsdnCardState *cs) njs_pci_probe() argument
158 cs->irq = dev_netjet->irq; njs_pci_probe()
159 if (!cs->irq) { njs_pci_probe()
163 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); njs_pci_probe()
164 if (!cs->hw.njet.base) { njs_pci_probe()
174 cs->subtyp = 1; /* TJ320 */ njs_pci_probe()
176 cs->subtyp = 0; /* TJ300 */ njs_pci_probe()
189 static int njs_cs_init(struct IsdnCard *card, struct IsdnCardState *cs) njs_cs_init() argument
192 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; njs_cs_init()
193 cs->hw.njet.isac = cs->hw.njet.base | NETJET_ISAC_OFF; njs_cs_init()
195 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ njs_cs_init()
196 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); njs_cs_init()
199 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ njs_cs_init()
200 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); njs_cs_init()
203 cs->hw.njet.auxd = 0xC0; njs_cs_init()
204 cs->hw.njet.dmactrl = 0; njs_cs_init()
206 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); njs_cs_init()
207 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); njs_cs_init()
208 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); njs_cs_init()
210 switch (((NETjet_ReadIC(cs, ISAC_RBCH) >> 5) & 3)) njs_cs_init()
226 static int njs_cs_init_rest(struct IsdnCard *card, struct IsdnCardState *cs) njs_cs_init_rest() argument
232 cs->subtyp ? "TJ320" : "TJ300", cs->hw.njet.base, cs->irq); njs_cs_init_rest()
233 if (!request_region(cs->hw.njet.base, bytecnt, "netjet-s isdn")) { njs_cs_init_rest()
236 cs->hw.njet.base, njs_cs_init_rest()
237 cs->hw.njet.base + bytecnt); njs_cs_init_rest()
240 cs->readisac = &NETjet_ReadIC; njs_cs_init_rest()
241 cs->writeisac = &NETjet_WriteIC; njs_cs_init_rest()
242 cs->readisacfifo = &NETjet_ReadICfifo; njs_cs_init_rest()
243 cs->writeisacfifo = &NETjet_WriteICfifo; njs_cs_init_rest()
244 cs->BC_Read_Reg = &dummyrr; njs_cs_init_rest()
245 cs->BC_Write_Reg = &dummywr; njs_cs_init_rest()
246 cs->BC_Send_Data = &netjet_fill_dma; njs_cs_init_rest()
247 setup_isac(cs); njs_cs_init_rest()
248 cs->cardmsg = &NETjet_S_card_msg; njs_cs_init_rest()
249 cs->irq_func = &netjet_s_interrupt; njs_cs_init_rest()
250 cs->irq_flags |= IRQF_SHARED; njs_cs_init_rest()
251 ISACVersion(cs, "NETjet-S:"); njs_cs_init_rest()
261 struct IsdnCardState *cs = card->cs; setup_netjet_s() local
269 if (cs->typ != ISDN_CTYPE_NETJET_S) setup_netjet_s()
271 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); setup_netjet_s()
277 ret = njs_pci_probe(dev_netjet, cs); setup_netjet_s()
285 ret = njs_cs_init(card, cs); setup_netjet_s()
293 return njs_cs_init_rest(card, cs); setup_netjet_s()
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| H A D | niccy.c | 78 static u_char ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); ReadISAC()
83 static void WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); WriteISAC()
88 static void ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
90 readfifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); ReadISACfifo()
93 static void WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
95 writefifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); WriteISACfifo()
98 static u_char ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
100 return readreg(cs->hw.niccy.hscx_ale, ReadHSCX()
101 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0)); ReadHSCX()
104 static void WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, WriteHSCX() argument
107 writereg(cs->hw.niccy.hscx_ale, WriteHSCX()
108 cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
111 #define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \
112 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
113 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
114 cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0), data)
116 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.niccy.hscx_ale, \
117 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
119 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.niccy.hscx_ale, \
120 cs->hw.niccy.hscx, (nr ? 0x40 : 0), ptr, cnt)
126 struct IsdnCardState *cs = dev_id; niccy_interrupt() local
130 spin_lock_irqsave(&cs->lock, flags); niccy_interrupt()
131 if (cs->subtyp == NICCY_PCI) { niccy_interrupt()
133 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_interrupt()
135 spin_unlock_irqrestore(&cs->lock, flags); niccy_interrupt()
138 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_interrupt()
140 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt()
144 hscx_int_main(cs, val); niccy_interrupt()
145 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); niccy_interrupt()
148 isac_interrupt(cs, val); niccy_interrupt()
149 val = readreg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, niccy_interrupt()
152 if (cs->debug & L1_DEB_HSCX) niccy_interrupt()
153 debugl1(cs, "HSCX IntStat after IntRoutine"); niccy_interrupt()
156 val = readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_ISTA); niccy_interrupt()
158 if (cs->debug & L1_DEB_ISAC) niccy_interrupt()
159 debugl1(cs, "ISAC IntStat after IntRoutine"); niccy_interrupt()
162 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); niccy_interrupt()
163 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, niccy_interrupt()
165 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); niccy_interrupt()
166 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); niccy_interrupt()
167 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); niccy_interrupt()
168 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); niccy_interrupt()
169 spin_unlock_irqrestore(&cs->lock, flags); niccy_interrupt()
173 static void release_io_niccy(struct IsdnCardState *cs) release_io_niccy() argument
175 if (cs->subtyp == NICCY_PCI) { release_io_niccy()
178 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); release_io_niccy()
180 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); release_io_niccy()
181 release_region(cs->hw.niccy.cfg_reg, 0x40); release_io_niccy()
182 release_region(cs->hw.niccy.isac, 4); release_io_niccy()
184 release_region(cs->hw.niccy.isac, 2); release_io_niccy()
185 release_region(cs->hw.niccy.isac_ale, 2); release_io_niccy()
189 static void niccy_reset(struct IsdnCardState *cs) niccy_reset() argument
191 if (cs->subtyp == NICCY_PCI) { niccy_reset()
194 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_reset()
196 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); niccy_reset()
198 inithscxisac(cs, 3); niccy_reset()
201 static int niccy_card_msg(struct IsdnCardState *cs, int mt, void *arg) niccy_card_msg() argument
207 spin_lock_irqsave(&cs->lock, flags); niccy_card_msg()
208 niccy_reset(cs); niccy_card_msg()
209 spin_unlock_irqrestore(&cs->lock, flags); niccy_card_msg()
212 release_io_niccy(cs); niccy_card_msg()
215 spin_lock_irqsave(&cs->lock, flags); niccy_card_msg()
216 niccy_reset(cs); niccy_card_msg()
217 spin_unlock_irqrestore(&cs->lock, flags); niccy_card_msg()
231 struct IsdnCardState *cs = card->cs; setup_niccy() local
236 if (cs->typ != ISDN_CTYPE_NICCY) setup_niccy()
278 cs->hw.niccy.isac = card->para[1] + ISAC_PNP; setup_niccy()
279 cs->hw.niccy.hscx = card->para[1] + HSCX_PNP; setup_niccy()
280 cs->hw.niccy.isac_ale = card->para[2] + ISAC_PNP; setup_niccy()
281 cs->hw.niccy.hscx_ale = card->para[2] + HSCX_PNP; setup_niccy()
282 cs->hw.niccy.cfg_reg = 0; setup_niccy()
283 cs->subtyp = NICCY_PNP; setup_niccy()
284 cs->irq = card->para[0]; setup_niccy()
285 if (!request_region(cs->hw.niccy.isac, 2, "niccy data")) { setup_niccy()
288 cs->hw.niccy.isac, cs->hw.niccy.isac + 1); setup_niccy()
291 if (!request_region(cs->hw.niccy.isac_ale, 2, "niccy addr")) { setup_niccy()
294 cs->hw.niccy.isac_ale, setup_niccy()
295 cs->hw.niccy.isac_ale + 1); setup_niccy()
296 release_region(cs->hw.niccy.isac, 2); setup_niccy()
304 cs->subtyp = 0; setup_niccy()
316 cs->irq = niccy_dev->irq; setup_niccy()
317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0); setup_niccy()
318 if (!cs->hw.niccy.cfg_reg) { setup_niccy()
329 cs->subtyp = NICCY_PCI; setup_niccy()
334 cs->irq_flags |= IRQF_SHARED; setup_niccy()
335 cs->hw.niccy.isac = pci_ioaddr + ISAC_PCI_DATA; setup_niccy()
336 cs->hw.niccy.isac_ale = pci_ioaddr + ISAC_PCI_ADDR; setup_niccy()
337 cs->hw.niccy.hscx = pci_ioaddr + HSCX_PCI_DATA; setup_niccy()
338 cs->hw.niccy.hscx_ale = pci_ioaddr + HSCX_PCI_ADDR; setup_niccy()
339 if (!request_region(cs->hw.niccy.isac, 4, "niccy")) { setup_niccy()
342 cs->hw.niccy.isac, cs->hw.niccy.isac + 4); setup_niccy()
345 if (!request_region(cs->hw.niccy.cfg_reg, 0x40, "niccy pci")) { setup_niccy()
348 cs->hw.niccy.cfg_reg, setup_niccy()
349 cs->hw.niccy.cfg_reg + 0x40); setup_niccy()
350 release_region(cs->hw.niccy.isac, 4); setup_niccy()
360 (cs->subtyp == 1) ? "PnP" : "PCI", setup_niccy()
361 cs->irq, cs->hw.niccy.isac, cs->hw.niccy.isac_ale); setup_niccy()
362 setup_isac(cs); setup_niccy()
363 cs->readisac = &ReadISAC; setup_niccy()
364 cs->writeisac = &WriteISAC; setup_niccy()
365 cs->readisacfifo = &ReadISACfifo; setup_niccy()
366 cs->writeisacfifo = &WriteISACfifo; setup_niccy()
367 cs->BC_Read_Reg = &ReadHSCX; setup_niccy()
368 cs->BC_Write_Reg = &WriteHSCX; setup_niccy()
369 cs->BC_Send_Data = &hscx_fill_fifo; setup_niccy()
370 cs->cardmsg = &niccy_card_msg; setup_niccy()
371 cs->irq_func = &niccy_interrupt; setup_niccy()
372 ISACVersion(cs, "Niccy:"); setup_niccy()
373 if (HscxVersion(cs, "Niccy:")) { setup_niccy()
376 release_io_niccy(cs); setup_niccy()
|
| H A D | nj_u.c | 19 static u_char dummyrr(struct IsdnCardState *cs, int chan, u_char off) dummyrr() argument
24 static void dummywr(struct IsdnCardState *cs, int chan, u_char off, u_char value) dummywr() argument
31 struct IsdnCardState *cs = dev_id; netjet_u_interrupt() local
35 spin_lock_irqsave(&cs->lock, flags); netjet_u_interrupt()
36 if (!((sval = bytein(cs->hw.njet.base + NETJET_IRQSTAT1)) & netjet_u_interrupt()
38 val = NETjet_ReadIC(cs, ICC_ISTA); netjet_u_interrupt()
39 if (cs->debug & L1_DEB_ISAC) netjet_u_interrupt()
40 debugl1(cs, "tiger: i1 %x %x", sval, val); netjet_u_interrupt()
42 icc_interrupt(cs, val); netjet_u_interrupt()
43 NETjet_WriteIC(cs, ICC_MASK, 0xFF); netjet_u_interrupt()
44 NETjet_WriteIC(cs, ICC_MASK, 0x0); netjet_u_interrupt()
49 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < netjet_u_interrupt()
50 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) netjet_u_interrupt()
55 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < netjet_u_interrupt()
56 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) netjet_u_interrupt()
61 if (sval != cs->hw.njet.last_is0) /* we have a DMA interrupt */ netjet_u_interrupt()
63 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { netjet_u_interrupt()
64 spin_unlock_irqrestore(&cs->lock, flags); netjet_u_interrupt()
67 cs->hw.njet.irqstat0 = sval; netjet_u_interrupt()
68 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != netjet_u_interrupt()
69 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) netjet_u_interrupt()
71 read_tiger(cs); netjet_u_interrupt()
72 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != netjet_u_interrupt()
73 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) netjet_u_interrupt()
75 write_tiger(cs); netjet_u_interrupt()
77 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); netjet_u_interrupt()
79 spin_unlock_irqrestore(&cs->lock, flags); netjet_u_interrupt()
84 reset_netjet_u(struct IsdnCardState *cs) reset_netjet_u() argument
86 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ reset_netjet_u()
87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_u()
89 cs->hw.njet.ctrl_reg = 0x40; /* Reset Off and status read clear */ reset_netjet_u()
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); reset_netjet_u()
93 cs->hw.njet.auxd = 0xC0; reset_netjet_u()
94 cs->hw.njet.dmactrl = 0; reset_netjet_u()
95 byteout(cs->hw.njet.auxa, 0); reset_netjet_u()
96 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); reset_netjet_u()
97 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); reset_netjet_u()
98 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); reset_netjet_u()
102 NETjet_U_card_msg(struct IsdnCardState *cs, int mt, void *arg) NETjet_U_card_msg() argument
108 spin_lock_irqsave(&cs->lock, flags); NETjet_U_card_msg()
109 reset_netjet_u(cs); NETjet_U_card_msg()
110 spin_unlock_irqrestore(&cs->lock, flags); NETjet_U_card_msg()
113 release_io_netjet(cs); NETjet_U_card_msg()
116 spin_lock_irqsave(&cs->lock, flags); NETjet_U_card_msg()
117 inittiger(cs); NETjet_U_card_msg()
118 reset_netjet_u(cs); NETjet_U_card_msg()
119 clear_pending_icc_ints(cs); NETjet_U_card_msg()
120 initicc(cs); NETjet_U_card_msg()
122 cs->writeisac(cs, ICC_MASK, 0); NETjet_U_card_msg()
123 spin_unlock_irqrestore(&cs->lock, flags); NETjet_U_card_msg()
131 static int nju_pci_probe(struct pci_dev *dev_netjet, struct IsdnCardState *cs) nju_pci_probe() argument
136 cs->irq = dev_netjet->irq; nju_pci_probe()
137 if (!cs->irq) { nju_pci_probe()
141 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); nju_pci_probe()
142 if (!cs->hw.njet.base) { nju_pci_probe()
150 static int nju_cs_init(struct IsdnCard *card, struct IsdnCardState *cs) nju_cs_init() argument
152 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; nju_cs_init()
153 cs->hw.njet.isac = cs->hw.njet.base | NETJET_ISAC_OFF; nju_cs_init()
156 cs->hw.njet.ctrl_reg = 0xff; /* Reset On */ nju_cs_init()
157 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); nju_cs_init()
160 cs->hw.njet.ctrl_reg = 0x00; /* Reset Off and status read clear */ nju_cs_init()
161 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); nju_cs_init()
164 cs->hw.njet.auxd = 0xC0; nju_cs_init()
165 cs->hw.njet.dmactrl = 0; nju_cs_init()
167 byteout(cs->hw.njet.auxa, 0); nju_cs_init()
168 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); nju_cs_init()
169 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); nju_cs_init()
170 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); nju_cs_init()
172 switch (((NETjet_ReadIC(cs, ICC_RBCH) >> 5) & 3)) nju_cs_init()
188 static int nju_cs_init_rest(struct IsdnCard *card, struct IsdnCardState *cs) nju_cs_init_rest() argument
194 cs->hw.njet.base, cs->irq); nju_cs_init_rest()
195 if (!request_region(cs->hw.njet.base, bytecnt, "netspider-u isdn")) { nju_cs_init_rest()
199 cs->hw.njet.base, nju_cs_init_rest()
200 cs->hw.njet.base + bytecnt); nju_cs_init_rest()
203 setup_icc(cs); nju_cs_init_rest()
204 cs->readisac = &NETjet_ReadIC; nju_cs_init_rest()
205 cs->writeisac = &NETjet_WriteIC; nju_cs_init_rest()
206 cs->readisacfifo = &NETjet_ReadICfifo; nju_cs_init_rest()
207 cs->writeisacfifo = &NETjet_WriteICfifo; nju_cs_init_rest()
208 cs->BC_Read_Reg = &dummyrr; nju_cs_init_rest()
209 cs->BC_Write_Reg = &dummywr; nju_cs_init_rest()
210 cs->BC_Send_Data = &netjet_fill_dma; nju_cs_init_rest()
211 cs->cardmsg = &NETjet_U_card_msg; nju_cs_init_rest()
212 cs->irq_func = &netjet_u_interrupt; nju_cs_init_rest()
213 cs->irq_flags |= IRQF_SHARED; nju_cs_init_rest()
214 ICCVersion(cs, "NETspider-U:"); nju_cs_init_rest()
224 struct IsdnCardState *cs = card->cs; setup_netjet_u() local
233 if (cs->typ != ISDN_CTYPE_NETJET_U) setup_netjet_u()
235 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); setup_netjet_u()
241 ret = nju_pci_probe(dev_netjet, cs); setup_netjet_u()
249 ret = nju_cs_init(card, cs); setup_netjet_u()
257 return nju_cs_init_rest(card, cs); setup_netjet_u()
|
| H A D | ix1_micro.c | 76 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); ReadISAC()
82 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); WriteISAC()
88 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
90 readfifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); ReadISACfifo()
94 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
96 writefifo(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, 0, data, size); WriteISACfifo()
100 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
102 return (readreg(cs->hw.ix1.hscx_ale, ReadHSCX()
103 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
109 writereg(cs->hw.ix1.hscx_ale, WriteHSCX()
110 cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
113 #define READHSCX(cs, nr, reg) readreg(cs->hw.ix1.hscx_ale, \
114 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0))
115 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
116 cs->hw.ix1.hscx, reg + (nr ? 0x40 : 0), data)
118 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ix1.hscx_ale, \
119 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
121 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ix1.hscx_ale, \
122 cs->hw.ix1.hscx, (nr ? 0x40 : 0), ptr, cnt)
129 struct IsdnCardState *cs = dev_id; ix1micro_interrupt() local
133 spin_lock_irqsave(&cs->lock, flags); ix1micro_interrupt()
134 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt()
137 hscx_int_main(cs, val); ix1micro_interrupt()
138 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); ix1micro_interrupt()
141 isac_interrupt(cs, val); ix1micro_interrupt()
142 val = readreg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_ISTA + 0x40); ix1micro_interrupt()
144 if (cs->debug & L1_DEB_HSCX) ix1micro_interrupt()
145 debugl1(cs, "HSCX IntStat after IntRoutine"); ix1micro_interrupt()
148 val = readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_ISTA); ix1micro_interrupt()
150 if (cs->debug & L1_DEB_ISAC) ix1micro_interrupt()
151 debugl1(cs, "ISAC IntStat after IntRoutine"); ix1micro_interrupt()
154 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); ix1micro_interrupt()
155 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); ix1micro_interrupt()
156 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); ix1micro_interrupt()
157 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); ix1micro_interrupt()
158 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); ix1micro_interrupt()
159 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); ix1micro_interrupt()
160 spin_unlock_irqrestore(&cs->lock, flags); ix1micro_interrupt()
165 release_io_ix1micro(struct IsdnCardState *cs) release_io_ix1micro() argument
167 if (cs->hw.ix1.cfg_reg) release_io_ix1micro()
168 release_region(cs->hw.ix1.cfg_reg, 4); release_io_ix1micro()
172 ix1_reset(struct IsdnCardState *cs) ix1_reset() argument
179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); ix1_reset()
182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); ix1_reset()
186 ix1_card_msg(struct IsdnCardState *cs, int mt, void *arg) ix1_card_msg() argument
192 spin_lock_irqsave(&cs->lock, flags); ix1_card_msg()
193 ix1_reset(cs); ix1_card_msg()
194 spin_unlock_irqrestore(&cs->lock, flags); ix1_card_msg()
197 release_io_ix1micro(cs); ix1_card_msg()
200 spin_lock_irqsave(&cs->lock, flags); ix1_card_msg()
201 ix1_reset(cs); ix1_card_msg()
202 inithscxisac(cs, 3); ix1_card_msg()
203 spin_unlock_irqrestore(&cs->lock, flags); ix1_card_msg()
229 struct IsdnCardState *cs = card->cs; setup_ix1micro() local
234 if (cs->typ != ISDN_CTYPE_IX1MICROR2) setup_ix1micro()
280 cs->hw.ix1.isac_ale = card->para[1] + ISAC_COMMAND_OFFSET; setup_ix1micro()
281 cs->hw.ix1.hscx_ale = card->para[1] + HSCX_COMMAND_OFFSET; setup_ix1micro()
282 cs->hw.ix1.isac = card->para[1] + ISAC_DATA_OFFSET; setup_ix1micro()
283 cs->hw.ix1.hscx = card->para[1] + HSCX_DATA_OFFSET; setup_ix1micro()
284 cs->hw.ix1.cfg_reg = card->para[1]; setup_ix1micro()
285 cs->irq = card->para[0]; setup_ix1micro()
286 if (cs->hw.ix1.cfg_reg) { setup_ix1micro()
287 if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) { setup_ix1micro()
291 cs->hw.ix1.cfg_reg, setup_ix1micro()
292 cs->hw.ix1.cfg_reg + 4); setup_ix1micro()
297 cs->irq, cs->hw.ix1.cfg_reg); setup_ix1micro()
298 setup_isac(cs); setup_ix1micro()
299 cs->readisac = &ReadISAC; setup_ix1micro()
300 cs->writeisac = &WriteISAC; setup_ix1micro()
301 cs->readisacfifo = &ReadISACfifo; setup_ix1micro()
302 cs->writeisacfifo = &WriteISACfifo; setup_ix1micro()
303 cs->BC_Read_Reg = &ReadHSCX; setup_ix1micro()
304 cs->BC_Write_Reg = &WriteHSCX; setup_ix1micro()
305 cs->BC_Send_Data = &hscx_fill_fifo; setup_ix1micro()
306 cs->cardmsg = &ix1_card_msg; setup_ix1micro()
307 cs->irq_func = &ix1micro_interrupt; setup_ix1micro()
308 ISACVersion(cs, "ix1-Micro:"); setup_ix1micro()
309 if (HscxVersion(cs, "ix1-Micro:")) { setup_ix1micro()
312 release_io_ix1micro(cs); setup_ix1micro()
|
| H A D | elsa.c | 136 static void set_arcofi(struct IsdnCardState *cs, int bc);
176 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
178 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset)); ReadISAC()
182 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
184 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); WriteISAC()
188 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
190 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); ReadISACfifo()
194 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
196 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0, data, size); WriteISACfifo()
200 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) ReadISAC_IPAC() argument
202 return (readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset + 0x80)); ReadISAC_IPAC()
206 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC_IPAC() argument
208 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset | 0x80, value); WriteISAC_IPAC()
212 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo_IPAC() argument
214 readfifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); ReadISACfifo_IPAC()
218 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo_IPAC() argument
220 writefifo(cs->hw.elsa.ale, cs->hw.elsa.isac, 0x80, data, size); WriteISACfifo_IPAC()
224 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
226 return (readreg(cs->hw.elsa.ale, ReadHSCX()
227 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
231 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
233 writereg(cs->hw.elsa.ale, WriteHSCX()
234 cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
238 readitac(struct IsdnCardState *cs, u_char off) readitac() argument
242 byteout(cs->hw.elsa.ale, off); readitac()
243 ret = bytein(cs->hw.elsa.itac); readitac()
248 writeitac(struct IsdnCardState *cs, u_char off, u_char data) writeitac() argument
250 byteout(cs->hw.elsa.ale, off); writeitac()
251 byteout(cs->hw.elsa.itac, data); writeitac()
255 TimerRun(struct IsdnCardState *cs) TimerRun() argument
259 v = bytein(cs->hw.elsa.cfg); TimerRun()
260 if ((cs->subtyp == ELSA_QS1000) || (cs->subtyp == ELSA_QS3000)) TimerRun()
262 else if (cs->subtyp == ELSA_PCC8) TimerRun()
270 #define READHSCX(cs, nr, reg) readreg(cs->hw.elsa.ale, \
271 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0))
272 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \
273 cs->hw.elsa.hscx, reg + (nr ? 0x40 : 0), data)
275 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.elsa.ale, \
276 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
278 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.elsa.ale, \
279 cs->hw.elsa.hscx, (nr ? 0x40 : 0), ptr, cnt)
286 struct IsdnCardState *cs = dev_id; elsa_interrupt() local
291 if ((cs->typ == ISDN_CTYPE_ELSA_PCMCIA) && (*cs->busy_flag == 1)) { elsa_interrupt()
297 spin_lock_irqsave(&cs->lock, flags); elsa_interrupt()
299 if (cs->hw.elsa.MFlag) { elsa_interrupt()
300 val = serial_inp(cs, UART_IIR); elsa_interrupt()
302 debugl1(cs, "IIR %02x", val); elsa_interrupt()
303 rs_interrupt_elsa(cs); elsa_interrupt()
307 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt()
310 hscx_int_main(cs, val); elsa_interrupt()
312 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); elsa_interrupt()
315 isac_interrupt(cs, val); elsa_interrupt()
317 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt()
319 if (cs->debug & L1_DEB_HSCX) elsa_interrupt()
320 debugl1(cs, "HSCX IntStat after IntRoutine"); elsa_interrupt()
324 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA); elsa_interrupt()
326 if (cs->debug & L1_DEB_ISAC) elsa_interrupt()
327 debugl1(cs, "ISAC IntStat after IntRoutine"); elsa_interrupt()
333 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); elsa_interrupt()
334 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); elsa_interrupt()
335 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF); elsa_interrupt()
336 if (cs->hw.elsa.status & ELIRQF_TIMER_AKTIV) { elsa_interrupt()
337 if (!TimerRun(cs)) { elsa_interrupt()
339 byteout(cs->hw.elsa.timer, 0); elsa_interrupt()
340 cs->hw.elsa.counter++; elsa_interrupt()
344 if (cs->hw.elsa.MFlag) { elsa_interrupt()
345 val = serial_inp(cs, UART_MCR); elsa_interrupt()
347 serial_outp(cs, UART_MCR, val); elsa_interrupt()
348 val = serial_inp(cs, UART_MCR); elsa_interrupt()
350 serial_outp(cs, UART_MCR, val); elsa_interrupt()
353 if (cs->hw.elsa.trig) elsa_interrupt()
354 byteout(cs->hw.elsa.trig, 0x00); elsa_interrupt()
355 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); elsa_interrupt()
356 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); elsa_interrupt()
357 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0x0); elsa_interrupt()
358 spin_unlock_irqrestore(&cs->lock, flags); elsa_interrupt()
365 struct IsdnCardState *cs = dev_id; elsa_interrupt_ipac() local
370 spin_lock_irqsave(&cs->lock, flags); elsa_interrupt_ipac()
371 if (cs->subtyp == ELSA_QS1000PCI || cs->subtyp == ELSA_QS3000PCI) { elsa_interrupt_ipac()
372 val = bytein(cs->hw.elsa.cfg + 0x4c); /* PCI IRQ */ elsa_interrupt_ipac()
374 spin_unlock_irqrestore(&cs->lock, flags); elsa_interrupt_ipac()
379 if (cs->hw.elsa.MFlag) { elsa_interrupt_ipac()
380 val = serial_inp(cs, UART_IIR); elsa_interrupt_ipac()
382 debugl1(cs, "IIR %02x", val); elsa_interrupt_ipac()
383 rs_interrupt_elsa(cs); elsa_interrupt_ipac()
387 ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); elsa_interrupt_ipac()
389 if (cs->debug & L1_DEB_IPAC) elsa_interrupt_ipac()
390 debugl1(cs, "IPAC ISTA %02X", ista); elsa_interrupt_ipac()
392 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_ISTA + 0x40); elsa_interrupt_ipac()
400 hscx_int_main(cs, val); elsa_interrupt_ipac()
403 val = 0xfe & readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_ISTA + 0x80); elsa_interrupt_ipac()
405 isac_interrupt(cs, val); elsa_interrupt_ipac()
410 isac_interrupt(cs, val); elsa_interrupt_ipac()
412 ista = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ISTA); elsa_interrupt_ipac()
419 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xFF); elsa_interrupt_ipac()
420 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xC0); elsa_interrupt_ipac()
421 spin_unlock_irqrestore(&cs->lock, flags); elsa_interrupt_ipac()
426 release_io_elsa(struct IsdnCardState *cs) release_io_elsa() argument
430 del_timer(&cs->hw.elsa.tl); release_io_elsa()
432 clear_arcofi(cs); release_io_elsa()
434 if (cs->hw.elsa.ctrl) release_io_elsa()
435 byteout(cs->hw.elsa.ctrl, 0); /* LEDs Out */ release_io_elsa()
436 if (cs->subtyp == ELSA_QS1000PCI) { release_io_elsa()
437 byteout(cs->hw.elsa.cfg + 0x4c, 0x01); /* disable IRQ */ release_io_elsa()
438 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
440 release_region(cs->hw.elsa.cfg, 0x80); release_io_elsa()
442 if (cs->subtyp == ELSA_QS3000PCI) { release_io_elsa()
443 byteout(cs->hw.elsa.cfg + 0x4c, 0x03); /* disable ELSA PCI IRQ */ release_io_elsa()
444 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
445 release_region(cs->hw.elsa.cfg, 0x80); release_io_elsa()
447 if (cs->subtyp == ELSA_PCMCIA_IPAC) { release_io_elsa()
448 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); release_io_elsa()
450 if ((cs->subtyp == ELSA_PCFPRO) || release_io_elsa()
451 (cs->subtyp == ELSA_QS3000) || release_io_elsa()
452 (cs->subtyp == ELSA_PCF) || release_io_elsa()
453 (cs->subtyp == ELSA_QS3000PCI)) { release_io_elsa()
456 release_modem(cs); release_io_elsa()
459 if (cs->hw.elsa.base) release_io_elsa()
460 release_region(cs->hw.elsa.base, bytecnt); release_io_elsa()
464 reset_elsa(struct IsdnCardState *cs) reset_elsa() argument
466 if (cs->hw.elsa.timer) { reset_elsa()
468 byteout(cs->hw.elsa.timer, 0); reset_elsa()
469 while (TimerRun(cs)); reset_elsa()
470 cs->hw.elsa.ctrl_reg |= 0x50; reset_elsa()
471 cs->hw.elsa.ctrl_reg &= ~ELSA_ISDN_RESET; /* Reset On */ reset_elsa()
472 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); reset_elsa()
474 byteout(cs->hw.elsa.timer, 0); reset_elsa()
475 while (TimerRun(cs)); reset_elsa()
476 cs->hw.elsa.ctrl_reg |= ELSA_ISDN_RESET; /* Reset Off */ reset_elsa()
477 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); reset_elsa()
479 byteout(cs->hw.elsa.timer, 0); reset_elsa()
480 while (TimerRun(cs)); reset_elsa()
481 if (cs->hw.elsa.trig) reset_elsa()
482 byteout(cs->hw.elsa.trig, 0xff); reset_elsa()
484 if ((cs->subtyp == ELSA_QS1000PCI) || (cs->subtyp == ELSA_QS3000PCI) || (cs->subtyp == ELSA_PCMCIA_IPAC)) { reset_elsa()
485 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_POTA2, 0x20); reset_elsa()
487 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_POTA2, 0x00); reset_elsa()
488 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_MASK, 0xc0); reset_elsa()
490 if (cs->subtyp != ELSA_PCMCIA_IPAC) { reset_elsa()
491 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ACFG, 0x0); reset_elsa()
492 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_AOE, 0x3c); reset_elsa()
494 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_PCFG, 0x10); reset_elsa()
495 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ACFG, 0x4); reset_elsa()
496 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_AOE, 0xf8); reset_elsa()
498 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, 0xff); reset_elsa()
499 if (cs->subtyp == ELSA_QS1000PCI) reset_elsa()
500 byteout(cs->hw.elsa.cfg + 0x4c, 0x41); /* enable ELSA PCI IRQ */ reset_elsa()
501 else if (cs->subtyp == ELSA_QS3000PCI) reset_elsa()
502 byteout(cs->hw.elsa.cfg + 0x4c, 0x43); /* enable ELSA PCI IRQ */ reset_elsa()
509 set_arcofi(struct IsdnCardState *cs, int bc) { set_arcofi() argument
510 cs->dc.isac.arcofi_bc = bc; set_arcofi()
511 arcofi_fsm(cs, ARCOFI_START, &ARCOFI_COP_5); set_arcofi()
512 wait_event_interruptible(cs->dc.isac.arcofi_wait, set_arcofi()
513 cs->dc.isac.arcofi_state == ARCOFI_NOP); set_arcofi()
517 check_arcofi(struct IsdnCardState *cs) check_arcofi() argument
524 if (!cs->dc.isac.mon_tx) check_arcofi()
525 if (!(cs->dc.isac.mon_tx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { check_arcofi()
526 if (cs->debug & L1_DEB_WARN) check_arcofi()
527 debugl1(cs, "ISAC MON TX out of buffers!"); check_arcofi()
530 cs->dc.isac.arcofi_bc = 0; check_arcofi()
531 arcofi_fsm(cs, ARCOFI_START, &ARCOFI_VERSION); check_arcofi()
532 wait_event_interruptible(cs->dc.isac.arcofi_wait, check_arcofi()
533 cs->dc.isac.arcofi_state == ARCOFI_NOP); check_arcofi()
534 if (!test_and_clear_bit(FLG_ARCOFI_ERROR, &cs->HW_Flags)) { check_arcofi()
535 debugl1(cs, "Arcofi response received %d bytes", cs->dc.isac.mon_rxp); check_arcofi()
536 p = cs->dc.isac.mon_rx; check_arcofi()
539 QuickHex(t, p, cs->dc.isac.mon_rxp); check_arcofi()
540 debugl1(cs, "%s", tmp); check_arcofi()
541 if ((cs->dc.isac.mon_rxp == 2) && (cs->dc.isac.mon_rx[0] == 0xa0)) { check_arcofi()
542 switch (cs->dc.isac.mon_rx[1]) { check_arcofi()
544 debugl1(cs, "Arcofi 2160 detected"); check_arcofi()
548 debugl1(cs, "Arcofi 2165 detected"); check_arcofi()
552 debugl1(cs, "Arcofi 2163 detected"); check_arcofi()
556 debugl1(cs, "unknown Arcofi response"); check_arcofi()
560 debugl1(cs, "undefined Monitor response"); check_arcofi()
561 cs->dc.isac.mon_rxp = 0; check_arcofi()
562 } else if (cs->dc.isac.mon_tx) { check_arcofi()
563 debugl1(cs, "Arcofi not detected"); check_arcofi()
566 if (cs->subtyp == ELSA_QS1000) { check_arcofi()
567 cs->subtyp = ELSA_QS3000; check_arcofi()
570 Elsa_Types[cs->subtyp], check_arcofi()
571 cs->hw.elsa.base + 8); check_arcofi()
572 release_region(cs->hw.elsa.base, 8); check_arcofi()
573 if (!request_region(cs->hw.elsa.base, 16, "elsa isdn modem")) { check_arcofi()
576 Elsa_Types[cs->subtyp], check_arcofi()
577 cs->hw.elsa.base + 8, check_arcofi()
578 cs->hw.elsa.base + 16); check_arcofi()
580 } else if (cs->subtyp == ELSA_PCC16) { check_arcofi()
581 cs->subtyp = ELSA_PCF; check_arcofi()
584 Elsa_Types[cs->subtyp], check_arcofi()
585 cs->hw.elsa.base + 8); check_arcofi()
586 release_region(cs->hw.elsa.base, 8); check_arcofi()
587 if (!request_region(cs->hw.elsa.base, 16, "elsa isdn modem")) { check_arcofi()
590 Elsa_Types[cs->subtyp], check_arcofi()
591 cs->hw.elsa.base + 8, check_arcofi()
592 cs->hw.elsa.base + 16); check_arcofi()
597 Elsa_Types[cs->subtyp], check_arcofi()
598 cs->hw.elsa.base + 8); check_arcofi()
599 arcofi_fsm(cs, ARCOFI_START, &ARCOFI_XOP_0); check_arcofi()
600 wait_event_interruptible(cs->dc.isac.arcofi_wait, check_arcofi()
601 cs->dc.isac.arcofi_state == ARCOFI_NOP); check_arcofi()
609 elsa_led_handler(struct IsdnCardState *cs) elsa_led_handler() argument
613 if (cs->subtyp == ELSA_PCMCIA || cs->subtyp == ELSA_PCMCIA_IPAC) elsa_led_handler()
615 del_timer(&cs->hw.elsa.tl); elsa_led_handler()
616 if (cs->hw.elsa.status & ELSA_ASSIGN) elsa_led_handler()
617 cs->hw.elsa.ctrl_reg |= ELSA_STAT_LED; elsa_led_handler()
618 else if (cs->hw.elsa.status & ELSA_BAD_PWR) elsa_led_handler()
619 cs->hw.elsa.ctrl_reg &= ~ELSA_STAT_LED; elsa_led_handler()
621 cs->hw.elsa.ctrl_reg ^= ELSA_STAT_LED; elsa_led_handler()
624 if (cs->hw.elsa.status & 0xf000) elsa_led_handler()
625 cs->hw.elsa.ctrl_reg |= ELSA_LINE_LED; elsa_led_handler()
626 else if (cs->hw.elsa.status & 0x0f00) { elsa_led_handler()
627 cs->hw.elsa.ctrl_reg ^= ELSA_LINE_LED; elsa_led_handler()
630 cs->hw.elsa.ctrl_reg &= ~ELSA_LINE_LED; elsa_led_handler()
632 if ((cs->subtyp == ELSA_QS1000PCI) || elsa_led_handler()
633 (cs->subtyp == ELSA_QS3000PCI)) { elsa_led_handler()
635 if (cs->hw.elsa.ctrl_reg & ELSA_LINE_LED) elsa_led_handler()
637 if (cs->hw.elsa.ctrl_reg & ELSA_STAT_LED) elsa_led_handler()
639 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ATX, led); elsa_led_handler()
641 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); elsa_led_handler()
643 init_timer(&cs->hw.elsa.tl); elsa_led_handler()
644 cs->hw.elsa.tl.expires = jiffies + ((blink * HZ) / 1000); elsa_led_handler()
645 add_timer(&cs->hw.elsa.tl); elsa_led_handler()
650 Elsa_card_msg(struct IsdnCardState *cs, int mt, void *arg) Elsa_card_msg() argument
657 spin_lock_irqsave(&cs->lock, flags); Elsa_card_msg()
658 reset_elsa(cs); Elsa_card_msg()
659 spin_unlock_irqrestore(&cs->lock, flags); Elsa_card_msg()
662 release_io_elsa(cs); Elsa_card_msg()
665 spin_lock_irqsave(&cs->lock, flags); Elsa_card_msg()
666 cs->debug |= L1_DEB_IPAC; Elsa_card_msg()
667 reset_elsa(cs); Elsa_card_msg()
668 inithscxisac(cs, 1); Elsa_card_msg()
669 if ((cs->subtyp == ELSA_QS1000) || Elsa_card_msg()
670 (cs->subtyp == ELSA_QS3000)) Elsa_card_msg()
672 byteout(cs->hw.elsa.timer, 0); Elsa_card_msg()
674 if (cs->hw.elsa.trig) Elsa_card_msg()
675 byteout(cs->hw.elsa.trig, 0xff); Elsa_card_msg()
676 inithscxisac(cs, 2); Elsa_card_msg()
677 spin_unlock_irqrestore(&cs->lock, flags); Elsa_card_msg()
680 if ((cs->subtyp == ELSA_PCMCIA) || Elsa_card_msg()
681 (cs->subtyp == ELSA_PCMCIA_IPAC) || Elsa_card_msg()
682 (cs->subtyp == ELSA_QS1000PCI)) { Elsa_card_msg()
684 } else if (cs->subtyp == ELSA_QS3000PCI) { Elsa_card_msg()
687 spin_lock_irqsave(&cs->lock, flags); Elsa_card_msg()
688 cs->hw.elsa.counter = 0; Elsa_card_msg()
689 cs->hw.elsa.ctrl_reg |= ELSA_ENA_TIMER_INT; Elsa_card_msg()
690 cs->hw.elsa.status |= ELIRQF_TIMER_AKTIV; Elsa_card_msg()
691 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); Elsa_card_msg()
692 byteout(cs->hw.elsa.timer, 0); Elsa_card_msg()
693 spin_unlock_irqrestore(&cs->lock, flags); Elsa_card_msg()
695 spin_lock_irqsave(&cs->lock, flags); Elsa_card_msg()
696 cs->hw.elsa.ctrl_reg &= ~ELSA_ENA_TIMER_INT; Elsa_card_msg()
697 byteout(cs->hw.elsa.ctrl, cs->hw.elsa.ctrl_reg); Elsa_card_msg()
698 cs->hw.elsa.status &= ~ELIRQF_TIMER_AKTIV; Elsa_card_msg()
699 spin_unlock_irqrestore(&cs->lock, flags); Elsa_card_msg()
701 cs->hw.elsa.counter); Elsa_card_msg()
702 if ((cs->hw.elsa.counter > 10) && Elsa_card_msg()
703 (cs->hw.elsa.counter < 16)) { Elsa_card_msg()
709 cs->hw.elsa.counter, cs->irq); Elsa_card_msg()
714 if (check_arcofi(cs)) { Elsa_card_msg()
715 init_modem(cs); Elsa_card_msg()
718 elsa_led_handler(cs); Elsa_card_msg()
721 cs->hw.elsa.status &= 0; Elsa_card_msg()
724 cs->hw.elsa.status |= ELSA_ASSIGN; Elsa_card_msg()
728 cs->hw.elsa.status |= 0x0200; Elsa_card_msg()
730 cs->hw.elsa.status |= 0x0100; Elsa_card_msg()
734 cs->hw.elsa.status |= 0x2000; Elsa_card_msg()
736 cs->hw.elsa.status |= 0x1000; Elsa_card_msg()
740 cs->hw.elsa.status &= ~0x2000; Elsa_card_msg()
741 cs->hw.elsa.status &= ~0x0200; Elsa_card_msg()
743 cs->hw.elsa.status &= ~0x1000; Elsa_card_msg()
744 cs->hw.elsa.status &= ~0x0100; Elsa_card_msg()
749 if (cs->hw.elsa.MFlag) { Elsa_card_msg()
758 modem_write_cmd(cs, msg, len); Elsa_card_msg()
763 if (cs->typ == ISDN_CTYPE_ELSA) { Elsa_card_msg()
764 int pwr = bytein(cs->hw.elsa.ale); Elsa_card_msg()
766 cs->hw.elsa.status |= ELSA_BAD_PWR; Elsa_card_msg()
768 cs->hw.elsa.status &= ~ELSA_BAD_PWR; Elsa_card_msg()
770 elsa_led_handler(cs); Elsa_card_msg()
824 probe_elsa(struct IsdnCardState *cs) probe_elsa() argument
831 if ((cs->subtyp = probe_elsa_adr(CARD_portlist[i], cs->typ))) probe_elsa()
839 struct IsdnCardState *cs = card->cs; setup_elsa_isa() local
842 cs->hw.elsa.base = card->para[0]; setup_elsa_isa()
844 if (cs->hw.elsa.base) { setup_elsa_isa()
845 if (!(cs->subtyp = probe_elsa_adr(cs->hw.elsa.base, setup_elsa_isa()
846 cs->typ))) { setup_elsa_isa()
849 cs->hw.elsa.base); setup_elsa_isa()
853 cs->hw.elsa.base = probe_elsa(cs); setup_elsa_isa()
855 if (!cs->hw.elsa.base) { setup_elsa_isa()
861 cs->hw.elsa.cfg = cs->hw.elsa.base + ELSA_CONFIG; setup_elsa_isa()
862 cs->hw.elsa.ctrl = cs->hw.elsa.base + ELSA_CONTROL; setup_elsa_isa()
863 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE; setup_elsa_isa()
864 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC; setup_elsa_isa()
865 cs->hw.elsa.itac = cs->hw.elsa.base + ELSA_ITAC; setup_elsa_isa()
866 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isa()
867 cs->hw.elsa.trig = cs->hw.elsa.base + ELSA_TRIG_IRQ; setup_elsa_isa()
868 cs->hw.elsa.timer = cs->hw.elsa.base + ELSA_START_TIMER; setup_elsa_isa()
869 val = bytein(cs->hw.elsa.cfg); setup_elsa_isa()
870 if (cs->subtyp == ELSA_PC) { setup_elsa_isa()
873 cs->irq = CARD_IrqTab[(val & ELSA_IRQ_IDX_PC) >> 2]; setup_elsa_isa()
874 } else if (cs->subtyp == ELSA_PCC8) { setup_elsa_isa()
877 cs->irq = CARD_IrqTab[(val & ELSA_IRQ_IDX_PCC8) >> 4]; setup_elsa_isa()
881 cs->irq = CARD_IrqTab[(val & ELSA_IRQ_IDX) >> 3]; setup_elsa_isa()
883 val = bytein(cs->hw.elsa.ale) & ELSA_HW_RELEASE; setup_elsa_isa()
889 if ((cs->subtyp == ELSA_PCFPRO) && (val == 'G')) setup_elsa_isa()
893 Elsa_Types[cs->subtyp], setup_elsa_isa()
894 cs->hw.elsa.base, setup_elsa_isa()
895 val, cs->irq); setup_elsa_isa()
896 val = bytein(cs->hw.elsa.ale) & ELSA_S0_POWER_BAD; setup_elsa_isa()
900 cs->hw.elsa.status |= ELSA_BAD_PWR; setup_elsa_isa()
923 struct IsdnCardState *cs = card->cs; setup_elsa_isapnp() local
955 cs->subtyp = ELSA_QS1000; setup_elsa_isapnp()
957 cs->subtyp = ELSA_QS3000; setup_elsa_isapnp()
975 cs->hw.elsa.base = card->para[1]; setup_elsa_isapnp()
976 cs->irq = card->para[0]; setup_elsa_isapnp()
977 if (!cs->subtyp) setup_elsa_isapnp()
978 cs->subtyp = ELSA_QS1000; setup_elsa_isapnp()
982 cs->hw.elsa.cfg = cs->hw.elsa.base + ELSA_CONFIG; setup_elsa_isapnp()
983 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE; setup_elsa_isapnp()
984 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC; setup_elsa_isapnp()
985 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_isapnp()
986 cs->hw.elsa.trig = cs->hw.elsa.base + ELSA_TRIG_IRQ; setup_elsa_isapnp()
987 cs->hw.elsa.timer = cs->hw.elsa.base + ELSA_START_TIMER; setup_elsa_isapnp()
988 cs->hw.elsa.ctrl = cs->hw.elsa.base + ELSA_CONTROL; setup_elsa_isapnp()
991 Elsa_Types[cs->subtyp], setup_elsa_isapnp()
992 cs->hw.elsa.base, setup_elsa_isapnp()
993 cs->irq); setup_elsa_isapnp()
1000 struct IsdnCardState *cs = card->cs; setup_elsa_pcmcia() local
1003 cs->hw.elsa.base = card->para[1]; setup_elsa_pcmcia()
1004 cs->irq = card->para[0]; setup_elsa_pcmcia()
1005 val = readreg(cs->hw.elsa.base + 0, cs->hw.elsa.base + 2, IPAC_ID); setup_elsa_pcmcia()
1007 cs->subtyp = ELSA_PCMCIA_IPAC; setup_elsa_pcmcia()
1008 cs->hw.elsa.ale = cs->hw.elsa.base + 0; setup_elsa_pcmcia()
1009 cs->hw.elsa.isac = cs->hw.elsa.base + 2; setup_elsa_pcmcia()
1010 cs->hw.elsa.hscx = cs->hw.elsa.base + 2; setup_elsa_pcmcia()
1011 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_elsa_pcmcia()
1013 cs->subtyp = ELSA_PCMCIA; setup_elsa_pcmcia()
1014 cs->hw.elsa.ale = cs->hw.elsa.base + ELSA_ALE_PCM; setup_elsa_pcmcia()
1015 cs->hw.elsa.isac = cs->hw.elsa.base + ELSA_ISAC_PCM; setup_elsa_pcmcia()
1016 cs->hw.elsa.hscx = cs->hw.elsa.base + ELSA_HSCX; setup_elsa_pcmcia()
1018 cs->hw.elsa.timer = 0; setup_elsa_pcmcia()
1019 cs->hw.elsa.trig = 0; setup_elsa_pcmcia()
1020 cs->hw.elsa.ctrl = 0; setup_elsa_pcmcia()
1021 cs->irq_flags |= IRQF_SHARED; setup_elsa_pcmcia()
1024 Elsa_Types[cs->subtyp], setup_elsa_pcmcia()
1025 cs->hw.elsa.base, setup_elsa_pcmcia()
1026 cs->irq); setup_elsa_pcmcia()
1035 struct IsdnCardState *cs = card->cs; setup_elsa_pci() local
1037 cs->subtyp = 0; setup_elsa_pci()
1042 cs->subtyp = ELSA_QS1000PCI; setup_elsa_pci()
1043 cs->irq = dev_qs1000->irq; setup_elsa_pci()
1044 cs->hw.elsa.cfg = pci_resource_start(dev_qs1000, 1); setup_elsa_pci()
1045 cs->hw.elsa.base = pci_resource_start(dev_qs1000, 3); setup_elsa_pci()
1050 cs->subtyp = ELSA_QS3000PCI; setup_elsa_pci()
1051 cs->irq = dev_qs3000->irq; setup_elsa_pci()
1052 cs->hw.elsa.cfg = pci_resource_start(dev_qs3000, 1); setup_elsa_pci()
1053 cs->hw.elsa.base = pci_resource_start(dev_qs3000, 3); setup_elsa_pci()
1058 if (!cs->irq) { setup_elsa_pci()
1063 if (!(cs->hw.elsa.base && cs->hw.elsa.cfg)) { setup_elsa_pci()
1067 if ((cs->hw.elsa.cfg & 0xff) || (cs->hw.elsa.base & 0xf)) { setup_elsa_pci()
1072 cs->hw.elsa.ale = cs->hw.elsa.base; setup_elsa_pci()
1073 cs->hw.elsa.isac = cs->hw.elsa.base + 1; setup_elsa_pci()
1074 cs->hw.elsa.hscx = cs->hw.elsa.base + 1; setup_elsa_pci()
1075 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_elsa_pci()
1076 cs->hw.elsa.timer = 0; setup_elsa_pci()
1077 cs->hw.elsa.trig = 0; setup_elsa_pci()
1078 cs->irq_flags |= IRQF_SHARED; setup_elsa_pci()
1081 Elsa_Types[cs->subtyp], setup_elsa_pci()
1082 cs->hw.elsa.base, setup_elsa_pci()
1083 cs->hw.elsa.cfg, setup_elsa_pci()
1084 cs->irq); setup_elsa_pci()
1099 struct IsdnCardState *cs = card->cs; setup_elsa_common() local
1103 switch (cs->subtyp) { setup_elsa_common()
1123 "Unknown ELSA subtype %d\n", cs->subtyp); setup_elsa_common()
1129 if (cs->typ != ISDN_CTYPE_ELSA_PCMCIA && !request_region(cs->hw.elsa.base, bytecnt, "elsa isdn")) { setup_elsa_common()
1132 cs->hw.elsa.base, setup_elsa_common()
1133 cs->hw.elsa.base + bytecnt); setup_elsa_common()
1136 if ((cs->subtyp == ELSA_QS1000PCI) || (cs->subtyp == ELSA_QS3000PCI)) { setup_elsa_common()
1137 if (!request_region(cs->hw.elsa.cfg, 0x80, "elsa isdn pci")) { setup_elsa_common()
1140 cs->hw.elsa.cfg, setup_elsa_common()
1141 cs->hw.elsa.cfg + 0x80); setup_elsa_common()
1142 release_region(cs->hw.elsa.base, bytecnt); setup_elsa_common()
1147 init_arcofi(cs); setup_elsa_common()
1149 setup_isac(cs); setup_elsa_common()
1150 cs->hw.elsa.tl.function = (void *) elsa_led_handler; setup_elsa_common()
1151 cs->hw.elsa.tl.data = (long) cs; setup_elsa_common()
1152 init_timer(&cs->hw.elsa.tl); setup_elsa_common()
1154 if (cs->hw.elsa.timer) { setup_elsa_common()
1155 byteout(cs->hw.elsa.trig, 0xff); setup_elsa_common()
1156 byteout(cs->hw.elsa.timer, 0); setup_elsa_common()
1157 if (!TimerRun(cs)) { setup_elsa_common()
1158 byteout(cs->hw.elsa.timer, 0); /* 2. Versuch */ setup_elsa_common()
1159 if (!TimerRun(cs)) { setup_elsa_common()
1162 release_io_elsa(cs); setup_elsa_common()
1167 if (TimerRun(cs)) { setup_elsa_common()
1169 release_io_elsa(cs); setup_elsa_common()
1174 cs->BC_Read_Reg = &ReadHSCX; setup_elsa_common()
1175 cs->BC_Write_Reg = &WriteHSCX; setup_elsa_common()
1176 cs->BC_Send_Data = &hscx_fill_fifo; setup_elsa_common()
1177 cs->cardmsg = &Elsa_card_msg; setup_elsa_common()
1178 if ((cs->subtyp == ELSA_QS1000PCI) || (cs->subtyp == ELSA_QS3000PCI) || (cs->subtyp == ELSA_PCMCIA_IPAC)) { setup_elsa_common()
1179 cs->readisac = &ReadISAC_IPAC; setup_elsa_common()
1180 cs->writeisac = &WriteISAC_IPAC; setup_elsa_common()
1181 cs->readisacfifo = &ReadISACfifo_IPAC; setup_elsa_common()
1182 cs->writeisacfifo = &WriteISACfifo_IPAC; setup_elsa_common()
1183 cs->irq_func = &elsa_interrupt_ipac; setup_elsa_common()
1184 val = readreg(cs->hw.elsa.ale, cs->hw.elsa.isac, IPAC_ID); setup_elsa_common()
1187 cs->readisac = &ReadISAC; setup_elsa_common()
1188 cs->writeisac = &WriteISAC; setup_elsa_common()
1189 cs->readisacfifo = &ReadISACfifo; setup_elsa_common()
1190 cs->writeisacfifo = &WriteISACfifo; setup_elsa_common()
1191 cs->irq_func = &elsa_interrupt; setup_elsa_common()
1192 ISACVersion(cs, "Elsa:"); setup_elsa_common()
1193 if (HscxVersion(cs, "Elsa:")) { setup_elsa_common()
1196 release_io_elsa(cs); setup_elsa_common()
1200 if (cs->subtyp == ELSA_PC) { setup_elsa_common()
1201 val = readitac(cs, ITAC_SYS); setup_elsa_common()
1203 writeitac(cs, ITAC_ISEN, 0); setup_elsa_common()
1204 writeitac(cs, ITAC_RFIE, 0); setup_elsa_common()
1205 writeitac(cs, ITAC_XFIE, 0); setup_elsa_common()
1206 writeitac(cs, ITAC_SCIE, 0); setup_elsa_common()
1207 writeitac(cs, ITAC_STIE, 0); setup_elsa_common()
1215 struct IsdnCardState *cs = card->cs; setup_elsa() local
1220 cs->hw.elsa.ctrl_reg = 0; setup_elsa()
1221 cs->hw.elsa.status = 0; setup_elsa()
1222 cs->hw.elsa.MFlag = 0; setup_elsa()
1223 cs->subtyp = 0; setup_elsa()
1225 if (cs->typ == ISDN_CTYPE_ELSA) { setup_elsa()
1230 } else if (cs->typ == ISDN_CTYPE_ELSA_PNP) { setup_elsa()
1235 } else if (cs->typ == ISDN_CTYPE_ELSA_PCMCIA) setup_elsa()
1238 else if (cs->typ == ISDN_CTYPE_ELSA_PCI) { setup_elsa()
|
| H A D | s0box.c | 96 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
98 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); ReadISAC()
102 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
104 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); WriteISAC()
108 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
110 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); ReadISACfifo()
114 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
116 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); WriteISACfifo()
120 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
122 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); ReadHSCX()
126 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
128 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX()
135 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg)
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt)
146 struct IsdnCardState *cs = dev_id; s0box_interrupt() local
151 spin_lock_irqsave(&cs->lock, flags); s0box_interrupt()
152 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt()
155 hscx_int_main(cs, val); s0box_interrupt()
156 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA); s0box_interrupt()
159 isac_interrupt(cs, val); s0box_interrupt()
161 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_ISTA); s0box_interrupt()
163 if (cs->debug & L1_DEB_HSCX) s0box_interrupt()
164 debugl1(cs, "HSCX IntStat after IntRoutine"); s0box_interrupt()
167 val = readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_ISTA); s0box_interrupt()
169 if (cs->debug & L1_DEB_ISAC) s0box_interrupt()
170 debugl1(cs, "ISAC IntStat after IntRoutine"); s0box_interrupt()
175 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); s0box_interrupt()
176 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); s0box_interrupt()
177 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF); s0box_interrupt()
178 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0); s0box_interrupt()
179 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); s0box_interrupt()
180 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); s0box_interrupt()
181 spin_unlock_irqrestore(&cs->lock, flags); s0box_interrupt()
186 release_io_s0box(struct IsdnCardState *cs) release_io_s0box() argument
188 release_region(cs->hw.teles3.cfg_reg, 8); release_io_s0box()
192 S0Box_card_msg(struct IsdnCardState *cs, int mt, void *arg) S0Box_card_msg() argument
200 release_io_s0box(cs); S0Box_card_msg()
203 spin_lock_irqsave(&cs->lock, flags); S0Box_card_msg()
204 inithscxisac(cs, 3); S0Box_card_msg()
205 spin_unlock_irqrestore(&cs->lock, flags); S0Box_card_msg()
215 struct IsdnCardState *cs = card->cs; setup_s0box() local
220 if (cs->typ != ISDN_CTYPE_S0BOX) setup_s0box()
223 cs->hw.teles3.cfg_reg = card->para[1]; setup_s0box()
224 cs->hw.teles3.hscx[0] = -0x20; setup_s0box()
225 cs->hw.teles3.hscx[1] = 0x0; setup_s0box()
226 cs->hw.teles3.isac = 0x20; setup_s0box()
227 cs->hw.teles3.isacfifo = cs->hw.teles3.isac + 0x3e; setup_s0box()
228 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_s0box()
229 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_s0box()
230 cs->irq = card->para[0]; setup_s0box()
231 if (!request_region(cs->hw.teles3.cfg_reg, 8, "S0Box parallel I/O")) { setup_s0box()
233 cs->hw.teles3.cfg_reg, setup_s0box()
234 cs->hw.teles3.cfg_reg + 7); setup_s0box()
238 cs->irq, setup_s0box()
239 cs->hw.teles3.isac, cs->hw.teles3.cfg_reg); setup_s0box()
241 cs->hw.teles3.hscx[0], cs->hw.teles3.hscx[1]); setup_s0box()
242 setup_isac(cs); setup_s0box()
243 cs->readisac = &ReadISAC; setup_s0box()
244 cs->writeisac = &WriteISAC; setup_s0box()
245 cs->readisacfifo = &ReadISACfifo; setup_s0box()
246 cs->writeisacfifo = &WriteISACfifo; setup_s0box()
247 cs->BC_Read_Reg = &ReadHSCX; setup_s0box()
248 cs->BC_Write_Reg = &WriteHSCX; setup_s0box()
249 cs->BC_Send_Data = &hscx_fill_fifo; setup_s0box()
250 cs->cardmsg = &S0Box_card_msg; setup_s0box()
251 cs->irq_func = &s0box_interrupt; setup_s0box()
252 ISACVersion(cs, "S0Box:"); setup_s0box()
253 if (HscxVersion(cs, "S0Box:")) { setup_s0box()
256 release_io_s0box(cs); setup_s0box()
|
| H A D | teles3.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
58 return (readreg(cs->hw.teles3.isac, offset)); ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
64 writereg(cs->hw.teles3.isac, offset, value); WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
70 read_fifo(cs->hw.teles3.isacfifo, data, size); ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
76 write_fifo(cs->hw.teles3.isacfifo, data, size); WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); ReadHSCX()
86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
88 writereg(cs->hw.teles3.hscx[hscx], offset, value); WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
97 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
98 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.hscxfifo[nr], ptr, cnt)
106 struct IsdnCardState *cs = dev_id; teles3_interrupt() local
111 spin_lock_irqsave(&cs->lock, flags); teles3_interrupt()
112 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt()
115 hscx_int_main(cs, val); teles3_interrupt()
116 val = readreg(cs->hw.teles3.isac, ISAC_ISTA); teles3_interrupt()
119 isac_interrupt(cs, val); teles3_interrupt()
121 val = readreg(cs->hw.teles3.hscx[1], HSCX_ISTA); teles3_interrupt()
123 if (cs->debug & L1_DEB_HSCX) teles3_interrupt()
124 debugl1(cs, "HSCX IntStat after IntRoutine"); teles3_interrupt()
127 val = readreg(cs->hw.teles3.isac, ISAC_ISTA); teles3_interrupt()
129 if (cs->debug & L1_DEB_ISAC) teles3_interrupt()
130 debugl1(cs, "ISAC IntStat after IntRoutine"); teles3_interrupt()
135 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); teles3_interrupt()
136 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); teles3_interrupt()
137 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); teles3_interrupt()
138 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); teles3_interrupt()
139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); teles3_interrupt()
140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); teles3_interrupt()
141 spin_unlock_irqrestore(&cs->lock, flags); teles3_interrupt()
146 release_ioregs(struct IsdnCardState *cs, int mask) release_ioregs() argument
149 release_region(cs->hw.teles3.isac + 32, 32); release_ioregs()
151 release_region(cs->hw.teles3.hscx[0] + 32, 32); release_ioregs()
153 release_region(cs->hw.teles3.hscx[1] + 32, 32); release_ioregs()
157 release_io_teles3(struct IsdnCardState *cs) release_io_teles3() argument
159 if (cs->typ == ISDN_CTYPE_TELESPCMCIA) { release_io_teles3()
160 release_region(cs->hw.teles3.hscx[1], 96); release_io_teles3()
162 if (cs->hw.teles3.cfg_reg) { release_io_teles3()
163 if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { release_io_teles3()
164 release_region(cs->hw.teles3.cfg_reg, 1); release_io_teles3()
166 release_region(cs->hw.teles3.cfg_reg, 8); release_io_teles3()
169 release_ioregs(cs, 0x7); release_io_teles3()
174 reset_teles3(struct IsdnCardState *cs) reset_teles3() argument
178 if (cs->typ != ISDN_CTYPE_TELESPCMCIA) { reset_teles3()
179 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { reset_teles3()
180 switch (cs->irq) { reset_teles3()
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg); reset_teles3()
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1); reset_teles3()
213 } else if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { reset_teles3()
214 byteout(cs->hw.teles3.cfg_reg, 0xff); reset_teles3()
216 byteout(cs->hw.teles3.cfg_reg, 0x00); reset_teles3()
220 byteout(cs->hw.teles3.isac + 0x3c, 0); reset_teles3()
222 byteout(cs->hw.teles3.isac + 0x3c, 1); reset_teles3()
230 Teles_card_msg(struct IsdnCardState *cs, int mt, void *arg) Teles_card_msg() argument
236 spin_lock_irqsave(&cs->lock, flags); Teles_card_msg()
237 reset_teles3(cs); Teles_card_msg()
238 spin_unlock_irqrestore(&cs->lock, flags); Teles_card_msg()
241 release_io_teles3(cs); Teles_card_msg()
244 spin_lock_irqsave(&cs->lock, flags); Teles_card_msg()
245 inithscxisac(cs, 3); Teles_card_msg()
246 spin_unlock_irqrestore(&cs->lock, flags); Teles_card_msg()
276 struct IsdnCardState *cs = card->cs; setup_teles3() local
281 if ((cs->typ != ISDN_CTYPE_16_3) && (cs->typ != ISDN_CTYPE_PNP) setup_teles3()
282 && (cs->typ != ISDN_CTYPE_TELESPCMCIA) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) setup_teles3()
329 if (cs->typ == ISDN_CTYPE_16_3) { setup_teles3()
330 cs->hw.teles3.cfg_reg = card->para[1]; setup_teles3()
331 switch (cs->hw.teles3.cfg_reg) { setup_teles3()
335 cs->hw.teles3.cfg_reg |= 0xc00; setup_teles3()
338 cs->hw.teles3.isac = cs->hw.teles3.cfg_reg - 0x420; setup_teles3()
339 cs->hw.teles3.hscx[0] = cs->hw.teles3.cfg_reg - 0xc20; setup_teles3()
340 cs->hw.teles3.hscx[1] = cs->hw.teles3.cfg_reg - 0x820; setup_teles3()
341 } else if (cs->typ == ISDN_CTYPE_TELESPCMCIA) { setup_teles3()
342 cs->hw.teles3.cfg_reg = 0; setup_teles3()
343 cs->hw.teles3.hscx[0] = card->para[1] - 0x20; setup_teles3()
344 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3()
345 cs->hw.teles3.isac = card->para[1] + 0x20; setup_teles3()
346 } else if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { setup_teles3()
347 cs->hw.teles3.cfg_reg = card->para[3]; setup_teles3()
348 cs->hw.teles3.isac = card->para[2] - 32; setup_teles3()
349 cs->hw.teles3.hscx[0] = card->para[1] - 32; setup_teles3()
350 cs->hw.teles3.hscx[1] = card->para[1]; setup_teles3()
352 cs->hw.teles3.cfg_reg = 0; setup_teles3()
353 cs->hw.teles3.isac = card->para[1] - 32; setup_teles3()
354 cs->hw.teles3.hscx[0] = card->para[2] - 32; setup_teles3()
355 cs->hw.teles3.hscx[1] = card->para[2]; setup_teles3()
357 cs->irq = card->para[0]; setup_teles3()
358 cs->hw.teles3.isacfifo = cs->hw.teles3.isac + 0x3e; setup_teles3()
359 cs->hw.teles3.hscxfifo[0] = cs->hw.teles3.hscx[0] + 0x3e; setup_teles3()
360 cs->hw.teles3.hscxfifo[1] = cs->hw.teles3.hscx[1] + 0x3e; setup_teles3()
361 if (cs->typ == ISDN_CTYPE_TELESPCMCIA) { setup_teles3()
362 if (!request_region(cs->hw.teles3.hscx[1], 96, "HiSax Teles PCMCIA")) { setup_teles3()
365 CardType[cs->typ], setup_teles3()
366 cs->hw.teles3.hscx[1], setup_teles3()
367 cs->hw.teles3.hscx[1] + 96); setup_teles3()
370 cs->irq_flags |= IRQF_SHARED; /* cardbus can share */ setup_teles3()
372 if (cs->hw.teles3.cfg_reg) { setup_teles3()
373 if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { setup_teles3()
374 if (!request_region(cs->hw.teles3.cfg_reg, 1, "teles3 cfg")) { setup_teles3()
378 cs->hw.teles3.cfg_reg); setup_teles3()
382 if (!request_region(cs->hw.teles3.cfg_reg, 8, "teles3 cfg")) { setup_teles3()
386 cs->hw.teles3.cfg_reg, setup_teles3()
387 cs->hw.teles3.cfg_reg + 8); setup_teles3()
392 if (!request_region(cs->hw.teles3.isac + 32, 32, "HiSax isac")) { setup_teles3()
395 CardType[cs->typ], setup_teles3()
396 cs->hw.teles3.isac + 32, setup_teles3()
397 cs->hw.teles3.isac + 64); setup_teles3()
398 if (cs->hw.teles3.cfg_reg) { setup_teles3()
399 if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { setup_teles3()
400 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
402 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
407 if (!request_region(cs->hw.teles3.hscx[0] + 32, 32, "HiSax hscx A")) { setup_teles3()
410 CardType[cs->typ], setup_teles3()
411 cs->hw.teles3.hscx[0] + 32, setup_teles3()
412 cs->hw.teles3.hscx[0] + 64); setup_teles3()
413 if (cs->hw.teles3.cfg_reg) { setup_teles3()
414 if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { setup_teles3()
415 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
417 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
420 release_ioregs(cs, 1); setup_teles3()
423 if (!request_region(cs->hw.teles3.hscx[1] + 32, 32, "HiSax hscx B")) { setup_teles3()
426 CardType[cs->typ], setup_teles3()
427 cs->hw.teles3.hscx[1] + 32, setup_teles3()
428 cs->hw.teles3.hscx[1] + 64); setup_teles3()
429 if (cs->hw.teles3.cfg_reg) { setup_teles3()
430 if (cs->typ == ISDN_CTYPE_COMPAQ_ISA) { setup_teles3()
431 release_region(cs->hw.teles3.cfg_reg, 1); setup_teles3()
433 release_region(cs->hw.teles3.cfg_reg, 8); setup_teles3()
436 release_ioregs(cs, 3); setup_teles3()
440 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { setup_teles3()
441 if ((val = bytein(cs->hw.teles3.cfg_reg + 0)) != 0x51) { setup_teles3()
443 cs->hw.teles3.cfg_reg + 0, val); setup_teles3()
444 release_io_teles3(cs); setup_teles3()
447 if ((val = bytein(cs->hw.teles3.cfg_reg + 1)) != 0x93) { setup_teles3()
449 cs->hw.teles3.cfg_reg + 1, val); setup_teles3()
450 release_io_teles3(cs); setup_teles3()
453 val = bytein(cs->hw.teles3.cfg_reg + 2);/* 0x1e=without AB setup_teles3()
462 cs->hw.teles3.cfg_reg + 2, val); setup_teles3()
463 release_io_teles3(cs); setup_teles3()
469 CardType[cs->typ], cs->irq, setup_teles3()
470 cs->hw.teles3.isac + 32, cs->hw.teles3.cfg_reg); setup_teles3()
473 cs->hw.teles3.hscx[0] + 32, cs->hw.teles3.hscx[1] + 32); setup_teles3()
475 setup_isac(cs); setup_teles3()
476 if (reset_teles3(cs)) { setup_teles3()
478 release_io_teles3(cs); setup_teles3()
481 cs->readisac = &ReadISAC; setup_teles3()
482 cs->writeisac = &WriteISAC; setup_teles3()
483 cs->readisacfifo = &ReadISACfifo; setup_teles3()
484 cs->writeisacfifo = &WriteISACfifo; setup_teles3()
485 cs->BC_Read_Reg = &ReadHSCX; setup_teles3()
486 cs->BC_Write_Reg = &WriteHSCX; setup_teles3()
487 cs->BC_Send_Data = &hscx_fill_fifo; setup_teles3()
488 cs->cardmsg = &Teles_card_msg; setup_teles3()
489 cs->irq_func = &teles3_interrupt; setup_teles3()
490 ISACVersion(cs, "Teles3:"); setup_teles3()
491 if (HscxVersion(cs, "Teles3:")) { setup_teles3()
494 release_io_teles3(cs); setup_teles3()
|
| H A D | amd7930_fn.h | 19 #define rByteAMD(cs, reg) cs->readisac(cs, reg)
20 #define wByteAMD(cs, reg, val) cs->writeisac(cs, reg, val)
21 #define rWordAMD(cs, reg) ReadWordAmd7930(cs, reg)
22 #define wWordAMD(cs, reg, val) WriteWordAmd7930(cs, reg, val)
26 #define AmdIrqOff(cs) cs->dc.amd7930.setIrqMask(cs, 0)
27 #define AmdIrqOn(cs) cs->dc.amd7930.setIrqMask(cs, 1)
|
| H A D | bkm_a8.c | 78 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
80 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80)); ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
86 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
92 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
98 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size); WriteISACfifo()
103 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
105 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0))); ReadHSCX()
109 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
111 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
116 set_ipac_active(struct IsdnCardState *cs, u_int active) set_ipac_active() argument
119 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, set_ipac_active()
127 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
128 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
130 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
131 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
132 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
133 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
134 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
141 struct IsdnCardState *cs = dev_id; bkm_interrupt_ipac() local
145 spin_lock_irqsave(&cs->lock, flags); bkm_interrupt_ipac()
146 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); bkm_interrupt_ipac()
148 spin_unlock_irqrestore(&cs->lock, flags); bkm_interrupt_ipac()
152 if (cs->debug & L1_DEB_IPAC) bkm_interrupt_ipac()
153 debugl1(cs, "IPAC ISTA %02X", ista); bkm_interrupt_ipac()
155 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40); bkm_interrupt_ipac()
163 hscx_int_main(cs, val); bkm_interrupt_ipac()
167 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80); bkm_interrupt_ipac()
169 isac_interrupt(cs, val); bkm_interrupt_ipac()
174 isac_interrupt(cs, val); bkm_interrupt_ipac()
176 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA); bkm_interrupt_ipac()
183 sct_quadro_subtypes[cs->subtyp]); bkm_interrupt_ipac()
184 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); bkm_interrupt_ipac()
185 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); bkm_interrupt_ipac()
186 spin_unlock_irqrestore(&cs->lock, flags); bkm_interrupt_ipac()
191 release_io_sct_quadro(struct IsdnCardState *cs) release_io_sct_quadro() argument
193 release_region(cs->hw.ax.base & 0xffffffc0, 128); release_io_sct_quadro()
194 if (cs->subtyp == SCT_1) release_io_sct_quadro()
195 release_region(cs->hw.ax.plx_adr, 64); release_io_sct_quadro()
199 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable) enable_bkm_int() argument
201 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) { enable_bkm_int()
203 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41)); enable_bkm_int()
205 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41)); enable_bkm_int()
210 reset_bkm(struct IsdnCardState *cs) reset_bkm() argument
212 if (cs->subtyp == SCT_1) { reset_bkm()
213 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4)); reset_bkm()
216 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4)); reset_bkm()
222 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg) BKM_card_msg() argument
228 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
230 set_ipac_active(cs, 0); BKM_card_msg()
231 enable_bkm_int(cs, 0); BKM_card_msg()
232 reset_bkm(cs); BKM_card_msg()
233 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
237 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
238 set_ipac_active(cs, 0); BKM_card_msg()
239 enable_bkm_int(cs, 0); BKM_card_msg()
240 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
241 release_io_sct_quadro(cs); BKM_card_msg()
244 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
245 cs->debug |= L1_DEB_IPAC; BKM_card_msg()
246 set_ipac_active(cs, 1); BKM_card_msg()
247 inithscxisac(cs, 3); BKM_card_msg()
249 enable_bkm_int(cs, 1); BKM_card_msg()
250 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
278 struct IsdnCardState *cs = card->cs; setup_sct_quadro() local
285 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) { setup_sct_quadro()
286 cs->subtyp = SCT_1; /* Preset */ setup_sct_quadro()
292 cs->subtyp = card->para[0]; setup_sct_quadro()
298 if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) || setup_sct_quadro()
301 if (cs->subtyp == SCT_1) { setup_sct_quadro()
322 sct_quadro_subtypes[cs->subtyp]); setup_sct_quadro()
330 sct_quadro_subtypes[cs->subtyp]); setup_sct_quadro()
343 sct_quadro_subtypes[cs->subtyp]); setup_sct_quadro()
354 sct_quadro_subtypes[cs->subtyp]); setup_sct_quadro()
363 cs->irq = pci_irq; setup_sct_quadro()
364 cs->irq_flags |= IRQF_SHARED; setup_sct_quadro()
370 cs->hw.ax.plx_adr = pci_ioaddr1; setup_sct_quadro()
372 switch (cs->subtyp) { setup_sct_quadro()
374 cs->hw.ax.base = pci_ioaddr5 + 0x00; setup_sct_quadro()
390 cs->hw.ax.base = pci_ioaddr4 + 0x08; setup_sct_quadro()
395 cs->hw.ax.base = pci_ioaddr3 + 0x10; setup_sct_quadro()
400 cs->hw.ax.base = pci_ioaddr2 + 0x20; setup_sct_quadro()
406 cs->hw.ax.data_adr = cs->hw.ax.base + 4; setup_sct_quadro()
410 sct_quadro_subtypes[cs->subtyp], setup_sct_quadro()
411 cs->hw.ax.plx_adr, setup_sct_quadro()
412 cs->hw.ax.base, setup_sct_quadro()
413 cs->hw.ax.data_adr, setup_sct_quadro()
414 cs->irq); setup_sct_quadro()
416 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_sct_quadro()
418 cs->readisac = &ReadISAC; setup_sct_quadro()
419 cs->writeisac = &WriteISAC; setup_sct_quadro()
420 cs->readisacfifo = &ReadISACfifo; setup_sct_quadro()
421 cs->writeisacfifo = &WriteISACfifo; setup_sct_quadro()
423 cs->BC_Read_Reg = &ReadHSCX; setup_sct_quadro()
424 cs->BC_Write_Reg = &WriteHSCX; setup_sct_quadro()
425 cs->BC_Send_Data = &hscx_fill_fifo; setup_sct_quadro()
426 cs->cardmsg = &BKM_card_msg; setup_sct_quadro()
427 cs->irq_func = &bkm_interrupt_ipac; setup_sct_quadro()
430 sct_quadro_subtypes[cs->subtyp], setup_sct_quadro()
431 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID)); setup_sct_quadro()
|
| H A D | mic.c | 66 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset)); ReadISAC()
72 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); WriteISAC()
78 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
80 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); ReadISACfifo()
84 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
86 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size); WriteISACfifo()
90 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
92 return (readreg(cs->hw.mic.adr, ReadHSCX()
93 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
97 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
99 writereg(cs->hw.mic.adr, WriteHSCX()
100 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
107 #define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \
108 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
109 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
110 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
112 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.mic.adr, \
113 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
115 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.mic.adr, \
116 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
123 struct IsdnCardState *cs = dev_id; mic_interrupt() local
127 spin_lock_irqsave(&cs->lock, flags); mic_interrupt()
128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt()
131 hscx_int_main(cs, val); mic_interrupt()
132 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA); mic_interrupt()
135 isac_interrupt(cs, val); mic_interrupt()
136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40); mic_interrupt()
138 if (cs->debug & L1_DEB_HSCX) mic_interrupt()
139 debugl1(cs, "HSCX IntStat after IntRoutine"); mic_interrupt()
142 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA); mic_interrupt()
144 if (cs->debug & L1_DEB_ISAC) mic_interrupt()
145 debugl1(cs, "ISAC IntStat after IntRoutine"); mic_interrupt()
148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); mic_interrupt()
149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); mic_interrupt()
150 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF); mic_interrupt()
151 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0); mic_interrupt()
152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); mic_interrupt()
153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); mic_interrupt()
154 spin_unlock_irqrestore(&cs->lock, flags); mic_interrupt()
159 release_io_mic(struct IsdnCardState *cs) release_io_mic() argument
163 if (cs->hw.mic.cfg_reg) release_io_mic()
164 release_region(cs->hw.mic.cfg_reg, bytecnt); release_io_mic()
168 mic_card_msg(struct IsdnCardState *cs, int mt, void *arg) mic_card_msg() argument
176 release_io_mic(cs); mic_card_msg()
179 spin_lock_irqsave(&cs->lock, flags); mic_card_msg()
180 inithscx(cs); /* /RTSA := ISAC RST */ mic_card_msg()
181 inithscxisac(cs, 3); mic_card_msg()
182 spin_unlock_irqrestore(&cs->lock, flags); mic_card_msg()
193 struct IsdnCardState *cs = card->cs; setup_mic() local
198 if (cs->typ != ISDN_CTYPE_MIC) setup_mic()
202 cs->hw.mic.cfg_reg = card->para[1]; setup_mic()
203 cs->irq = card->para[0]; setup_mic()
204 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR; setup_mic()
205 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC; setup_mic()
206 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX; setup_mic()
208 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) { setup_mic()
211 cs->hw.mic.cfg_reg, setup_mic()
212 cs->hw.mic.cfg_reg + bytecnt); setup_mic()
216 cs->hw.mic.cfg_reg, cs->irq); setup_mic()
217 setup_isac(cs); setup_mic()
218 cs->readisac = &ReadISAC; setup_mic()
219 cs->writeisac = &WriteISAC; setup_mic()
220 cs->readisacfifo = &ReadISACfifo; setup_mic()
221 cs->writeisacfifo = &WriteISACfifo; setup_mic()
222 cs->BC_Read_Reg = &ReadHSCX; setup_mic()
223 cs->BC_Write_Reg = &WriteHSCX; setup_mic()
224 cs->BC_Send_Data = &hscx_fill_fifo; setup_mic()
225 cs->cardmsg = &mic_card_msg; setup_mic()
226 cs->irq_func = &mic_interrupt; setup_mic()
227 ISACVersion(cs, "mic:"); setup_mic()
228 if (HscxVersion(cs, "mic:")) { setup_mic()
231 release_io_mic(cs); setup_mic()
|
| H A D | asuscom.c | 78 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
80 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset)); ReadISAC()
84 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
86 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); WriteISAC()
90 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
92 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); ReadISACfifo()
96 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
98 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0, data, size); WriteISACfifo()
102 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) ReadISAC_IPAC() argument
104 return (readreg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80)); ReadISAC_IPAC()
108 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC_IPAC() argument
110 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset | 0x80, value); WriteISAC_IPAC()
114 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo_IPAC() argument
116 readfifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); ReadISACfifo_IPAC()
120 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo_IPAC() argument
122 writefifo(cs->hw.asus.adr, cs->hw.asus.isac, 0x80, data, size); WriteISACfifo_IPAC()
126 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
128 return (readreg(cs->hw.asus.adr, ReadHSCX()
129 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
133 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
135 writereg(cs->hw.asus.adr, WriteHSCX()
136 cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
143 #define READHSCX(cs, nr, reg) readreg(cs->hw.asus.adr, \
144 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0))
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \
146 cs->hw.asus.hscx, reg + (nr ? 0x40 : 0), data)
148 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.asus.adr, \
149 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
151 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.asus.adr, \
152 cs->hw.asus.hscx, (nr ? 0x40 : 0), ptr, cnt)
159 struct IsdnCardState *cs = dev_id; asuscom_interrupt() local
163 spin_lock_irqsave(&cs->lock, flags); asuscom_interrupt()
164 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt()
167 hscx_int_main(cs, val); asuscom_interrupt()
168 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); asuscom_interrupt()
171 isac_interrupt(cs, val); asuscom_interrupt()
172 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt()
174 if (cs->debug & L1_DEB_HSCX) asuscom_interrupt()
175 debugl1(cs, "HSCX IntStat after IntRoutine"); asuscom_interrupt()
178 val = readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA); asuscom_interrupt()
180 if (cs->debug & L1_DEB_ISAC) asuscom_interrupt()
181 debugl1(cs, "ISAC IntStat after IntRoutine"); asuscom_interrupt()
184 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); asuscom_interrupt()
185 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); asuscom_interrupt()
186 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF); asuscom_interrupt()
187 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0); asuscom_interrupt()
188 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); asuscom_interrupt()
189 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0x0); asuscom_interrupt()
190 spin_unlock_irqrestore(&cs->lock, flags); asuscom_interrupt()
197 struct IsdnCardState *cs = dev_id; asuscom_interrupt_ipac() local
201 spin_lock_irqsave(&cs->lock, flags); asuscom_interrupt_ipac()
202 ista = readreg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ISTA); asuscom_interrupt_ipac()
204 if (cs->debug & L1_DEB_IPAC) asuscom_interrupt_ipac()
205 debugl1(cs, "IPAC ISTA %02X", ista); asuscom_interrupt_ipac()
207 val = readreg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_ISTA + 0x40); asuscom_interrupt_ipac()
215 hscx_int_main(cs, val); asuscom_interrupt_ipac()
218 val = 0xfe & readreg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_ISTA | 0x80); asuscom_interrupt_ipac()
220 isac_interrupt(cs, val); asuscom_interrupt_ipac()
225 isac_interrupt(cs, val); asuscom_interrupt_ipac()
227 ista = readreg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ISTA); asuscom_interrupt_ipac()
234 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xFF); asuscom_interrupt_ipac()
235 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xC0); asuscom_interrupt_ipac()
236 spin_unlock_irqrestore(&cs->lock, flags); asuscom_interrupt_ipac()
241 release_io_asuscom(struct IsdnCardState *cs) release_io_asuscom() argument
245 if (cs->hw.asus.cfg_reg) release_io_asuscom()
246 release_region(cs->hw.asus.cfg_reg, bytecnt); release_io_asuscom()
250 reset_asuscom(struct IsdnCardState *cs) reset_asuscom() argument
252 if (cs->subtyp == ASUS_IPAC) reset_asuscom()
253 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_POTA2, 0x20); reset_asuscom()
255 byteout(cs->hw.asus.adr, ASUS_RESET); /* Reset On */ reset_asuscom()
257 if (cs->subtyp == ASUS_IPAC) reset_asuscom()
258 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_POTA2, 0x0); reset_asuscom()
260 byteout(cs->hw.asus.adr, 0); /* Reset Off */ reset_asuscom()
262 if (cs->subtyp == ASUS_IPAC) { reset_asuscom()
263 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_CONF, 0x0); reset_asuscom()
264 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_ACFG, 0xff); reset_asuscom()
265 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_AOE, 0x0); reset_asuscom()
266 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_MASK, 0xc0); reset_asuscom()
267 writereg(cs->hw.asus.adr, cs->hw.asus.isac, IPAC_PCFG, 0x12); reset_asuscom()
272 Asus_card_msg(struct IsdnCardState *cs, int mt, void *arg) Asus_card_msg() argument
278 spin_lock_irqsave(&cs->lock, flags); Asus_card_msg()
279 reset_asuscom(cs); Asus_card_msg()
280 spin_unlock_irqrestore(&cs->lock, flags); Asus_card_msg()
283 release_io_asuscom(cs); Asus_card_msg()
286 spin_lock_irqsave(&cs->lock, flags); Asus_card_msg()
287 cs->debug |= L1_DEB_IPAC; Asus_card_msg()
288 inithscxisac(cs, 3); Asus_card_msg()
289 spin_unlock_irqrestore(&cs->lock, flags); Asus_card_msg()
321 struct IsdnCardState *cs = card->cs; setup_asuscom() local
327 if (cs->typ != ISDN_CTYPE_ASUSCOM) setup_asuscom()
372 cs->hw.asus.cfg_reg = card->para[1]; setup_asuscom()
373 cs->irq = card->para[0]; setup_asuscom()
374 if (!request_region(cs->hw.asus.cfg_reg, bytecnt, "asuscom isdn")) { setup_asuscom()
377 cs->hw.asus.cfg_reg, setup_asuscom()
378 cs->hw.asus.cfg_reg + bytecnt); setup_asuscom()
382 cs->hw.asus.cfg_reg, cs->irq); setup_asuscom()
383 setup_isac(cs); setup_asuscom()
384 cs->BC_Read_Reg = &ReadHSCX; setup_asuscom()
385 cs->BC_Write_Reg = &WriteHSCX; setup_asuscom()
386 cs->BC_Send_Data = &hscx_fill_fifo; setup_asuscom()
387 cs->cardmsg = &Asus_card_msg; setup_asuscom()
388 val = readreg(cs->hw.asus.cfg_reg + ASUS_IPAC_ALE, setup_asuscom()
389 cs->hw.asus.cfg_reg + ASUS_IPAC_DATA, IPAC_ID); setup_asuscom()
391 cs->subtyp = ASUS_IPAC; setup_asuscom()
392 cs->hw.asus.adr = cs->hw.asus.cfg_reg + ASUS_IPAC_ALE; setup_asuscom()
393 cs->hw.asus.isac = cs->hw.asus.cfg_reg + ASUS_IPAC_DATA; setup_asuscom()
394 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_IPAC_DATA; setup_asuscom()
395 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_asuscom()
396 cs->readisac = &ReadISAC_IPAC; setup_asuscom()
397 cs->writeisac = &WriteISAC_IPAC; setup_asuscom()
398 cs->readisacfifo = &ReadISACfifo_IPAC; setup_asuscom()
399 cs->writeisacfifo = &WriteISACfifo_IPAC; setup_asuscom()
400 cs->irq_func = &asuscom_interrupt_ipac; setup_asuscom()
403 cs->subtyp = ASUS_ISACHSCX; setup_asuscom()
404 cs->hw.asus.adr = cs->hw.asus.cfg_reg + ASUS_ADR; setup_asuscom()
405 cs->hw.asus.isac = cs->hw.asus.cfg_reg + ASUS_ISAC; setup_asuscom()
406 cs->hw.asus.hscx = cs->hw.asus.cfg_reg + ASUS_HSCX; setup_asuscom()
407 cs->hw.asus.u7 = cs->hw.asus.cfg_reg + ASUS_CTRL_U7; setup_asuscom()
408 cs->hw.asus.pots = cs->hw.asus.cfg_reg + ASUS_CTRL_POTS; setup_asuscom()
409 cs->readisac = &ReadISAC; setup_asuscom()
410 cs->writeisac = &WriteISAC; setup_asuscom()
411 cs->readisacfifo = &ReadISACfifo; setup_asuscom()
412 cs->writeisacfifo = &WriteISACfifo; setup_asuscom()
413 cs->irq_func = &asuscom_interrupt; setup_asuscom()
414 ISACVersion(cs, "ISDNLink:"); setup_asuscom()
415 if (HscxVersion(cs, "ISDNLink:")) { setup_asuscom()
418 release_io_asuscom(cs); setup_asuscom()
|
| H A D | sportster.c | 54 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
56 return (bytein(calc_off(cs->hw.spt.isac, offset))); ReadISAC()
60 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
62 byteout(calc_off(cs->hw.spt.isac, offset), value); WriteISAC()
66 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
68 read_fifo(cs->hw.spt.isac, data, size); ReadISACfifo()
72 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
74 write_fifo(cs->hw.spt.isac, data, size); WriteISACfifo()
78 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
80 return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset))); ReadHSCX()
84 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value); WriteHSCX()
93 #define READHSCX(cs, nr, reg) bytein(calc_off(cs->hw.spt.hscx[nr], reg))
94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
95 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
96 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.spt.hscx[nr], ptr, cnt)
103 struct IsdnCardState *cs = dev_id; sportster_interrupt() local
107 spin_lock_irqsave(&cs->lock, flags); sportster_interrupt()
108 val = READHSCX(cs, 1, HSCX_ISTA); sportster_interrupt()
111 hscx_int_main(cs, val); sportster_interrupt()
112 val = ReadISAC(cs, ISAC_ISTA); sportster_interrupt()
115 isac_interrupt(cs, val); sportster_interrupt()
116 val = READHSCX(cs, 1, HSCX_ISTA); sportster_interrupt()
118 if (cs->debug & L1_DEB_HSCX) sportster_interrupt()
119 debugl1(cs, "HSCX IntStat after IntRoutine"); sportster_interrupt()
122 val = ReadISAC(cs, ISAC_ISTA); sportster_interrupt()
124 if (cs->debug & L1_DEB_ISAC) sportster_interrupt()
125 debugl1(cs, "ISAC IntStat after IntRoutine"); sportster_interrupt()
129 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ + 1); sportster_interrupt()
130 spin_unlock_irqrestore(&cs->lock, flags); sportster_interrupt()
135 release_io_sportster(struct IsdnCardState *cs) release_io_sportster() argument
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0); release_io_sportster()
141 adr = cs->hw.spt.cfg_reg + i * 1024; release_io_sportster()
147 reset_sportster(struct IsdnCardState *cs) reset_sportster() argument
149 cs->hw.spt.res_irq |= SPORTSTER_RESET; /* Reset On */ reset_sportster()
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); reset_sportster()
152 cs->hw.spt.res_irq &= ~SPORTSTER_RESET; /* Reset Off */ reset_sportster()
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); reset_sportster()
158 Sportster_card_msg(struct IsdnCardState *cs, int mt, void *arg) Sportster_card_msg() argument
164 spin_lock_irqsave(&cs->lock, flags); Sportster_card_msg()
165 reset_sportster(cs); Sportster_card_msg()
166 spin_unlock_irqrestore(&cs->lock, flags); Sportster_card_msg()
169 release_io_sportster(cs); Sportster_card_msg()
172 spin_lock_irqsave(&cs->lock, flags); Sportster_card_msg()
173 reset_sportster(cs); Sportster_card_msg()
174 inithscxisac(cs, 1); Sportster_card_msg()
175 cs->hw.spt.res_irq |= SPORTSTER_INTE; /* IRQ On */ Sportster_card_msg()
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); Sportster_card_msg()
177 inithscxisac(cs, 2); Sportster_card_msg()
178 spin_unlock_irqrestore(&cs->lock, flags); Sportster_card_msg()
186 static int get_io_range(struct IsdnCardState *cs) get_io_range() argument
191 adr = cs->hw.spt.cfg_reg + i * 1024; get_io_range()
203 adr = cs->hw.spt.cfg_reg + j * 1024; get_io_range()
212 struct IsdnCardState *cs = card->cs; setup_sportster() local
217 if (cs->typ != ISDN_CTYPE_SPORTSTER) setup_sportster()
220 cs->hw.spt.cfg_reg = card->para[1]; setup_sportster()
221 cs->irq = card->para[0]; setup_sportster()
222 if (!get_io_range(cs)) setup_sportster()
224 cs->hw.spt.isac = cs->hw.spt.cfg_reg + SPORTSTER_ISAC; setup_sportster()
225 cs->hw.spt.hscx[0] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXA; setup_sportster()
226 cs->hw.spt.hscx[1] = cs->hw.spt.cfg_reg + SPORTSTER_HSCXB; setup_sportster()
228 switch (cs->irq) { setup_sportster()
229 case 5: cs->hw.spt.res_irq = 1; setup_sportster()
231 case 7: cs->hw.spt.res_irq = 2; setup_sportster()
233 case 10:cs->hw.spt.res_irq = 3; setup_sportster()
235 case 11:cs->hw.spt.res_irq = 4; setup_sportster()
237 case 12:cs->hw.spt.res_irq = 5; setup_sportster()
239 case 14:cs->hw.spt.res_irq = 6; setup_sportster()
241 case 15:cs->hw.spt.res_irq = 7; setup_sportster()
243 default:release_io_sportster(cs); setup_sportster()
248 cs->irq, cs->hw.spt.cfg_reg); setup_sportster()
249 setup_isac(cs); setup_sportster()
250 cs->readisac = &ReadISAC; setup_sportster()
251 cs->writeisac = &WriteISAC; setup_sportster()
252 cs->readisacfifo = &ReadISACfifo; setup_sportster()
253 cs->writeisacfifo = &WriteISACfifo; setup_sportster()
254 cs->BC_Read_Reg = &ReadHSCX; setup_sportster()
255 cs->BC_Write_Reg = &WriteHSCX; setup_sportster()
256 cs->BC_Send_Data = &hscx_fill_fifo; setup_sportster()
257 cs->cardmsg = &Sportster_card_msg; setup_sportster()
258 cs->irq_func = &sportster_interrupt; setup_sportster()
259 ISACVersion(cs, "Sportster:"); setup_sportster()
260 if (HscxVersion(cs, "Sportster:")) { setup_sportster()
263 release_io_sportster(cs); setup_sportster()
|
| H A D | avm_a1.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
58 return (readreg(cs->hw.avm.isac, offset)); ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
64 writereg(cs->hw.avm.isac, offset, value); WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
70 read_fifo(cs->hw.avm.isacfifo, data, size); ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
76 write_fifo(cs->hw.avm.isacfifo, data, size); WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); ReadHSCX()
86 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
88 writereg(cs->hw.avm.hscx[hscx], offset, value); WriteHSCX()
95 #define READHSCX(cs, nr, reg) readreg(cs->hw.avm.hscx[nr], reg)
96 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
97 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
98 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.avm.hscxfifo[nr], ptr, cnt)
105 struct IsdnCardState *cs = dev_id; avm_a1_interrupt() local
109 spin_lock_irqsave(&cs->lock, flags); avm_a1_interrupt()
110 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { avm_a1_interrupt()
112 byteout(cs->hw.avm.cfg_reg, 0x1E); avm_a1_interrupt()
113 sval = bytein(cs->hw.avm.cfg_reg); avm_a1_interrupt()
114 } else if (cs->debug & L1_DEB_INTSTAT) avm_a1_interrupt()
115 debugl1(cs, "avm IntStatus %x", sval); avm_a1_interrupt()
117 val = readreg(cs->hw.avm.hscx[1], HSCX_ISTA); avm_a1_interrupt()
119 hscx_int_main(cs, val); avm_a1_interrupt()
122 val = readreg(cs->hw.avm.isac, ISAC_ISTA); avm_a1_interrupt()
124 isac_interrupt(cs, val); avm_a1_interrupt()
127 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); avm_a1_interrupt()
128 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); avm_a1_interrupt()
129 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); avm_a1_interrupt()
130 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); avm_a1_interrupt()
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); avm_a1_interrupt()
132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); avm_a1_interrupt()
133 spin_unlock_irqrestore(&cs->lock, flags); avm_a1_interrupt()
138 release_ioregs(struct IsdnCardState *cs, int mask) release_ioregs() argument
140 release_region(cs->hw.avm.cfg_reg, 8); release_ioregs()
142 release_region(cs->hw.avm.isac + 32, 32); release_ioregs()
144 release_region(cs->hw.avm.isacfifo, 1); release_ioregs()
146 release_region(cs->hw.avm.hscx[0] + 32, 32); release_ioregs()
148 release_region(cs->hw.avm.hscxfifo[0], 1); release_ioregs()
150 release_region(cs->hw.avm.hscx[1] + 32, 32); release_ioregs()
152 release_region(cs->hw.avm.hscxfifo[1], 1); release_ioregs()
156 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg) AVM_card_msg() argument
164 release_ioregs(cs, 0x3f); AVM_card_msg()
167 spin_lock_irqsave(&cs->lock, flags); AVM_card_msg()
168 inithscxisac(cs, 1); AVM_card_msg()
169 byteout(cs->hw.avm.cfg_reg, 0x16); AVM_card_msg()
170 byteout(cs->hw.avm.cfg_reg, 0x1E); AVM_card_msg()
171 inithscxisac(cs, 2); AVM_card_msg()
172 spin_unlock_irqrestore(&cs->lock, flags); AVM_card_msg()
183 struct IsdnCardState *cs = card->cs; setup_avm_a1() local
188 if (cs->typ != ISDN_CTYPE_A1) setup_avm_a1()
191 cs->hw.avm.cfg_reg = card->para[1] + 0x1800; setup_avm_a1()
192 cs->hw.avm.isac = card->para[1] + 0x1400 - 0x20; setup_avm_a1()
193 cs->hw.avm.hscx[0] = card->para[1] + 0x400 - 0x20; setup_avm_a1()
194 cs->hw.avm.hscx[1] = card->para[1] + 0xc00 - 0x20; setup_avm_a1()
195 cs->hw.avm.isacfifo = card->para[1] + 0x1000; setup_avm_a1()
196 cs->hw.avm.hscxfifo[0] = card->para[1]; setup_avm_a1()
197 cs->hw.avm.hscxfifo[1] = card->para[1] + 0x800; setup_avm_a1()
198 cs->irq = card->para[0]; setup_avm_a1()
199 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) { setup_avm_a1()
202 cs->hw.avm.cfg_reg, setup_avm_a1()
203 cs->hw.avm.cfg_reg + 8); setup_avm_a1()
206 if (!request_region(cs->hw.avm.isac + 32, 32, "HiSax isac")) { setup_avm_a1()
209 cs->hw.avm.isac + 32, setup_avm_a1()
210 cs->hw.avm.isac + 64); setup_avm_a1()
211 release_ioregs(cs, 0); setup_avm_a1()
214 if (!request_region(cs->hw.avm.isacfifo, 1, "HiSax isac fifo")) { setup_avm_a1()
217 cs->hw.avm.isacfifo); setup_avm_a1()
218 release_ioregs(cs, 1); setup_avm_a1()
221 if (!request_region(cs->hw.avm.hscx[0] + 32, 32, "HiSax hscx A")) { setup_avm_a1()
224 cs->hw.avm.hscx[0] + 32, setup_avm_a1()
225 cs->hw.avm.hscx[0] + 64); setup_avm_a1()
226 release_ioregs(cs, 3); setup_avm_a1()
229 if (!request_region(cs->hw.avm.hscxfifo[0], 1, "HiSax hscx A fifo")) { setup_avm_a1()
232 cs->hw.avm.hscxfifo[0]); setup_avm_a1()
233 release_ioregs(cs, 7); setup_avm_a1()
236 if (!request_region(cs->hw.avm.hscx[1] + 32, 32, "HiSax hscx B")) { setup_avm_a1()
239 cs->hw.avm.hscx[1] + 32, setup_avm_a1()
240 cs->hw.avm.hscx[1] + 64); setup_avm_a1()
241 release_ioregs(cs, 0xf); setup_avm_a1()
244 if (!request_region(cs->hw.avm.hscxfifo[1], 1, "HiSax hscx B fifo")) { setup_avm_a1()
247 cs->hw.avm.hscxfifo[1]); setup_avm_a1()
248 release_ioregs(cs, 0x1f); setup_avm_a1()
251 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
253 byteout(cs->hw.avm.cfg_reg, 0x1); setup_avm_a1()
255 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
257 val = cs->irq; setup_avm_a1()
260 byteout(cs->hw.avm.cfg_reg + 1, val); setup_avm_a1()
262 byteout(cs->hw.avm.cfg_reg, 0x0); setup_avm_a1()
265 val = bytein(cs->hw.avm.cfg_reg); setup_avm_a1()
267 cs->hw.avm.cfg_reg, val); setup_avm_a1()
268 val = bytein(cs->hw.avm.cfg_reg + 3); setup_avm_a1()
270 cs->hw.avm.cfg_reg + 3, val); setup_avm_a1()
271 val = bytein(cs->hw.avm.cfg_reg + 2); setup_avm_a1()
273 cs->hw.avm.cfg_reg + 2, val); setup_avm_a1()
274 val = bytein(cs->hw.avm.cfg_reg); setup_avm_a1()
276 cs->hw.avm.cfg_reg, val); setup_avm_a1()
279 cs->irq, setup_avm_a1()
280 cs->hw.avm.cfg_reg); setup_avm_a1()
283 cs->hw.avm.isac + 32, cs->hw.avm.isacfifo); setup_avm_a1()
286 cs->hw.avm.hscx[0] + 32, cs->hw.avm.hscxfifo[0], setup_avm_a1()
287 cs->hw.avm.hscx[1] + 32, cs->hw.avm.hscxfifo[1]); setup_avm_a1()
289 cs->readisac = &ReadISAC; setup_avm_a1()
290 cs->writeisac = &WriteISAC; setup_avm_a1()
291 cs->readisacfifo = &ReadISACfifo; setup_avm_a1()
292 cs->writeisacfifo = &WriteISACfifo; setup_avm_a1()
293 cs->BC_Read_Reg = &ReadHSCX; setup_avm_a1()
294 cs->BC_Write_Reg = &WriteHSCX; setup_avm_a1()
295 cs->BC_Send_Data = &hscx_fill_fifo; setup_avm_a1()
296 setup_isac(cs); setup_avm_a1()
297 cs->cardmsg = &AVM_card_msg; setup_avm_a1()
298 cs->irq_func = &avm_a1_interrupt; setup_avm_a1()
299 ISACVersion(cs, "AVM A1:"); setup_avm_a1()
300 if (HscxVersion(cs, "AVM A1:")) { setup_avm_a1()
303 release_ioregs(cs, 0x3f); setup_avm_a1()
|
| H A D | sedlbauer.c | 154 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
156 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset)); ReadISAC()
160 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
162 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); WriteISAC()
166 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
168 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); ReadISACfifo()
172 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
174 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0, data, size); WriteISACfifo()
178 ReadISAC_IPAC(struct IsdnCardState *cs, u_char offset) ReadISAC_IPAC() argument
180 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80)); ReadISAC_IPAC()
184 WriteISAC_IPAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC_IPAC() argument
186 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset | 0x80, value); WriteISAC_IPAC()
190 ReadISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo_IPAC() argument
192 readfifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); ReadISACfifo_IPAC()
196 WriteISACfifo_IPAC(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo_IPAC() argument
198 writefifo(cs->hw.sedl.adr, cs->hw.sedl.isac, 0x80, data, size); WriteISACfifo_IPAC()
202 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
204 return (readreg(cs->hw.sedl.adr, ReadHSCX()
205 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0))); ReadHSCX()
209 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
211 writereg(cs->hw.sedl.adr, WriteHSCX()
212 cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0), value); WriteHSCX()
222 ReadISAR(struct IsdnCardState *cs, int mode, u_char offset) ReadISAR() argument
225 return (readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset)); ReadISAR()
227 byteout(cs->hw.sedl.adr, offset); ReadISAR()
228 return (bytein(cs->hw.sedl.hscx)); ReadISAR()
232 WriteISAR(struct IsdnCardState *cs, int mode, u_char offset, u_char value) WriteISAR() argument
235 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); WriteISAR()
238 byteout(cs->hw.sedl.adr, offset); WriteISAR()
239 byteout(cs->hw.sedl.hscx, value); WriteISAR()
247 #define READHSCX(cs, nr, reg) readreg(cs->hw.sedl.adr, \
248 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0))
249 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \
250 cs->hw.sedl.hscx, reg + (nr ? 0x40 : 0), data)
252 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.sedl.adr, \
253 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
255 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.sedl.adr, \
256 cs->hw.sedl.hscx, (nr ? 0x40 : 0), ptr, cnt)
263 struct IsdnCardState *cs = dev_id; sedlbauer_interrupt() local
267 spin_lock_irqsave(&cs->lock, flags); sedlbauer_interrupt()
268 if ((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && (*cs->busy_flag == 1)) { sedlbauer_interrupt()
271 spin_unlock_irqrestore(&cs->lock, flags); sedlbauer_interrupt()
276 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt()
279 hscx_int_main(cs, val); sedlbauer_interrupt()
280 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt()
283 isac_interrupt(cs, val); sedlbauer_interrupt()
284 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt()
286 if (cs->debug & L1_DEB_HSCX) sedlbauer_interrupt()
287 debugl1(cs, "HSCX IntStat after IntRoutine"); sedlbauer_interrupt()
290 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt()
292 if (cs->debug & L1_DEB_ISAC) sedlbauer_interrupt()
293 debugl1(cs, "ISAC IntStat after IntRoutine"); sedlbauer_interrupt()
296 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); sedlbauer_interrupt()
297 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); sedlbauer_interrupt()
298 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); sedlbauer_interrupt()
299 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); sedlbauer_interrupt()
300 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0x0); sedlbauer_interrupt()
301 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0x0); sedlbauer_interrupt()
302 spin_unlock_irqrestore(&cs->lock, flags); sedlbauer_interrupt()
309 struct IsdnCardState *cs = dev_id; sedlbauer_interrupt_ipac() local
313 spin_lock_irqsave(&cs->lock, flags); sedlbauer_interrupt_ipac()
314 ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); sedlbauer_interrupt_ipac()
316 if (cs->debug & L1_DEB_IPAC) sedlbauer_interrupt_ipac()
317 debugl1(cs, "IPAC ISTA %02X", ista); sedlbauer_interrupt_ipac()
319 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_ISTA + 0x40); sedlbauer_interrupt_ipac()
327 hscx_int_main(cs, val); sedlbauer_interrupt_ipac()
330 val = 0xfe & readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA | 0x80); sedlbauer_interrupt_ipac()
332 isac_interrupt(cs, val); sedlbauer_interrupt_ipac()
337 isac_interrupt(cs, val); sedlbauer_interrupt_ipac()
339 ista = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ISTA); sedlbauer_interrupt_ipac()
345 if (cs->debug & L1_DEB_ISAC) sedlbauer_interrupt_ipac()
346 debugl1(cs, "Sedlbauer IRQ LOOP"); sedlbauer_interrupt_ipac()
347 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xFF); sedlbauer_interrupt_ipac()
348 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xC0); sedlbauer_interrupt_ipac()
349 spin_unlock_irqrestore(&cs->lock, flags); sedlbauer_interrupt_ipac()
356 struct IsdnCardState *cs = dev_id; sedlbauer_interrupt_isar() local
361 spin_lock_irqsave(&cs->lock, flags); sedlbauer_interrupt_isar()
362 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar()
365 isar_int_main(cs); sedlbauer_interrupt_isar()
366 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt_isar()
369 isac_interrupt(cs, val); sedlbauer_interrupt_isar()
370 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT); sedlbauer_interrupt_isar()
372 if (cs->debug & L1_DEB_HSCX) sedlbauer_interrupt_isar()
373 debugl1(cs, "ISAR IntStat after IntRoutine"); sedlbauer_interrupt_isar()
376 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_ISTA); sedlbauer_interrupt_isar()
378 if (cs->debug & L1_DEB_ISAC) sedlbauer_interrupt_isar()
379 debugl1(cs, "ISAC IntStat after IntRoutine"); sedlbauer_interrupt_isar()
383 if (cs->debug & L1_DEB_ISAC) sedlbauer_interrupt_isar()
384 debugl1(cs, "Sedlbauer IRQ LOOP"); sedlbauer_interrupt_isar()
386 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, 0); sedlbauer_interrupt_isar()
387 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); sedlbauer_interrupt_isar()
388 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); sedlbauer_interrupt_isar()
389 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, ISAR_IRQBIT, ISAR_IRQMSK); sedlbauer_interrupt_isar()
390 spin_unlock_irqrestore(&cs->lock, flags); sedlbauer_interrupt_isar()
395 release_io_sedlbauer(struct IsdnCardState *cs) release_io_sedlbauer() argument
399 if (cs->subtyp == SEDL_SPEED_FAX) { release_io_sedlbauer()
401 } else if (cs->hw.sedl.bus == SEDL_BUS_PCI) { release_io_sedlbauer()
404 if (cs->hw.sedl.cfg_reg) release_io_sedlbauer()
405 release_region(cs->hw.sedl.cfg_reg, bytecnt); release_io_sedlbauer()
409 reset_sedlbauer(struct IsdnCardState *cs) reset_sedlbauer() argument
413 if (!((cs->hw.sedl.bus == SEDL_BUS_PCMCIA) && reset_sedlbauer()
414 (cs->hw.sedl.chip == SEDL_CHIP_ISAC_HSCX))) { reset_sedlbauer()
415 if (cs->hw.sedl.chip == SEDL_CHIP_IPAC) { reset_sedlbauer()
416 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_POTA2, 0x20); reset_sedlbauer()
418 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_POTA2, 0x0); reset_sedlbauer()
420 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_CONF, 0x0); reset_sedlbauer()
421 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ACFG, 0xff); reset_sedlbauer()
422 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_AOE, 0x0); reset_sedlbauer()
423 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_MASK, 0xc0); reset_sedlbauer()
424 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_PCFG, 0x12); reset_sedlbauer()
425 } else if ((cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) && reset_sedlbauer()
426 (cs->hw.sedl.bus == SEDL_BUS_PCI)) { reset_sedlbauer()
427 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); reset_sedlbauer()
429 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); reset_sedlbauer()
432 byteout(cs->hw.sedl.reset_on, SEDL_RESET); /* Reset On */ reset_sedlbauer()
434 byteout(cs->hw.sedl.reset_off, 0); /* Reset Off */ reset_sedlbauer()
441 Sedl_card_msg(struct IsdnCardState *cs, int mt, void *arg) Sedl_card_msg() argument
447 spin_lock_irqsave(&cs->lock, flags); Sedl_card_msg()
448 reset_sedlbauer(cs); Sedl_card_msg()
449 spin_unlock_irqrestore(&cs->lock, flags); Sedl_card_msg()
452 if (cs->hw.sedl.bus == SEDL_BUS_PCI) Sedl_card_msg()
454 byteout(cs->hw.sedl.cfg_reg + 5, 0); Sedl_card_msg()
455 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { Sedl_card_msg()
456 spin_lock_irqsave(&cs->lock, flags); Sedl_card_msg()
457 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
459 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, Sedl_card_msg()
461 reset_sedlbauer(cs); Sedl_card_msg()
462 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
464 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, Sedl_card_msg()
466 spin_unlock_irqrestore(&cs->lock, flags); Sedl_card_msg()
468 release_io_sedlbauer(cs); Sedl_card_msg()
471 spin_lock_irqsave(&cs->lock, flags); Sedl_card_msg()
472 if (cs->hw.sedl.bus == SEDL_BUS_PCI) Sedl_card_msg()
474 byteout(cs->hw.sedl.cfg_reg + 5, 0x02); Sedl_card_msg()
475 reset_sedlbauer(cs); Sedl_card_msg()
476 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { Sedl_card_msg()
477 clear_pending_isac_ints(cs); Sedl_card_msg()
478 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, Sedl_card_msg()
480 initisac(cs); Sedl_card_msg()
481 initisar(cs); Sedl_card_msg()
483 cs->writeisac(cs, ISAC_MASK, 0); Sedl_card_msg()
485 cs->writeisac(cs, ISAC_CMDR, 0x41); Sedl_card_msg()
487 inithscxisac(cs, 3); Sedl_card_msg()
489 spin_unlock_irqrestore(&cs->lock, flags); Sedl_card_msg()
494 if (cs->subtyp != SEDL_SPEEDFAX_PYRAMID) Sedl_card_msg()
496 spin_lock_irqsave(&cs->lock, flags); Sedl_card_msg()
498 cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED2; Sedl_card_msg()
500 cs->hw.sedl.reset_off &= ~SEDL_ISAR_PCI_LED1; Sedl_card_msg()
501 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); Sedl_card_msg()
502 spin_unlock_irqrestore(&cs->lock, flags); Sedl_card_msg()
505 if (cs->subtyp != SEDL_SPEEDFAX_PYRAMID) Sedl_card_msg()
507 spin_lock_irqsave(&cs->lock, flags); Sedl_card_msg()
509 cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED2; Sedl_card_msg()
511 cs->hw.sedl.reset_off |= SEDL_ISAR_PCI_LED1; Sedl_card_msg()
512 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); Sedl_card_msg()
513 spin_unlock_irqrestore(&cs->lock, flags); Sedl_card_msg()
535 struct IsdnCardState *cs = card->cs; setup_sedlbauer_isapnp() local
567 cs->hw.sedl.cfg_reg = card->para[1]; setup_sedlbauer_isapnp()
568 cs->irq = card->para[0]; setup_sedlbauer_isapnp()
570 cs->subtyp = SEDL_SPEED_FAX; setup_sedlbauer_isapnp()
571 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_isapnp()
574 cs->subtyp = SEDL_SPEED_CARD_WIN; setup_sedlbauer_isapnp()
575 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer_isapnp()
604 struct IsdnCardState *cs = card->cs; setup_sedlbauer_pci() local
611 cs->irq = dev_sedl->irq; setup_sedlbauer_pci()
612 if (!cs->irq) { setup_sedlbauer_pci()
616 cs->hw.sedl.cfg_reg = pci_resource_start(dev_sedl, 0); setup_sedlbauer_pci()
621 cs->irq_flags |= IRQF_SHARED; setup_sedlbauer_pci()
622 cs->hw.sedl.bus = SEDL_BUS_PCI; setup_sedlbauer_pci()
628 cs->hw.sedl.cfg_reg); setup_sedlbauer_pci()
634 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_pci()
635 cs->subtyp = SEDL_SPEEDFAX_PYRAMID; setup_sedlbauer_pci()
637 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer_pci()
638 cs->subtyp = SEDL_SPEEDFAX_PCI; setup_sedlbauer_pci()
640 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer_pci()
641 cs->subtyp = HST_SAPHIR3; setup_sedlbauer_pci()
643 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer_pci()
644 cs->subtyp = SEDL_SPEED_PCI; setup_sedlbauer_pci()
651 cs->hw.sedl.reset_on = SEDL_ISAR_PCI_ISAR_RESET_ON; setup_sedlbauer_pci()
652 cs->hw.sedl.reset_off = SEDL_ISAR_PCI_ISAR_RESET_OFF; setup_sedlbauer_pci()
653 byteout(cs->hw.sedl.cfg_reg, 0xff); setup_sedlbauer_pci()
654 byteout(cs->hw.sedl.cfg_reg, 0x00); setup_sedlbauer_pci()
655 byteout(cs->hw.sedl.cfg_reg + 2, 0xdd); setup_sedlbauer_pci()
656 byteout(cs->hw.sedl.cfg_reg + 5, 0); /* disable all IRQ */ setup_sedlbauer_pci()
657 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); setup_sedlbauer_pci()
659 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_off); setup_sedlbauer_pci()
677 struct IsdnCardState *cs = card->cs; setup_sedlbauer() local
683 if (cs->typ == ISDN_CTYPE_SEDLBAUER) { setup_sedlbauer()
684 cs->subtyp = SEDL_SPEED_CARD_WIN; setup_sedlbauer()
685 cs->hw.sedl.bus = SEDL_BUS_ISA; setup_sedlbauer()
686 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer()
687 } else if (cs->typ == ISDN_CTYPE_SEDLBAUER_PCMCIA) { setup_sedlbauer()
688 cs->subtyp = SEDL_SPEED_STAR; setup_sedlbauer()
689 cs->hw.sedl.bus = SEDL_BUS_PCMCIA; setup_sedlbauer()
690 cs->hw.sedl.chip = SEDL_CHIP_TEST; setup_sedlbauer()
691 } else if (cs->typ == ISDN_CTYPE_SEDLBAUER_FAX) { setup_sedlbauer()
692 cs->subtyp = SEDL_SPEED_FAX; setup_sedlbauer()
693 cs->hw.sedl.bus = SEDL_BUS_ISA; setup_sedlbauer()
694 cs->hw.sedl.chip = SEDL_CHIP_ISAC_ISAR; setup_sedlbauer()
700 cs->hw.sedl.cfg_reg = card->para[1]; setup_sedlbauer()
701 cs->irq = card->para[0]; setup_sedlbauer()
702 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { setup_sedlbauer()
726 if (cs->hw.sedl.bus != SEDL_BUS_PCMCIA && setup_sedlbauer()
727 !request_region(cs->hw.sedl.cfg_reg, bytecnt, "sedlbauer isdn")) { setup_sedlbauer()
731 cs->hw.sedl.cfg_reg, setup_sedlbauer()
732 cs->hw.sedl.cfg_reg + bytecnt); setup_sedlbauer()
738 cs->hw.sedl.cfg_reg, setup_sedlbauer()
739 cs->hw.sedl.cfg_reg + bytecnt, setup_sedlbauer()
740 cs->irq); setup_sedlbauer()
742 cs->BC_Read_Reg = &ReadHSCX; setup_sedlbauer()
743 cs->BC_Write_Reg = &WriteHSCX; setup_sedlbauer()
744 cs->BC_Send_Data = &hscx_fill_fifo; setup_sedlbauer()
745 cs->cardmsg = &Sedl_card_msg; setup_sedlbauer()
752 if (cs->hw.sedl.bus != SEDL_BUS_PCI) { setup_sedlbauer()
753 val = readreg(cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_ADR, setup_sedlbauer()
754 cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC, IPAC_ID); setup_sedlbauer()
758 cs->subtyp = SEDL_SPEED_WIN2_PC104; setup_sedlbauer()
759 if (cs->hw.sedl.bus == SEDL_BUS_PCMCIA) { setup_sedlbauer()
760 cs->subtyp = SEDL_SPEED_STAR2; setup_sedlbauer()
762 cs->hw.sedl.chip = SEDL_CHIP_IPAC; setup_sedlbauer()
765 if (cs->hw.sedl.chip == SEDL_CHIP_TEST) { setup_sedlbauer()
766 cs->hw.sedl.chip = SEDL_CHIP_ISAC_HSCX; setup_sedlbauer()
775 Sedlbauer_Types[cs->subtyp]); setup_sedlbauer()
777 setup_isac(cs); setup_sedlbauer()
778 if (cs->hw.sedl.chip == SEDL_CHIP_IPAC) { setup_sedlbauer()
779 if (cs->hw.sedl.bus == SEDL_BUS_PCI) { setup_sedlbauer()
780 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_ADR; setup_sedlbauer()
781 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_IPAC; setup_sedlbauer()
782 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_PCI_IPAC; setup_sedlbauer()
784 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_ADR; setup_sedlbauer()
785 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC; setup_sedlbauer()
786 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_IPAC_ANY_IPAC; setup_sedlbauer()
788 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_sedlbauer()
789 cs->readisac = &ReadISAC_IPAC; setup_sedlbauer()
790 cs->writeisac = &WriteISAC_IPAC; setup_sedlbauer()
791 cs->readisacfifo = &ReadISACfifo_IPAC; setup_sedlbauer()
792 cs->writeisacfifo = &WriteISACfifo_IPAC; setup_sedlbauer()
793 cs->irq_func = &sedlbauer_interrupt_ipac; setup_sedlbauer()
794 val = readreg(cs->hw.sedl.adr, cs->hw.sedl.isac, IPAC_ID); setup_sedlbauer()
798 cs->readisac = &ReadISAC; setup_sedlbauer()
799 cs->writeisac = &WriteISAC; setup_sedlbauer()
800 cs->readisacfifo = &ReadISACfifo; setup_sedlbauer()
801 cs->writeisacfifo = &WriteISACfifo; setup_sedlbauer()
802 if (cs->hw.sedl.chip == SEDL_CHIP_ISAC_ISAR) { setup_sedlbauer()
803 if (cs->hw.sedl.bus == SEDL_BUS_PCI) { setup_sedlbauer()
804 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + setup_sedlbauer()
806 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + setup_sedlbauer()
808 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer()
811 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + setup_sedlbauer()
813 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + setup_sedlbauer()
815 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + setup_sedlbauer()
817 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + setup_sedlbauer()
819 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + setup_sedlbauer()
822 cs->bcs[0].hw.isar.reg = &cs->hw.sedl.isar; setup_sedlbauer()
823 cs->bcs[1].hw.isar.reg = &cs->hw.sedl.isar; setup_sedlbauer()
824 test_and_set_bit(HW_ISAR, &cs->HW_Flags); setup_sedlbauer()
825 cs->irq_func = &sedlbauer_interrupt_isar; setup_sedlbauer()
826 cs->auxcmd = &isar_auxcmd; setup_sedlbauer()
827 ISACVersion(cs, "Sedlbauer:"); setup_sedlbauer()
828 cs->BC_Read_Reg = &ReadISAR; setup_sedlbauer()
829 cs->BC_Write_Reg = &WriteISAR; setup_sedlbauer()
830 cs->BC_Send_Data = &isar_fill_fifo; setup_sedlbauer()
833 ver = ISARVersion(cs, "Sedlbauer:"); setup_sedlbauer()
839 reset_sedlbauer(cs); setup_sedlbauer()
843 release_io_sedlbauer(cs); setup_sedlbauer()
847 if (cs->hw.sedl.bus == SEDL_BUS_PCMCIA) { setup_sedlbauer()
848 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_ADR; setup_sedlbauer()
849 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_ISAC; setup_sedlbauer()
850 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_HSCX; setup_sedlbauer()
851 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_RESET; setup_sedlbauer()
852 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + SEDL_HSCX_PCMCIA_RESET; setup_sedlbauer()
853 cs->irq_flags |= IRQF_SHARED; setup_sedlbauer()
855 cs->hw.sedl.adr = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_ADR; setup_sedlbauer()
856 cs->hw.sedl.isac = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_ISAC; setup_sedlbauer()
857 cs->hw.sedl.hscx = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_HSCX; setup_sedlbauer()
858 cs->hw.sedl.reset_on = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_RESET_ON; setup_sedlbauer()
859 cs->hw.sedl.reset_off = cs->hw.sedl.cfg_reg + SEDL_HSCX_ISA_RESET_OFF; setup_sedlbauer()
861 cs->irq_func = &sedlbauer_interrupt; setup_sedlbauer()
862 ISACVersion(cs, "Sedlbauer:"); setup_sedlbauer()
864 if (HscxVersion(cs, "Sedlbauer:")) { setup_sedlbauer()
867 release_io_sedlbauer(cs); setup_sedlbauer()
|
| H A D | ipacx.c | 35 static void ph_command(struct IsdnCardState *cs, unsigned int command);
36 static inline void cic_int(struct IsdnCardState *cs);
38 static void dbusy_timer_handler(struct IsdnCardState *cs);
39 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
40 static void dch_fill_fifo(struct IsdnCardState *cs);
41 static inline void dch_int(struct IsdnCardState *cs);
42 static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
43 static void dch_init(struct IsdnCardState *cs);
47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
50 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
52 static void bch_init(struct IsdnCardState *cs, int hscx);
53 static void clear_pending_ints(struct IsdnCardState *cs);
59 ph_command(struct IsdnCardState *cs, unsigned int command) ph_command() argument
61 if (cs->debug & L1_DEB_ISAC) ph_command()
62 debugl1(cs, "ph_command (%#x) in (%#x)", command, ph_command()
63 cs->dc.isac.ph_state); ph_command()
67 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E); ph_command()
74 cic_int(struct IsdnCardState *cs) cic_int() argument
78 event = cs->readisac(cs, IPACX_CIR0) >> 4; cic_int()
79 if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event); cic_int()
83 cs->dc.isac.ph_state = event; cic_int()
84 schedule_event(cs, D_L1STATECHANGE); cic_int()
97 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; dch_l2l1() local
103 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); dch_l2l1()
104 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); dch_l2l1()
105 if (cs->tx_skb) { dch_l2l1()
106 skb_queue_tail(&cs->sq, skb); dch_l2l1()
108 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0); dch_l2l1()
111 cs->tx_skb = skb; dch_l2l1()
112 cs->tx_cnt = 0; dch_l2l1()
114 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0); dch_l2l1()
116 dch_fill_fifo(cs); dch_l2l1()
121 if (cs->tx_skb) { dch_l2l1()
122 if (cs->debug & L1_DEB_WARN) dch_l2l1()
123 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); dch_l2l1()
124 skb_queue_tail(&cs->sq, skb); dch_l2l1()
127 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); dch_l2l1()
128 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); dch_l2l1()
129 cs->tx_skb = skb; dch_l2l1()
130 cs->tx_cnt = 0; dch_l2l1()
132 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); dch_l2l1()
134 dch_fill_fifo(cs); dch_l2l1()
139 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL"); dch_l2l1()
141 if (!cs->tx_skb) { dch_l2l1()
150 if ((cs->dc.isac.ph_state == IPACX_IND_RES) || dch_l2l1()
151 (cs->dc.isac.ph_state == IPACX_IND_DR) || dch_l2l1()
152 (cs->dc.isac.ph_state == IPACX_IND_DC)) dch_l2l1()
153 ph_command(cs, IPACX_CMD_TIM); dch_l2l1()
155 ph_command(cs, IPACX_CMD_RES); dch_l2l1()
159 ph_command(cs, IPACX_CMD_AR8); dch_l2l1()
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1 dch_l2l1()
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1 dch_l2l1()
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR); dch_l2l1()
166 (void) cs->readisac(cs, IPACX_CDA2_CR); dch_l2l1()
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a); dch_l2l1()
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a); dch_l2l1()
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14); dch_l2l1()
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14); dch_l2l1()
182 skb_queue_purge(&cs->rq); dch_l2l1()
183 skb_queue_purge(&cs->sq); dch_l2l1()
184 if (cs->tx_skb) { dch_l2l1()
185 dev_kfree_skb_any(cs->tx_skb); dch_l2l1()
186 cs->tx_skb = NULL; dch_l2l1()
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) dch_l2l1()
189 del_timer(&cs->dbusytimer); dch_l2l1()
193 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr); dch_l2l1()
201 dbusy_timer_handler(struct IsdnCardState *cs) dbusy_timer_handler() argument
206 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dbusy_timer_handler()
207 rbchd = cs->readisac(cs, IPACX_RBCHD); dbusy_timer_handler()
208 stard = cs->readisac(cs, IPACX_STARD); dbusy_timer_handler()
209 if (cs->debug) dbusy_timer_handler()
210 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard); dbusy_timer_handler()
212 set_bit(FLG_L1_DBUSY, &cs->HW_Flags); dbusy_timer_handler()
213 for (st = cs->stlist; st; st = st->next) { dbusy_timer_handler()
218 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); dbusy_timer_handler()
219 if (cs->tx_skb) { dbusy_timer_handler()
220 dev_kfree_skb_any(cs->tx_skb); dbusy_timer_handler()
221 cs->tx_cnt = 0; dbusy_timer_handler()
222 cs->tx_skb = NULL; dbusy_timer_handler()
225 debugl1(cs, "D-Channel Busy no skb"); dbusy_timer_handler()
227 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR dbusy_timer_handler()
236 dch_empty_fifo(struct IsdnCardState *cs, int count) dch_empty_fifo() argument
240 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) dch_empty_fifo()
241 debugl1(cs, "dch_empty_fifo()"); dch_empty_fifo()
244 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { dch_empty_fifo()
245 if (cs->debug & L1_DEB_WARN) dch_empty_fifo()
246 debugl1(cs, "dch_empty_fifo() incoming message too large"); dch_empty_fifo()
247 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC dch_empty_fifo()
248 cs->rcvidx = 0; dch_empty_fifo()
252 ptr = cs->rcvbuf + cs->rcvidx; dch_empty_fifo()
253 cs->rcvidx += count; dch_empty_fifo()
255 cs->readisacfifo(cs, ptr, count); dch_empty_fifo()
256 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC dch_empty_fifo()
258 if (cs->debug & L1_DEB_ISAC_FIFO) { dch_empty_fifo()
259 char *t = cs->dlog; dch_empty_fifo()
263 debugl1(cs, "%s", cs->dlog); dch_empty_fifo()
271 dch_fill_fifo(struct IsdnCardState *cs) dch_fill_fifo() argument
276 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) dch_fill_fifo()
277 debugl1(cs, "dch_fill_fifo()"); dch_fill_fifo()
279 if (!cs->tx_skb) return; dch_fill_fifo()
280 count = cs->tx_skb->len; dch_fill_fifo()
290 ptr = cs->tx_skb->data; dch_fill_fifo()
291 skb_pull(cs->tx_skb, count); dch_fill_fifo()
292 cs->tx_cnt += count; dch_fill_fifo()
293 cs->writeisacfifo(cs, ptr, count); dch_fill_fifo()
294 cs->writeisac(cs, IPACX_CMDRD, cmd); dch_fill_fifo()
297 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { dch_fill_fifo()
298 debugl1(cs, "dch_fill_fifo dbusytimer running"); dch_fill_fifo()
299 del_timer(&cs->dbusytimer); dch_fill_fifo()
301 init_timer(&cs->dbusytimer); dch_fill_fifo()
302 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); dch_fill_fifo()
303 add_timer(&cs->dbusytimer); dch_fill_fifo()
305 if (cs->debug & L1_DEB_ISAC_FIFO) { dch_fill_fifo()
306 char *t = cs->dlog; dch_fill_fifo()
310 debugl1(cs, "%s", cs->dlog); dch_fill_fifo()
318 dch_int(struct IsdnCardState *cs) dch_int() argument
324 istad = cs->readisac(cs, IPACX_ISTAD); dch_int()
330 rstad = cs->readisac(cs, IPACX_RSTAD); dch_int()
333 if (cs->debug & L1_DEB_WARN) dch_int()
334 debugl1(cs, "dch_int(): invalid frame"); dch_int()
336 if (cs->debug & L1_DEB_WARN) dch_int()
337 debugl1(cs, "dch_int(): RDO"); dch_int()
339 if (cs->debug & L1_DEB_WARN) dch_int()
340 debugl1(cs, "dch_int(): CRC error"); dch_int()
341 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC dch_int()
343 count = cs->readisac(cs, IPACX_RBCLD); dch_int()
347 dch_empty_fifo(cs, count); dch_int()
348 if ((count = cs->rcvidx) > 0) { dch_int()
349 cs->rcvidx = 0; dch_int()
353 memcpy(skb_put(skb, count), cs->rcvbuf, count); dch_int()
354 skb_queue_tail(&cs->rq, skb); dch_int()
358 cs->rcvidx = 0; dch_int()
359 schedule_event(cs, D_RCVBUFREADY); dch_int()
363 dch_empty_fifo(cs, D_FIFO_SIZE); dch_int()
367 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO"); dch_int()
368 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES dch_int()
372 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) dch_int()
373 del_timer(&cs->dbusytimer); dch_int()
374 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) dch_int()
375 schedule_event(cs, D_CLEARBUSY); dch_int()
376 if (cs->tx_skb) { dch_int()
377 if (cs->tx_skb->len) { dch_int()
378 dch_fill_fifo(cs); dch_int()
382 dev_kfree_skb_irq(cs->tx_skb); dch_int()
383 cs->tx_skb = NULL; dch_int()
384 cs->tx_cnt = 0; dch_int()
387 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { dch_int()
388 cs->tx_cnt = 0; dch_int()
389 dch_fill_fifo(cs); dch_int()
392 schedule_event(cs, D_XMTBUFREADY); dch_int()
398 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU"); dch_int()
399 if (cs->tx_skb) { dch_int()
400 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit dch_int()
401 cs->tx_cnt = 0; dch_int()
402 dch_fill_fifo(cs); dch_int()
405 debugl1(cs, "ISAC XDU no skb"); dch_int()
413 dch_setstack(struct PStack *st, struct IsdnCardState *cs) dch_setstack() argument
421 dch_init(struct IsdnCardState *cs) dch_init() argument
425 cs->setstack_d = dch_setstack; dch_init()
427 cs->dbusytimer.function = (void *) dbusy_timer_handler; dch_init()
428 cs->dbusytimer.data = (long) cs; dch_init()
429 init_timer(&cs->dbusytimer); dch_init()
431 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD dch_init()
432 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter dch_init()
433 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go dch_init()
434 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel dch_init()
454 spin_lock_irqsave(&bcs->cs->lock, flags); bch_l2l1()
463 spin_unlock_irqrestore(&bcs->cs->lock, flags); bch_l2l1()
466 spin_lock_irqsave(&bcs->cs->lock, flags); bch_l2l1()
475 spin_unlock_irqrestore(&bcs->cs->lock, flags); bch_l2l1()
485 spin_lock_irqsave(&bcs->cs->lock, flags); bch_l2l1()
488 spin_unlock_irqrestore(&bcs->cs->lock, flags); bch_l2l1()
495 spin_lock_irqsave(&bcs->cs->lock, flags); bch_l2l1()
499 spin_unlock_irqrestore(&bcs->cs->lock, flags); bch_l2l1()
512 struct IsdnCardState *cs; bch_empty_fifo() local
515 cs = bcs->cs; bch_empty_fifo()
517 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) bch_empty_fifo()
518 debugl1(cs, "bch_empty_fifo()"); bch_empty_fifo()
522 if (cs->debug & L1_DEB_WARN) bch_empty_fifo()
523 debugl1(cs, "bch_empty_fifo() incoming packet too large"); bch_empty_fifo()
524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo()
531 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); bch_empty_fifo()
532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo()
537 if (cs->debug & L1_DEB_HSCX_FIFO) { bch_empty_fifo()
542 debugl1(cs, "%s", bcs->blog); bch_empty_fifo()
552 struct IsdnCardState *cs; bch_fill_fifo() local
556 cs = bcs->cs; bch_fill_fifo()
557 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) bch_fill_fifo()
558 debugl1(cs, "bch_fill_fifo()"); bch_fill_fifo()
577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); bch_fill_fifo()
578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); bch_fill_fifo()
580 if (cs->debug & L1_DEB_HSCX_FIFO) { bch_fill_fifo()
585 debugl1(cs, "%s", bcs->blog); bch_fill_fifo()
593 bch_int(struct IsdnCardState *cs, u_char hscx) bch_int() argument
601 bcs = cs->bcs + hscx; bch_int()
602 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB); bch_int()
609 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB); bch_int()
612 if (cs->debug & L1_DEB_WARN) bch_int()
613 debugl1(cs, "bch_int() B-%d: invalid frame", hscx); bch_int()
615 if (cs->debug & L1_DEB_WARN) bch_int()
616 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); bch_int()
618 if (cs->debug & L1_DEB_WARN) bch_int()
619 debugl1(cs, "bch_int() B-%d: CRC error", hscx); bch_int()
620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_int()
623 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1); bch_int()
627 if (cs->debug & L1_DEB_HSCX_FIFO) bch_int()
628 debugl1(cs, "bch_int Frame %d", count); bch_int()
658 if (cs->debug & L1_DEB_WARN) bch_int()
659 debugl1(cs, "bch_int() B-%d: RFO error", hscx); bch_int()
660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES bch_int()
703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES bch_int()
704 if (cs->debug & L1_DEB_WARN) bch_int()
705 debugl1(cs, "bch_int() B-%d XDU error", hscx); bch_int()
715 struct IsdnCardState *cs = bcs->cs; bch_mode() local
719 if (cs->debug & L1_DEB_HSCX) bch_mode()
720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc); bch_mode()
727 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc); bch_mode()
728 cs->writeisac(cs, IPACX_BCHA_CR, 0x88); bch_mode()
732 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc); bch_mode()
733 cs->writeisac(cs, IPACX_BCHB_CR, 0x88); bch_mode()
738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off bch_mode()
739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. bch_mode()
740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off bch_mode()
741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode bch_mode()
745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 bch_mode()
746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode()
750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 bch_mode()
751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled bch_mode()
752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode()
782 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs) bch_open_state() argument
828 bch_init(struct IsdnCardState *cs, int hscx) bch_init() argument
830 cs->bcs[hscx].BC_SetStack = bch_setstack; bch_init()
831 cs->bcs[hscx].BC_Close = bch_close_state; bch_init()
832 cs->bcs[hscx].hw.hscx.hscx = hscx; bch_init()
833 cs->bcs[hscx].cs = cs; bch_init()
834 bch_mode(cs->bcs + hscx, 0, hscx); bch_init()
846 interrupt_ipacx(struct IsdnCardState *cs) interrupt_ipacx() argument
850 while ((ista = cs->readisac(cs, IPACX_ISTA))) { interrupt_ipacx()
854 if (ista & 0x80) bch_int(cs, 0); // B channel interrupts interrupt_ipacx()
855 if (ista & 0x40) bch_int(cs, 1); interrupt_ipacx()
857 if (ista & 0x01) dch_int(cs); // D channel interrupt_ipacx()
858 if (ista & 0x10) cic_int(cs); // Layer 1 state interrupt_ipacx()
866 clear_pending_ints(struct IsdnCardState *cs) clear_pending_ints() argument
871 cs->writeisac(cs, IPACX_MASK, 0xff); clear_pending_ints()
872 cs->writeisac(cs, IPACX_MASKD, 0xff); clear_pending_ints()
873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff); clear_pending_ints()
874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff); clear_pending_ints()
876 ista = cs->readisac(cs, IPACX_ISTA); clear_pending_ints()
877 if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB); clear_pending_ints()
878 if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB); clear_pending_ints()
879 if (ista & 0x10) cs->readisac(cs, IPACX_CIR0); clear_pending_ints()
880 if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD); clear_pending_ints()
888 init_ipacx(struct IsdnCardState *cs, int part) init_ipacx() argument
894 clear_pending_ints(cs); init_ipacx()
895 bch_init(cs, 0); init_ipacx()
896 bch_init(cs, 1); init_ipacx()
897 dch_init(cs); init_ipacx()
900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK); init_ipacx()
901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK); init_ipacx()
902 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK); init_ipacx()
903 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register init_ipacx()
906 cs->writeisac(cs, IPACX_CMDRD, 0x41); init_ipacx()
907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41); init_ipacx()
908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41); init_ipacx()
909 ph_command(cs, IPACX_CMD_RES); init_ipacx()
|
| H A D | avm_a1p.c | 62 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
67 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); ReadISAC()
68 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); ReadISAC()
73 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
76 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); WriteISAC()
77 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); WriteISAC()
81 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
83 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); ReadISACfifo()
84 insb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); ReadISACfifo()
88 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
90 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); WriteISACfifo()
91 outsb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); WriteISACfifo()
95 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
100 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ReadHSCX()
102 ret = bytein(cs->hw.avm.cfg_reg + DATAREG_OFFSET); ReadHSCX()
107 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
110 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, WriteHSCX()
112 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); WriteHSCX()
116 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) ReadHSCXfifo() argument
118 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ReadHSCXfifo()
120 insb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); ReadHSCXfifo()
124 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) WriteHSCXfifo() argument
126 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, WriteHSCXfifo()
128 outsb(cs->hw.avm.cfg_reg + DATAREG_OFFSET, data, size); WriteHSCXfifo()
135 #define READHSCX(cs, nr, reg) ReadHSCX(cs, nr, reg)
136 #define WRITEHSCX(cs, nr, reg, data) WriteHSCX(cs, nr, reg, data)
137 #define READHSCXFIFO(cs, nr, ptr, cnt) ReadHSCXfifo(cs, nr, ptr, cnt)
138 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) WriteHSCXfifo(cs, nr, ptr, cnt)
145 struct IsdnCardState *cs = dev_id; avm_a1p_interrupt() local
149 spin_lock_irqsave(&cs->lock, flags); avm_a1p_interrupt()
150 while ((sval = (~bytein(cs->hw.avm.cfg_reg + ASL0_OFFSET) & ASL0_R_IRQPENDING))) { avm_a1p_interrupt()
151 if (cs->debug & L1_DEB_INTSTAT) avm_a1p_interrupt()
152 debugl1(cs, "avm IntStatus %x", sval); avm_a1p_interrupt()
154 val = ReadHSCX(cs, 1, HSCX_ISTA); avm_a1p_interrupt()
156 hscx_int_main(cs, val); avm_a1p_interrupt()
159 val = ReadISAC(cs, ISAC_ISTA); avm_a1p_interrupt()
161 isac_interrupt(cs, val); avm_a1p_interrupt()
164 WriteHSCX(cs, 0, HSCX_MASK, 0xff); avm_a1p_interrupt()
165 WriteHSCX(cs, 1, HSCX_MASK, 0xff); avm_a1p_interrupt()
166 WriteISAC(cs, ISAC_MASK, 0xff); avm_a1p_interrupt()
167 WriteISAC(cs, ISAC_MASK, 0x00); avm_a1p_interrupt()
168 WriteHSCX(cs, 0, HSCX_MASK, 0x00); avm_a1p_interrupt()
169 WriteHSCX(cs, 1, HSCX_MASK, 0x00); avm_a1p_interrupt()
170 spin_unlock_irqrestore(&cs->lock, flags); avm_a1p_interrupt()
175 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg) AVM_card_msg() argument
181 spin_lock_irqsave(&cs->lock, flags); AVM_card_msg()
182 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, 0x00); AVM_card_msg()
184 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, ASL0_W_RESET); AVM_card_msg()
186 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, 0x00); AVM_card_msg()
187 spin_unlock_irqrestore(&cs->lock, flags); AVM_card_msg()
192 /* free_irq(cs->irq, cs); */ AVM_card_msg()
196 spin_lock_irqsave(&cs->lock, flags); AVM_card_msg()
197 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, ASL0_W_TDISABLE | ASL0_W_TRESET | ASL0_W_IRQENABLE); AVM_card_msg()
198 clear_pending_isac_ints(cs); AVM_card_msg()
199 clear_pending_hscx_ints(cs); AVM_card_msg()
200 inithscxisac(cs, 1); AVM_card_msg()
201 inithscxisac(cs, 2); AVM_card_msg()
202 spin_unlock_irqrestore(&cs->lock, flags); AVM_card_msg()
219 struct IsdnCardState *cs = card->cs; setup_avm_a1_pcmcia() local
226 if (cs->typ != ISDN_CTYPE_A1_PCMCIA) setup_avm_a1_pcmcia()
229 cs->hw.avm.cfg_reg = card->para[1]; setup_avm_a1_pcmcia()
230 cs->irq = card->para[0]; setup_avm_a1_pcmcia()
233 byteout(cs->hw.avm.cfg_reg + ASL1_OFFSET, ASL1_W_ENABLE_S0); setup_avm_a1_pcmcia()
234 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, 0x00); setup_avm_a1_pcmcia()
236 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, ASL0_W_RESET); setup_avm_a1_pcmcia()
238 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, 0x00); setup_avm_a1_pcmcia()
240 byteout(cs->hw.avm.cfg_reg + ASL0_OFFSET, ASL0_W_TDISABLE | ASL0_W_TRESET); setup_avm_a1_pcmcia()
242 model = bytein(cs->hw.avm.cfg_reg + MODREG_OFFSET); setup_avm_a1_pcmcia()
243 vers = bytein(cs->hw.avm.cfg_reg + VERREG_OFFSET); setup_avm_a1_pcmcia()
246 cs->hw.avm.cfg_reg, cs->irq, model, vers); setup_avm_a1_pcmcia()
248 setup_isac(cs); setup_avm_a1_pcmcia()
249 cs->readisac = &ReadISAC; setup_avm_a1_pcmcia()
250 cs->writeisac = &WriteISAC; setup_avm_a1_pcmcia()
251 cs->readisacfifo = &ReadISACfifo; setup_avm_a1_pcmcia()
252 cs->writeisacfifo = &WriteISACfifo; setup_avm_a1_pcmcia()
253 cs->BC_Read_Reg = &ReadHSCX; setup_avm_a1_pcmcia()
254 cs->BC_Write_Reg = &WriteHSCX; setup_avm_a1_pcmcia()
255 cs->BC_Send_Data = &hscx_fill_fifo; setup_avm_a1_pcmcia()
256 cs->cardmsg = &AVM_card_msg; setup_avm_a1_pcmcia()
257 cs->irq_flags = IRQF_SHARED; setup_avm_a1_pcmcia()
258 cs->irq_func = &avm_a1p_interrupt; setup_avm_a1_pcmcia()
260 ISACVersion(cs, "AVM A1 PCMCIA:"); setup_avm_a1_pcmcia()
261 if (HscxVersion(cs, "AVM A1 PCMCIA:")) { setup_avm_a1_pcmcia()
|
| H A D | hfc_pci.c | 73 release_io_hfcpci(struct IsdnCardState *cs) release_io_hfcpci() argument
76 cs->hw.hfcpci.pci_io); release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); release_io_hfcpci()
79 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ release_io_hfcpci()
81 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); release_io_hfcpci()
84 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */ release_io_hfcpci()
85 del_timer(&cs->hw.hfcpci.timer); release_io_hfcpci()
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, release_io_hfcpci()
87 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); release_io_hfcpci()
88 cs->hw.hfcpci.fifos = NULL; release_io_hfcpci()
89 iounmap((void *)cs->hw.hfcpci.pci_io); release_io_hfcpci()
97 reset_hfcpci(struct IsdnCardState *cs) reset_hfcpci() argument
99 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */ reset_hfcpci()
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ reset_hfcpci()
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); reset_hfcpci()
104 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */ reset_hfcpci()
105 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ reset_hfcpci()
107 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ reset_hfcpci()
109 if (Read_hfc(cs, HFCPCI_STATUS) & 2) reset_hfcpci()
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */ reset_hfcpci()
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); reset_hfcpci()
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ reset_hfcpci()
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); reset_hfcpci()
118 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */ reset_hfcpci()
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE; reset_hfcpci()
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ reset_hfcpci()
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */ reset_hfcpci()
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */ reset_hfcpci()
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; reset_hfcpci()
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); reset_hfcpci()
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | reset_hfcpci()
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); reset_hfcpci()
131 if (Read_hfc(cs, HFCPCI_INT_S1)); reset_hfcpci()
133 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */ reset_hfcpci()
135 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */ reset_hfcpci()
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */ reset_hfcpci()
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); reset_hfcpci()
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ reset_hfcpci()
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); reset_hfcpci()
141 cs->hw.hfcpci.sctrl_r = 0; reset_hfcpci()
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); reset_hfcpci()
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */ reset_hfcpci()
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); reset_hfcpci()
153 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ reset_hfcpci()
154 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ reset_hfcpci()
155 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ reset_hfcpci()
156 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ reset_hfcpci()
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE; reset_hfcpci()
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); reset_hfcpci()
161 if (Read_hfc(cs, HFCPCI_INT_S1)); reset_hfcpci()
168 hfcpci_Timer(struct IsdnCardState *cs) hfcpci_Timer() argument
170 cs->hw.hfcpci.timer.expires = jiffies + 75; hfcpci_Timer()
172 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80); hfcpci_Timer()
173 add_timer(&cs->hw.hfcpci.timer); hfcpci_Timer()
182 sched_event_D_pci(struct IsdnCardState *cs, int event) sched_event_D_pci() argument
184 test_and_set_bit(event, &cs->event); sched_event_D_pci()
185 schedule_work(&cs->tqueue); sched_event_D_pci()
203 Sel_BCS(struct IsdnCardState *cs, int channel) Sel_BCS() argument
205 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) Sel_BCS()
206 return (&cs->bcs[0]); Sel_BCS()
207 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) Sel_BCS()
208 return (&cs->bcs[1]); Sel_BCS()
216 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo) hfcpci_clear_fifo_rx() argument
221 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; hfcpci_clear_fifo_rx()
222 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX; hfcpci_clear_fifo_rx()
224 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; hfcpci_clear_fifo_rx()
225 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX; hfcpci_clear_fifo_rx()
228 cs->hw.hfcpci.fifo_en ^= fifo_state; hfcpci_clear_fifo_rx()
229 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); hfcpci_clear_fifo_rx()
230 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0; hfcpci_clear_fifo_rx()
236 cs->hw.hfcpci.fifo_en |= fifo_state; hfcpci_clear_fifo_rx()
237 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); hfcpci_clear_fifo_rx()
243 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo) hfcpci_clear_fifo_tx() argument
248 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; hfcpci_clear_fifo_tx()
249 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX; hfcpci_clear_fifo_tx()
251 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; hfcpci_clear_fifo_tx()
252 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX; hfcpci_clear_fifo_tx()
255 cs->hw.hfcpci.fifo_en ^= fifo_state; hfcpci_clear_fifo_tx()
256 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); hfcpci_clear_fifo_tx()
262 cs->hw.hfcpci.fifo_en |= fifo_state; hfcpci_clear_fifo_tx()
263 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); hfcpci_clear_fifo_tx()
275 struct IsdnCardState *cs = bcs->cs; hfcpci_empty_fifo() local
279 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hfcpci_empty_fifo()
280 debugl1(cs, "hfcpci_empty_fifo"); hfcpci_empty_fifo()
288 if (cs->debug & L1_DEB_WARN) hfcpci_empty_fifo()
289 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count); hfcpci_empty_fifo()
329 receive_dmsg(struct IsdnCardState *cs) receive_dmsg() argument
339 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx; receive_dmsg()
340 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { receive_dmsg()
341 debugl1(cs, "rec_dmsg blocked"); receive_dmsg()
350 if (cs->debug & L1_DEB_ISAC) receive_dmsg()
351 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)", receive_dmsg()
356 if (cs->debug & L1_DEB_WARN) receive_dmsg()
357 debugl1(cs, "empty_fifo hfcpci packet inv. len %d or crc %d", rcnt, df->data[zp->z1]); receive_dmsg()
359 cs->err_rx++; receive_dmsg()
385 skb_queue_tail(&cs->rq, skb); receive_dmsg()
386 sched_event_D_pci(cs, D_RCVBUFREADY); receive_dmsg()
390 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); receive_dmsg()
452 struct IsdnCardState *cs = bcs->cs; main_rec_hfcpci() local
461 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { main_rec_hfcpci()
462 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; main_rec_hfcpci()
463 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; main_rec_hfcpci()
466 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; main_rec_hfcpci()
467 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1; main_rec_hfcpci()
472 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { main_rec_hfcpci()
473 debugl1(cs, "rec_data %d blocked", bcs->channel); main_rec_hfcpci()
477 if (cs->debug & L1_DEB_HSCX) main_rec_hfcpci()
478 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)", main_rec_hfcpci()
486 if (cs->debug & L1_DEB_HSCX) main_rec_hfcpci()
487 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)", main_rec_hfcpci()
496 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) { main_rec_hfcpci()
498 hfcpci_clear_fifo_rx(cs, real_fifo); main_rec_hfcpci()
500 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt; main_rec_hfcpci()
509 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); main_rec_hfcpci()
518 hfcpci_fill_dfifo(struct IsdnCardState *cs) hfcpci_fill_dfifo() argument
525 if (!cs->tx_skb) hfcpci_fill_dfifo()
527 if (cs->tx_skb->len <= 0) hfcpci_fill_dfifo()
530 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx; hfcpci_fill_dfifo()
532 if (cs->debug & L1_DEB_ISAC) hfcpci_fill_dfifo()
533 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)", hfcpci_fill_dfifo()
540 if (cs->debug & L1_DEB_ISAC) hfcpci_fill_dfifo()
541 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames"); hfcpci_fill_dfifo()
543 cs->err_tx++; hfcpci_fill_dfifo()
552 if (cs->debug & L1_DEB_ISAC) hfcpci_fill_dfifo()
553 debugl1(cs, "hfcpci_fill_Dfifo count(%u/%d)", hfcpci_fill_dfifo()
554 cs->tx_skb->len, count); hfcpci_fill_dfifo()
555 if (count < cs->tx_skb->len) { hfcpci_fill_dfifo()
556 if (cs->debug & L1_DEB_ISAC) hfcpci_fill_dfifo()
557 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem"); hfcpci_fill_dfifo()
560 count = cs->tx_skb->len; /* get frame len */ hfcpci_fill_dfifo()
563 src = cs->tx_skb->data; /* source pointer */ hfcpci_fill_dfifo()
580 dev_kfree_skb_any(cs->tx_skb); hfcpci_fill_dfifo()
581 cs->tx_skb = NULL; hfcpci_fill_dfifo()
590 struct IsdnCardState *cs = bcs->cs; hfcpci_fill_fifo() local
603 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { hfcpci_fill_fifo()
604 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; hfcpci_fill_fifo()
605 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2; hfcpci_fill_fifo()
607 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; hfcpci_fill_fifo()
608 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1; hfcpci_fill_fifo()
614 if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
615 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)", hfcpci_fill_fifo()
646 } else if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
647 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded", hfcpci_fill_fifo()
665 if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
666 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)", hfcpci_fill_fifo()
674 if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
675 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames"); hfcpci_fill_fifo()
683 if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
684 debugl1(cs, "hfcpci_fill_fifo %d count(%u/%d),%lx", hfcpci_fill_fifo()
689 if (cs->debug & L1_DEB_HSCX) hfcpci_fill_fifo()
690 debugl1(cs, "hfcpci_fill_fifo no fifo mem"); hfcpci_fill_fifo()
736 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; dch_nt_l2l1() local
749 debugl1(cs, "PH_TEST_LOOP B1"); dch_nt_l2l1()
751 debugl1(cs, "PH_TEST_LOOP B2"); dch_nt_l2l1()
753 debugl1(cs, "PH_TEST_LOOP DISABLED"); dch_nt_l2l1()
757 if (cs->debug) dch_nt_l2l1()
758 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); dch_nt_l2l1()
769 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) hfcpci_auxcmd() argument
775 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) { hfcpci_auxcmd()
776 spin_lock_irqsave(&cs->lock, flags); hfcpci_auxcmd()
777 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */ hfcpci_auxcmd()
778 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */ hfcpci_auxcmd()
780 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT; hfcpci_auxcmd()
781 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ hfcpci_auxcmd()
783 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */ hfcpci_auxcmd()
785 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); hfcpci_auxcmd()
786 cs->dc.hfcpci.ph_state = 1; hfcpci_auxcmd()
787 cs->hw.hfcpci.nt_mode = 1; hfcpci_auxcmd()
788 cs->hw.hfcpci.nt_timer = 0; hfcpci_auxcmd()
789 cs->stlist->l2.l2l1 = dch_nt_l2l1; hfcpci_auxcmd()
790 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_auxcmd()
791 debugl1(cs, "NT mode activated"); hfcpci_auxcmd()
794 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) || hfcpci_auxcmd()
795 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12)) hfcpci_auxcmd()
798 spin_lock_irqsave(&cs->lock, flags); hfcpci_auxcmd()
800 cs->logecho = 1; hfcpci_auxcmd()
801 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */ hfcpci_auxcmd()
802 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC; hfcpci_auxcmd()
803 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX; hfcpci_auxcmd()
805 cs->logecho = 0; hfcpci_auxcmd()
806 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */ hfcpci_auxcmd()
807 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC; hfcpci_auxcmd()
808 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX; hfcpci_auxcmd()
810 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; hfcpci_auxcmd()
811 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; hfcpci_auxcmd()
812 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */ hfcpci_auxcmd()
813 cs->hw.hfcpci.ctmt &= ~2; hfcpci_auxcmd()
814 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); hfcpci_auxcmd()
815 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); hfcpci_auxcmd()
816 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); hfcpci_auxcmd()
818 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); hfcpci_auxcmd()
819 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); hfcpci_auxcmd()
821 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_auxcmd()
829 receive_emsg(struct IsdnCardState *cs) receive_emsg() argument
840 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; receive_emsg()
841 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; receive_emsg()
844 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { receive_emsg()
845 debugl1(cs, "echo_rec_data blocked"); receive_emsg()
849 if (cs->debug & L1_DEB_ISAC) receive_emsg()
850 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)", receive_emsg()
858 if (cs->debug & L1_DEB_ISAC) receive_emsg()
859 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)", receive_emsg()
867 if (cs->debug & L1_DEB_WARN) receive_emsg()
868 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt); receive_emsg()
892 if (cs->debug & DEB_DLOG_HEX) { receive_emsg()
893 ptr = cs->dlog; receive_emsg()
904 HiSax_putstatus(cs, NULL, "%s", cs->dlog); receive_emsg()
906 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3); receive_emsg()
919 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); receive_emsg()
931 struct IsdnCardState *cs = dev_id; hfcpci_interrupt() local
937 if (!(cs->hw.hfcpci.int_m2 & 0x08)) { hfcpci_interrupt()
938 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2); hfcpci_interrupt()
941 spin_lock_irqsave(&cs->lock, flags); hfcpci_interrupt()
942 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) { hfcpci_interrupt()
943 val = Read_hfc(cs, HFCPCI_INT_S1); hfcpci_interrupt()
944 if (cs->debug & L1_DEB_ISAC) hfcpci_interrupt()
945 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val); hfcpci_interrupt()
947 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_interrupt()
950 if (cs->debug & L1_DEB_ISAC) hfcpci_interrupt()
951 debugl1(cs, "HFC-PCI irq %x %s", val, hfcpci_interrupt()
952 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? hfcpci_interrupt()
954 val &= cs->hw.hfcpci.int_m1; hfcpci_interrupt()
956 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf; hfcpci_interrupt()
957 if (cs->debug & L1_DEB_ISAC) hfcpci_interrupt()
958 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state, hfcpci_interrupt()
960 cs->dc.hfcpci.ph_state = exval; hfcpci_interrupt()
961 sched_event_D_pci(cs, D_L1STATECHANGE); hfcpci_interrupt()
965 if (cs->hw.hfcpci.nt_mode) { hfcpci_interrupt()
966 if ((--cs->hw.hfcpci.nt_timer) < 0) hfcpci_interrupt()
967 sched_event_D_pci(cs, D_L1STATECHANGE); hfcpci_interrupt()
970 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); hfcpci_interrupt()
973 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
974 cs->hw.hfcpci.int_s1 |= val; hfcpci_interrupt()
975 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_interrupt()
978 if (cs->hw.hfcpci.int_s1 & 0x18) { hfcpci_interrupt()
980 val = cs->hw.hfcpci.int_s1; hfcpci_interrupt()
981 cs->hw.hfcpci.int_s1 = exval; hfcpci_interrupt()
984 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { hfcpci_interrupt()
985 if (cs->debug) hfcpci_interrupt()
986 debugl1(cs, "hfcpci spurious 0x08 IRQ"); hfcpci_interrupt()
991 if (cs->logecho) hfcpci_interrupt()
992 receive_emsg(cs); hfcpci_interrupt()
993 else if (!(bcs = Sel_BCS(cs, 1))) { hfcpci_interrupt()
994 if (cs->debug) hfcpci_interrupt()
995 debugl1(cs, "hfcpci spurious 0x10 IRQ"); hfcpci_interrupt()
1000 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { hfcpci_interrupt()
1001 if (cs->debug) hfcpci_interrupt()
1002 debugl1(cs, "hfcpci spurious 0x01 IRQ"); hfcpci_interrupt()
1005 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1007 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1009 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcpci_interrupt()
1012 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1014 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1016 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcpci_interrupt()
1024 if (!(bcs = Sel_BCS(cs, 1))) { hfcpci_interrupt()
1025 if (cs->debug) hfcpci_interrupt()
1026 debugl1(cs, "hfcpci spurious 0x02 IRQ"); hfcpci_interrupt()
1029 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1031 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1033 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcpci_interrupt()
1036 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1038 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1040 debugl1(cs, "fill_data %d blocked", bcs->channel); hfcpci_interrupt()
1048 receive_dmsg(cs); hfcpci_interrupt()
1051 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) hfcpci_interrupt()
1052 del_timer(&cs->dbusytimer); hfcpci_interrupt()
1053 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) hfcpci_interrupt()
1054 sched_event_D_pci(cs, D_CLEARBUSY); hfcpci_interrupt()
1055 if (cs->tx_skb) { hfcpci_interrupt()
1056 if (cs->tx_skb->len) { hfcpci_interrupt()
1057 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1058 hfcpci_fill_dfifo(cs); hfcpci_interrupt()
1059 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1061 debugl1(cs, "hfcpci_fill_dfifo irq blocked"); hfcpci_interrupt()
1065 dev_kfree_skb_irq(cs->tx_skb); hfcpci_interrupt()
1066 cs->tx_cnt = 0; hfcpci_interrupt()
1067 cs->tx_skb = NULL; hfcpci_interrupt()
1070 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { hfcpci_interrupt()
1071 cs->tx_cnt = 0; hfcpci_interrupt()
1072 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_interrupt()
1073 hfcpci_fill_dfifo(cs); hfcpci_interrupt()
1074 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_interrupt()
1076 debugl1(cs, "hfcpci_fill_dfifo irq blocked"); hfcpci_interrupt()
1079 sched_event_D_pci(cs, D_XMTBUFREADY); hfcpci_interrupt()
1082 if (cs->hw.hfcpci.int_s1 && count--) { hfcpci_interrupt()
1083 val = cs->hw.hfcpci.int_s1; hfcpci_interrupt()
1084 cs->hw.hfcpci.int_s1 = 0; hfcpci_interrupt()
1085 if (cs->debug & L1_DEB_ISAC) hfcpci_interrupt()
1086 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count); hfcpci_interrupt()
1090 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_interrupt()
1098 hfcpci_dbusy_timer(struct IsdnCardState *cs) hfcpci_dbusy_timer() argument
1109 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; HFCPCI_l1hw() local
1114 if (cs->debug & DEB_DLOG_HEX) HFCPCI_l1hw()
1115 LogFrame(cs, skb->data, skb->len); HFCPCI_l1hw()
1116 if (cs->debug & DEB_DLOG_VERBOSE) HFCPCI_l1hw()
1117 dlogframe(cs, skb, 0); HFCPCI_l1hw()
1118 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1119 if (cs->tx_skb) { HFCPCI_l1hw()
1120 skb_queue_tail(&cs->sq, skb); HFCPCI_l1hw()
1122 if (cs->debug & L1_DEB_LAPD) HFCPCI_l1hw()
1123 Logl2Frame(cs, skb, "PH_DATA Queued", 0); HFCPCI_l1hw()
1126 cs->tx_skb = skb; HFCPCI_l1hw()
1127 cs->tx_cnt = 0; HFCPCI_l1hw()
1129 if (cs->debug & L1_DEB_LAPD) HFCPCI_l1hw()
1130 Logl2Frame(cs, skb, "PH_DATA", 0); HFCPCI_l1hw()
1132 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCPCI_l1hw()
1133 hfcpci_fill_dfifo(cs); HFCPCI_l1hw()
1134 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCPCI_l1hw()
1136 debugl1(cs, "hfcpci_fill_dfifo blocked"); HFCPCI_l1hw()
1139 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1142 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1143 if (cs->tx_skb) { HFCPCI_l1hw()
1144 if (cs->debug & L1_DEB_WARN) HFCPCI_l1hw()
1145 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); HFCPCI_l1hw()
1146 skb_queue_tail(&cs->sq, skb); HFCPCI_l1hw()
1147 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1150 if (cs->debug & DEB_DLOG_HEX) HFCPCI_l1hw()
1151 LogFrame(cs, skb->data, skb->len); HFCPCI_l1hw()
1152 if (cs->debug & DEB_DLOG_VERBOSE) HFCPCI_l1hw()
1153 dlogframe(cs, skb, 0); HFCPCI_l1hw()
1154 cs->tx_skb = skb; HFCPCI_l1hw()
1155 cs->tx_cnt = 0; HFCPCI_l1hw()
1157 if (cs->debug & L1_DEB_LAPD) HFCPCI_l1hw()
1158 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); HFCPCI_l1hw()
1160 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { HFCPCI_l1hw()
1161 hfcpci_fill_dfifo(cs); HFCPCI_l1hw()
1162 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); HFCPCI_l1hw()
1164 debugl1(cs, "hfcpci_fill_dfifo blocked"); HFCPCI_l1hw()
1165 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1169 if (cs->debug & L1_DEB_LAPD) HFCPCI_l1hw()
1170 debugl1(cs, "-> PH_REQUEST_PULL"); HFCPCI_l1hw()
1172 if (!cs->tx_skb) { HFCPCI_l1hw()
1179 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1180 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */ HFCPCI_l1hw()
1182 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */ HFCPCI_l1hw()
1183 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; HFCPCI_l1hw()
1184 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); HFCPCI_l1hw()
1185 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); HFCPCI_l1hw()
1186 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1187 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); HFCPCI_l1hw()
1190 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1191 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION); HFCPCI_l1hw()
1192 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1195 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1196 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER; HFCPCI_l1hw()
1197 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); HFCPCI_l1hw()
1198 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1201 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1202 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; HFCPCI_l1hw()
1203 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); HFCPCI_l1hw()
1204 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1207 spin_lock_irqsave(&cs->lock, flags); HFCPCI_l1hw()
1210 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */ HFCPCI_l1hw()
1211 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */ HFCPCI_l1hw()
1212 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1; HFCPCI_l1hw()
1213 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); HFCPCI_l1hw()
1217 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */ HFCPCI_l1hw()
1218 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */ HFCPCI_l1hw()
1219 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08; HFCPCI_l1hw()
1220 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); HFCPCI_l1hw()
1224 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1225 if (cs->debug & L1_DEB_WARN) HFCPCI_l1hw()
1226 debugl1(cs, "hfcpci_l1hw loop invalid %4lx", (long) arg); HFCPCI_l1hw()
1229 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */ HFCPCI_l1hw()
1230 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); HFCPCI_l1hw()
1231 spin_unlock_irqrestore(&cs->lock, flags); HFCPCI_l1hw()
1234 if (cs->debug & L1_DEB_WARN) HFCPCI_l1hw()
1235 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr); HFCPCI_l1hw()
1244 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs) setstack_hfcpci() argument
1255 struct IsdnCardState *cs = bcs->cs; hfcpci_send_data() local
1257 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { hfcpci_send_data()
1259 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); hfcpci_send_data()
1261 debugl1(cs, "send_data %d blocked", bcs->channel); hfcpci_send_data()
1270 struct IsdnCardState *cs = bcs->cs; mode_hfcpci() local
1273 if (cs->debug & L1_DEB_HSCX) mode_hfcpci()
1274 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d", mode_hfcpci()
1279 if (cs->chanlimit > 1) { mode_hfcpci()
1280 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1281 cs->hw.hfcpci.sctrl_e &= ~0x80; mode_hfcpci()
1285 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */ mode_hfcpci()
1286 cs->hw.hfcpci.sctrl_e |= 0x80; mode_hfcpci()
1288 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1289 cs->hw.hfcpci.sctrl_e &= ~0x80; mode_hfcpci()
1293 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ mode_hfcpci()
1294 cs->hw.hfcpci.sctrl_e &= ~0x80; mode_hfcpci()
1300 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; mode_hfcpci()
1301 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; mode_hfcpci()
1303 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA; mode_hfcpci()
1304 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA; mode_hfcpci()
1307 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; mode_hfcpci()
1308 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); mode_hfcpci()
1310 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; mode_hfcpci()
1311 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); mode_hfcpci()
1315 hfcpci_clear_fifo_rx(cs, fifo2); mode_hfcpci()
1316 hfcpci_clear_fifo_tx(cs, fifo2); mode_hfcpci()
1318 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; mode_hfcpci()
1319 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; mode_hfcpci()
1321 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; mode_hfcpci()
1322 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; mode_hfcpci()
1325 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; mode_hfcpci()
1326 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); mode_hfcpci()
1327 cs->hw.hfcpci.ctmt |= 2; mode_hfcpci()
1328 cs->hw.hfcpci.conn &= ~0x18; mode_hfcpci()
1330 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; mode_hfcpci()
1331 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); mode_hfcpci()
1332 cs->hw.hfcpci.ctmt |= 1; mode_hfcpci()
1333 cs->hw.hfcpci.conn &= ~0x03; mode_hfcpci()
1337 hfcpci_clear_fifo_rx(cs, fifo2); mode_hfcpci()
1338 hfcpci_clear_fifo_tx(cs, fifo2); mode_hfcpci()
1340 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; mode_hfcpci()
1341 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; mode_hfcpci()
1343 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; mode_hfcpci()
1344 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; mode_hfcpci()
1347 cs->hw.hfcpci.last_bfifo_cnt[1] = 0; mode_hfcpci()
1348 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; mode_hfcpci()
1349 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); mode_hfcpci()
1350 cs->hw.hfcpci.ctmt &= ~2; mode_hfcpci()
1351 cs->hw.hfcpci.conn &= ~0x18; mode_hfcpci()
1353 cs->hw.hfcpci.last_bfifo_cnt[0] = 0; mode_hfcpci()
1354 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; mode_hfcpci()
1355 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); mode_hfcpci()
1356 cs->hw.hfcpci.ctmt &= ~1; mode_hfcpci()
1357 cs->hw.hfcpci.conn &= ~0x03; mode_hfcpci()
1362 cs->hw.hfcpci.conn |= 0x10; mode_hfcpci()
1363 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; mode_hfcpci()
1364 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; mode_hfcpci()
1365 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; mode_hfcpci()
1366 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); mode_hfcpci()
1368 cs->hw.hfcpci.conn |= 0x02; mode_hfcpci()
1369 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; mode_hfcpci()
1370 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; mode_hfcpci()
1371 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; mode_hfcpci()
1372 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); mode_hfcpci()
1376 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); mode_hfcpci()
1377 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); mode_hfcpci()
1378 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); mode_hfcpci()
1379 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); mode_hfcpci()
1380 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); mode_hfcpci()
1381 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); mode_hfcpci()
1382 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); mode_hfcpci()
1397 spin_lock_irqsave(&bcs->cs->lock, flags); hfcpci_l2l1()
1403 bcs->cs->BC_Send_Data(bcs); hfcpci_l2l1()
1405 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcpci_l2l1()
1408 spin_lock_irqsave(&bcs->cs->lock, flags); hfcpci_l2l1()
1410 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcpci_l2l1()
1416 bcs->cs->BC_Send_Data(bcs); hfcpci_l2l1()
1417 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcpci_l2l1()
1427 spin_lock_irqsave(&bcs->cs->lock, flags); hfcpci_l2l1()
1430 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcpci_l2l1()
1437 spin_lock_irqsave(&bcs->cs->lock, flags); hfcpci_l2l1()
1441 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfcpci_l2l1()
1469 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs) open_hfcpcistate() argument
1505 struct IsdnCardState *cs = hfcpci_bh() local
1510 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { hfcpci_bh()
1511 if (!cs->hw.hfcpci.nt_mode) hfcpci_bh()
1512 switch (cs->dc.hfcpci.ph_state) { hfcpci_bh()
1514 l1_msg(cs, HW_RESET | INDICATION, NULL); hfcpci_bh()
1517 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); hfcpci_bh()
1520 l1_msg(cs, HW_RSYNC | INDICATION, NULL); hfcpci_bh()
1523 l1_msg(cs, HW_INFO2 | INDICATION, NULL); hfcpci_bh()
1526 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); hfcpci_bh()
1531 spin_lock_irqsave(&cs->lock, flags); hfcpci_bh()
1532 switch (cs->dc.hfcpci.ph_state) { hfcpci_bh()
1534 if (cs->hw.hfcpci.nt_timer < 0) { hfcpci_bh()
1535 cs->hw.hfcpci.nt_timer = 0; hfcpci_bh()
1536 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; hfcpci_bh()
1537 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); hfcpci_bh()
1539 if (Read_hfc(cs, HFCPCI_INT_S1)); hfcpci_bh()
1540 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE); hfcpci_bh()
1542 Write_hfc(cs, HFCPCI_STATES, 4); hfcpci_bh()
1543 cs->dc.hfcpci.ph_state = 4; hfcpci_bh()
1545 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER; hfcpci_bh()
1546 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); hfcpci_bh()
1547 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER; hfcpci_bh()
1548 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125; hfcpci_bh()
1549 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); hfcpci_bh()
1550 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); hfcpci_bh()
1551 cs->hw.hfcpci.nt_timer = NT_T1_COUNT; hfcpci_bh()
1552 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */ hfcpci_bh()
1558 cs->hw.hfcpci.nt_timer = 0; hfcpci_bh()
1559 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; hfcpci_bh()
1560 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); hfcpci_bh()
1565 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_bh()
1568 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) hfcpci_bh()
1569 DChannel_proc_rcv(cs); hfcpci_bh()
1570 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) hfcpci_bh()
1571 DChannel_proc_xmt(cs); hfcpci_bh()
1579 inithfcpci(struct IsdnCardState *cs) inithfcpci() argument
1581 cs->bcs[0].BC_SetStack = setstack_2b; inithfcpci()
1582 cs->bcs[1].BC_SetStack = setstack_2b; inithfcpci()
1583 cs->bcs[0].BC_Close = close_hfcpci; inithfcpci()
1584 cs->bcs[1].BC_Close = close_hfcpci; inithfcpci()
1585 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer; inithfcpci()
1586 cs->dbusytimer.data = (long) cs; inithfcpci()
1587 init_timer(&cs->dbusytimer); inithfcpci()
1588 mode_hfcpci(cs->bcs, 0, 0); inithfcpci()
1589 mode_hfcpci(cs->bcs + 1, 0, 1); inithfcpci()
1598 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg) hfcpci_card_msg() argument
1602 if (cs->debug & L1_DEB_ISAC) hfcpci_card_msg()
1603 debugl1(cs, "HFCPCI: card_msg %x", mt); hfcpci_card_msg()
1606 spin_lock_irqsave(&cs->lock, flags); hfcpci_card_msg()
1607 reset_hfcpci(cs); hfcpci_card_msg()
1608 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_card_msg()
1611 release_io_hfcpci(cs); hfcpci_card_msg()
1614 spin_lock_irqsave(&cs->lock, flags); hfcpci_card_msg()
1615 inithfcpci(cs); hfcpci_card_msg()
1616 reset_hfcpci(cs); hfcpci_card_msg()
1617 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_card_msg()
1620 spin_lock_irqsave(&cs->lock, flags); hfcpci_card_msg()
1621 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; hfcpci_card_msg()
1622 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); hfcpci_card_msg()
1624 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); hfcpci_card_msg()
1625 spin_unlock_irqrestore(&cs->lock, flags); hfcpci_card_msg()
1641 struct IsdnCardState *cs = card->cs; setup_hfcpci() local
1649 cs->hw.hfcpci.int_s1 = 0; setup_hfcpci()
1650 cs->dc.hfcpci.ph_state = 0; setup_hfcpci()
1651 cs->hw.hfcpci.fifo = 255; setup_hfcpci()
1652 if (cs->typ != ISDN_CTYPE_HFC_PCI) setup_hfcpci()
1690 cs->hw.hfcpci.dev = dev_hfcpci; setup_hfcpci()
1691 cs->irq = dev_hfcpci->irq; setup_hfcpci()
1692 if (!cs->irq) { setup_hfcpci()
1696 cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start; setup_hfcpci()
1699 if (!cs->hw.hfcpci.pci_io) { setup_hfcpci()
1705 cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev, setup_hfcpci()
1706 0x8000, &cs->hw.hfcpci.dma); setup_hfcpci()
1707 if (!cs->hw.hfcpci.fifos) { setup_hfcpci()
1711 if (cs->hw.hfcpci.dma & 0x7fff) { setup_hfcpci()
1714 (u_long)cs->hw.hfcpci.dma); setup_hfcpci()
1715 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, setup_hfcpci()
1716 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); setup_hfcpci()
1719 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma); setup_hfcpci()
1720 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256); setup_hfcpci()
1723 cs->hw.hfcpci.pci_io, setup_hfcpci()
1724 cs->hw.hfcpci.fifos, setup_hfcpci()
1725 (u_long)cs->hw.hfcpci.dma, setup_hfcpci()
1726 cs->irq, HZ); setup_hfcpci()
1728 spin_lock_irqsave(&cs->lock, flags); setup_hfcpci()
1730 pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */ setup_hfcpci()
1731 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */ setup_hfcpci()
1732 cs->hw.hfcpci.int_m1 = 0; setup_hfcpci()
1733 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); setup_hfcpci()
1734 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); setup_hfcpci()
1738 INIT_WORK(&cs->tqueue, hfcpci_bh); setup_hfcpci()
1739 cs->setstack_d = setstack_hfcpci; setup_hfcpci()
1740 cs->BC_Send_Data = &hfcpci_send_data; setup_hfcpci()
1741 cs->readisac = NULL; setup_hfcpci()
1742 cs->writeisac = NULL; setup_hfcpci()
1743 cs->readisacfifo = NULL; setup_hfcpci()
1744 cs->writeisacfifo = NULL; setup_hfcpci()
1745 cs->BC_Read_Reg = NULL; setup_hfcpci()
1746 cs->BC_Write_Reg = NULL; setup_hfcpci()
1747 cs->irq_func = &hfcpci_interrupt; setup_hfcpci()
1748 cs->irq_flags |= IRQF_SHARED; setup_hfcpci()
1749 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer; setup_hfcpci()
1750 cs->hw.hfcpci.timer.data = (long) cs; setup_hfcpci()
1751 init_timer(&cs->hw.hfcpci.timer); setup_hfcpci()
1752 cs->cardmsg = &hfcpci_card_msg; setup_hfcpci()
1753 cs->auxcmd = &hfcpci_auxcmd; setup_hfcpci()
1755 spin_unlock_irqrestore(&cs->lock, flags); setup_hfcpci()
|
| H A D | teles0.c | 98 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
100 return (readisac(cs->hw.teles0.membase, offset)); ReadISAC()
104 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
106 writeisac(cs->hw.teles0.membase, offset, value); WriteISAC()
110 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
112 read_fifo_isac(cs->hw.teles0.membase, data, size); ReadISACfifo()
116 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
118 write_fifo_isac(cs->hw.teles0.membase, data, size); WriteISACfifo()
122 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
124 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX()
128 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
130 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
137 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
138 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
139 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
140 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
147 struct IsdnCardState *cs = dev_id; teles0_interrupt() local
152 spin_lock_irqsave(&cs->lock, flags); teles0_interrupt()
153 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
156 hscx_int_main(cs, val); teles0_interrupt()
157 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
160 isac_interrupt(cs, val); teles0_interrupt()
162 val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); teles0_interrupt()
164 if (cs->debug & L1_DEB_HSCX) teles0_interrupt()
165 debugl1(cs, "HSCX IntStat after IntRoutine"); teles0_interrupt()
168 val = readisac(cs->hw.teles0.membase, ISAC_ISTA); teles0_interrupt()
170 if (cs->debug & L1_DEB_ISAC) teles0_interrupt()
171 debugl1(cs, "ISAC IntStat after IntRoutine"); teles0_interrupt()
174 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); teles0_interrupt()
175 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); teles0_interrupt()
176 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); teles0_interrupt()
177 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); teles0_interrupt()
178 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); teles0_interrupt()
179 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); teles0_interrupt()
180 spin_unlock_irqrestore(&cs->lock, flags); teles0_interrupt()
185 release_io_teles0(struct IsdnCardState *cs) release_io_teles0() argument
187 if (cs->hw.teles0.cfg_reg) release_io_teles0()
188 release_region(cs->hw.teles0.cfg_reg, 8); release_io_teles0()
189 iounmap(cs->hw.teles0.membase); release_io_teles0()
190 release_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE); release_io_teles0()
194 reset_teles0(struct IsdnCardState *cs) reset_teles0() argument
198 if (cs->hw.teles0.cfg_reg) { reset_teles0()
199 switch (cs->irq) { reset_teles0()
228 cfval |= ((cs->hw.teles0.phymem >> 9) & 0xF0); reset_teles0()
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval); reset_teles0()
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1); reset_teles0()
234 writeb(0, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
236 writeb(1, cs->hw.teles0.membase + 0x80); mb(); reset_teles0()
242 Teles_card_msg(struct IsdnCardState *cs, int mt, void *arg) Teles_card_msg() argument
248 spin_lock_irqsave(&cs->lock, flags); Teles_card_msg()
249 reset_teles0(cs); Teles_card_msg()
250 spin_unlock_irqrestore(&cs->lock, flags); Teles_card_msg()
253 release_io_teles0(cs); Teles_card_msg()
256 spin_lock_irqsave(&cs->lock, flags); Teles_card_msg()
257 inithscxisac(cs, 3); Teles_card_msg()
258 spin_unlock_irqrestore(&cs->lock, flags); Teles_card_msg()
269 struct IsdnCardState *cs = card->cs; setup_teles0() local
274 if ((cs->typ != ISDN_CTYPE_16_0) && (cs->typ != ISDN_CTYPE_8_0)) setup_teles0()
277 if (cs->typ == ISDN_CTYPE_16_0) setup_teles0()
278 cs->hw.teles0.cfg_reg = card->para[2]; setup_teles0()
280 cs->hw.teles0.cfg_reg = 0; setup_teles0()
288 cs->irq = card->para[0]; setup_teles0()
289 if (cs->hw.teles0.cfg_reg) { setup_teles0()
290 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) { setup_teles0()
294 cs->hw.teles0.cfg_reg, setup_teles0()
295 cs->hw.teles0.cfg_reg + 8); setup_teles0()
299 if (cs->hw.teles0.cfg_reg) { setup_teles0()
300 if ((val = bytein(cs->hw.teles0.cfg_reg + 0)) != 0x51) { setup_teles0()
302 cs->hw.teles0.cfg_reg + 0, val); setup_teles0()
303 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
306 if ((val = bytein(cs->hw.teles0.cfg_reg + 1)) != 0x93) { setup_teles0()
308 cs->hw.teles0.cfg_reg + 1, val); setup_teles0()
309 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
312 val = bytein(cs->hw.teles0.cfg_reg + 2); /* 0x1e=without AB setup_teles0()
318 cs->hw.teles0.cfg_reg + 2, val); setup_teles0()
319 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
324 test_and_set_bit(HW_IOM1, &cs->HW_Flags); setup_teles0()
325 cs->hw.teles0.phymem = card->para[1]; setup_teles0()
326 if (!request_mem_region(cs->hw.teles0.phymem, TELES_IOMEM_SIZE, "teles iomem")) { setup_teles0()
330 cs->hw.teles0.phymem, setup_teles0()
331 cs->hw.teles0.phymem + TELES_IOMEM_SIZE); setup_teles0()
332 if (cs->hw.teles0.cfg_reg) setup_teles0()
333 release_region(cs->hw.teles0.cfg_reg, 8); setup_teles0()
336 cs->hw.teles0.membase = ioremap(cs->hw.teles0.phymem, TELES_IOMEM_SIZE); setup_teles0()
339 CardType[cs->typ], cs->irq, setup_teles0()
340 cs->hw.teles0.membase, cs->hw.teles0.cfg_reg); setup_teles0()
341 if (reset_teles0(cs)) { setup_teles0()
343 release_io_teles0(cs); setup_teles0()
346 setup_isac(cs); setup_teles0()
347 cs->readisac = &ReadISAC; setup_teles0()
348 cs->writeisac = &WriteISAC; setup_teles0()
349 cs->readisacfifo = &ReadISACfifo; setup_teles0()
350 cs->writeisacfifo = &WriteISACfifo; setup_teles0()
351 cs->BC_Read_Reg = &ReadHSCX; setup_teles0()
352 cs->BC_Write_Reg = &WriteHSCX; setup_teles0()
353 cs->BC_Send_Data = &hscx_fill_fifo; setup_teles0()
354 cs->cardmsg = &Teles_card_msg; setup_teles0()
355 cs->irq_func = &teles0_interrupt; setup_teles0()
356 ISACVersion(cs, "Teles0:"); setup_teles0()
357 if (HscxVersion(cs, "Teles0:")) { setup_teles0()
360 release_io_teles0(cs); setup_teles0()
|
| H A D | bkm_a4t.c | 74 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
76 return (readreg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset)); ReadISAC()
80 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
82 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value); WriteISAC()
86 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
88 readfifo(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, 0, data, size); ReadISACfifo()
92 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
94 writefifo(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, 0, data, size); WriteISACfifo()
98 ReadJADE(struct IsdnCardState *cs, int jade, u_char offset) ReadJADE() argument
100 return (readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)))); ReadJADE()
104 WriteJADE(struct IsdnCardState *cs, int jade, u_char offset, u_char value) WriteJADE() argument
106 writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)), value); WriteJADE()
113 #define READJADE(cs, nr, reg) readreg(cs->hw.ax.jade_ale, \
114 cs->hw.ax.jade_adr, reg + (nr == -1 ? 0 : (nr ? 0xC0 : 0x80)))
115 #define WRITEJADE(cs, nr, reg, data) writereg(cs->hw.ax.jade_ale, \
116 cs->hw.ax.jade_adr, reg + (nr == -1 ? 0 : (nr ? 0xC0 : 0x80)), data)
118 #define READJADEFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.jade_ale, \
119 cs->hw.ax.jade_adr, (nr == -1 ? 0 : (nr ? 0xC0 : 0x80)), ptr, cnt)
120 #define WRITEJADEFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.jade_ale, \
121 cs->hw.ax.jade_adr, (nr == -1 ? 0 : (nr ? 0xC0 : 0x80)), ptr, cnt)
128 struct IsdnCardState *cs = dev_id; bkm_interrupt() local
133 spin_lock_irqsave(&cs->lock, flags); bkm_interrupt()
134 pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base); bkm_interrupt()
143 val = readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, jade_HDLC_ISR + 0x80); bkm_interrupt()
145 jade_int_main(cs, val, 0); bkm_interrupt()
148 val = readreg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, jade_HDLC_ISR + 0xC0); bkm_interrupt()
150 jade_int_main(cs, val, 1); bkm_interrupt()
153 val = readreg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, ISAC_ISTA); bkm_interrupt()
155 isac_interrupt(cs, val); bkm_interrupt()
159 spin_unlock_irqrestore(&cs->lock, flags); bkm_interrupt()
162 spin_unlock_irqrestore(&cs->lock, flags); bkm_interrupt()
168 release_io_bkm(struct IsdnCardState *cs) release_io_bkm() argument
170 if (cs->hw.ax.base) { release_io_bkm()
171 iounmap((void *) cs->hw.ax.base); release_io_bkm()
172 cs->hw.ax.base = 0; release_io_bkm()
177 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable) enable_bkm_int() argument
179 if (cs->typ == ISDN_CTYPE_BKM_A4T) { enable_bkm_int()
180 I20_REGISTER_FILE *pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base); enable_bkm_int()
190 reset_bkm(struct IsdnCardState *cs) reset_bkm() argument
192 if (cs->typ == ISDN_CTYPE_BKM_A4T) { reset_bkm()
193 I20_REGISTER_FILE *pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base); reset_bkm()
220 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg) BKM_card_msg() argument
227 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
228 enable_bkm_int(cs, 0); BKM_card_msg()
229 reset_bkm(cs); BKM_card_msg()
230 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
234 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
235 enable_bkm_int(cs, 0); BKM_card_msg()
236 reset_bkm(cs); BKM_card_msg()
237 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
238 release_io_bkm(cs); BKM_card_msg()
241 spin_lock_irqsave(&cs->lock, flags); BKM_card_msg()
242 clear_pending_isac_ints(cs); BKM_card_msg()
243 clear_pending_jade_ints(cs); BKM_card_msg()
244 initisac(cs); BKM_card_msg()
245 initjade(cs); BKM_card_msg()
247 enable_bkm_int(cs, 1); BKM_card_msg()
248 spin_unlock_irqrestore(&cs->lock, flags); BKM_card_msg()
256 static int a4t_pci_probe(struct pci_dev *dev_a4t, struct IsdnCardState *cs, a4t_pci_probe() argument
269 cs->irq = dev_a4t->irq; a4t_pci_probe()
276 static int a4t_cs_init(struct IsdnCard *card, struct IsdnCardState *cs, a4t_cs_init() argument
281 if (!cs->irq) { /* IRQ range check ?? */ a4t_cs_init()
285 cs->hw.ax.base = (long) ioremap(pci_memaddr, 4096); a4t_cs_init()
287 pI20_Regs = (I20_REGISTER_FILE *) (cs->hw.ax.base); a4t_cs_init()
291 cs->hw.ax.base, cs->hw.ax.base + 4096); a4t_cs_init()
292 iounmap((void *) cs->hw.ax.base); a4t_cs_init()
293 cs->hw.ax.base = 0; a4t_cs_init()
296 cs->hw.ax.isac_adr = cs->hw.ax.base + PO_OFFSET; a4t_cs_init()
297 cs->hw.ax.jade_adr = cs->hw.ax.base + PO_OFFSET; a4t_cs_init()
298 cs->hw.ax.isac_ale = GCS_1; a4t_cs_init()
299 cs->hw.ax.jade_ale = GCS_3; a4t_cs_init()
303 cs->hw.ax.base, cs->irq); a4t_cs_init()
305 setup_isac(cs); a4t_cs_init()
306 cs->readisac = &ReadISAC; a4t_cs_init()
307 cs->writeisac = &WriteISAC; a4t_cs_init()
308 cs->readisacfifo = &ReadISACfifo; a4t_cs_init()
309 cs->writeisacfifo = &WriteISACfifo; a4t_cs_init()
310 cs->BC_Read_Reg = &ReadJADE; a4t_cs_init()
311 cs->BC_Write_Reg = &WriteJADE; a4t_cs_init()
312 cs->BC_Send_Data = &jade_fill_fifo; a4t_cs_init()
313 cs->cardmsg = &BKM_card_msg; a4t_cs_init()
314 cs->irq_func = &bkm_interrupt; a4t_cs_init()
315 cs->irq_flags |= IRQF_SHARED; a4t_cs_init()
316 ISACVersion(cs, "Telekom A4T:"); a4t_cs_init()
318 JadeVersion(cs, "Telekom A4T:"); a4t_cs_init()
327 struct IsdnCardState *cs = card->cs; setup_bkm_a4t() local
334 if (cs->typ == ISDN_CTYPE_BKM_A4T) { setup_bkm_a4t()
335 cs->subtyp = BKM_A4T; setup_bkm_a4t()
341 ret = a4t_pci_probe(dev_a4t, cs, &found, &pci_memaddr); setup_bkm_a4t()
357 return a4t_cs_init(card, cs, pci_memaddr); setup_bkm_a4t()
|
| H A D | elsa_ser.c | 48 static inline unsigned int serial_in(struct IsdnCardState *cs, int offset) serial_in() argument
51 u_int val = inb(cs->hw.elsa.base + 8 + offset); serial_in()
52 debugl1(cs, "in %s %02x", ModemIn[offset], val); serial_in()
55 return inb(cs->hw.elsa.base + 8 + offset); serial_in()
59 static inline unsigned int serial_inp(struct IsdnCardState *cs, int offset) serial_inp() argument
63 u_int val = inb(cs->hw.elsa.base + 8 + offset); serial_inp()
64 debugl1(cs, "inp %s %02x", ModemIn[offset], val); serial_inp()
66 u_int val = inb_p(cs->hw.elsa.base + 8 + offset); serial_inp()
67 debugl1(cs, "inP %s %02x", ModemIn[offset], val); serial_inp()
72 return inb(cs->hw.elsa.base + 8 + offset); serial_inp()
74 return inb_p(cs->hw.elsa.base + 8 + offset); serial_inp()
79 static inline void serial_out(struct IsdnCardState *cs, int offset, int value) serial_out() argument
82 debugl1(cs, "out %s %02x", ModemOut[offset], value); serial_out()
84 outb(value, cs->hw.elsa.base + 8 + offset); serial_out()
87 static inline void serial_outp(struct IsdnCardState *cs, int offset, serial_outp() argument
92 debugl1(cs, "outp %s %02x", ModemOut[offset], value); serial_outp()
94 debugl1(cs, "outP %s %02x", ModemOut[offset], value); serial_outp()
98 outb(value, cs->hw.elsa.base + 8 + offset); serial_outp()
100 outb_p(value, cs->hw.elsa.base + 8 + offset); serial_outp()
108 static void change_speed(struct IsdnCardState *cs, int baud) change_speed() argument
128 serial_outp(cs, UART_FCR, fcr); change_speed()
130 cs->hw.elsa.IER &= ~UART_IER_MSI; change_speed()
131 cs->hw.elsa.IER |= UART_IER_MSI; change_speed()
132 serial_outp(cs, UART_IER, cs->hw.elsa.IER); change_speed()
134 debugl1(cs, "modem quot=0x%x", quot); change_speed()
135 serial_outp(cs, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ change_speed()
136 serial_outp(cs, UART_DLL, quot & 0xff); /* LS of divisor */ change_speed()
137 serial_outp(cs, UART_DLM, quot >> 8); /* MS of divisor */ change_speed()
138 serial_outp(cs, UART_LCR, cval); /* reset DLAB */ change_speed()
139 serial_inp(cs, UART_RX); change_speed()
142 static int mstartup(struct IsdnCardState *cs) mstartup() argument
150 serial_outp(cs, UART_FCR, (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)); mstartup()
157 if (serial_inp(cs, UART_LSR) == 0xff) { mstartup()
165 (void) serial_inp(cs, UART_RX); mstartup()
166 (void) serial_inp(cs, UART_IIR); mstartup()
167 (void) serial_inp(cs, UART_MSR); mstartup()
172 serial_outp(cs, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */ mstartup()
174 cs->hw.elsa.MCR = 0; mstartup()
175 cs->hw.elsa.MCR = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; mstartup()
176 serial_outp(cs, UART_MCR, cs->hw.elsa.MCR); mstartup()
181 cs->hw.elsa.IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; mstartup()
182 serial_outp(cs, UART_IER, cs->hw.elsa.IER); /* enable interrupts */ mstartup()
187 (void)serial_inp(cs, UART_LSR); mstartup()
188 (void)serial_inp(cs, UART_RX); mstartup()
189 (void)serial_inp(cs, UART_IIR); mstartup()
190 (void)serial_inp(cs, UART_MSR); mstartup()
192 cs->hw.elsa.transcnt = cs->hw.elsa.transp = 0; mstartup()
193 cs->hw.elsa.rcvcnt = cs->hw.elsa.rcvp = 0; mstartup()
198 change_speed(cs, BASE_BAUD); mstartup()
199 cs->hw.elsa.MFlag = 1; mstartup()
208 static void mshutdown(struct IsdnCardState *cs) mshutdown() argument
220 cs->hw.elsa.IER = 0; mshutdown()
221 serial_outp(cs, UART_IER, 0x00); /* disable all intrs */ mshutdown()
222 cs->hw.elsa.MCR &= ~UART_MCR_OUT2; mshutdown()
225 serial_outp(cs, UART_LCR, serial_inp(cs, UART_LCR) & ~UART_LCR_SBC); mshutdown()
227 cs->hw.elsa.MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); mshutdown()
228 serial_outp(cs, UART_MCR, cs->hw.elsa.MCR); mshutdown()
231 serial_outp(cs, UART_FCR, (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)); mshutdown()
232 serial_inp(cs, UART_RX); /* read data port to reset things */ mshutdown()
242 struct IsdnCardState *cs = bcs->cs; write_modem() local
250 if (len > MAX_MODEM_BUF - cs->hw.elsa.transcnt) write_modem()
251 len = MAX_MODEM_BUF - cs->hw.elsa.transcnt; write_modem()
252 fp = cs->hw.elsa.transcnt + cs->hw.elsa.transp; write_modem()
258 cs->hw.elsa.transbuf + fp, count); write_modem()
260 cs->hw.elsa.transcnt += count; write_modem()
266 cs->hw.elsa.transbuf + fp, count); write_modem()
268 cs->hw.elsa.transcnt += count; write_modem()
271 if (cs->hw.elsa.transcnt && write_modem()
272 !(cs->hw.elsa.IER & UART_IER_THRI)) { write_modem()
273 cs->hw.elsa.IER |= UART_IER_THRI; write_modem()
274 serial_outp(cs, UART_IER, cs->hw.elsa.IER); write_modem()
309 static inline void receive_chars(struct IsdnCardState *cs, receive_chars() argument
316 ch = serial_in(cs, UART_RX); receive_chars()
317 if (cs->hw.elsa.rcvcnt >= MAX_MODEM_BUF) receive_chars()
319 cs->hw.elsa.rcvbuf[cs->hw.elsa.rcvcnt++] = ch; receive_chars()
330 *status = serial_inp(cs, UART_LSR); receive_chars()
332 if (cs->hw.elsa.MFlag == 2) { receive_chars()
333 if (!(skb = dev_alloc_skb(cs->hw.elsa.rcvcnt))) receive_chars()
336 memcpy(skb_put(skb, cs->hw.elsa.rcvcnt), cs->hw.elsa.rcvbuf, receive_chars()
337 cs->hw.elsa.rcvcnt); receive_chars()
338 skb_queue_tail(&cs->hw.elsa.bcs->rqueue, skb); receive_chars()
340 schedule_event(cs->hw.elsa.bcs, B_RCVBUFREADY); receive_chars()
345 t += sprintf(t, "modem read cnt %d", cs->hw.elsa.rcvcnt); receive_chars()
346 QuickHex(t, cs->hw.elsa.rcvbuf, cs->hw.elsa.rcvcnt); receive_chars()
347 debugl1(cs, "%s", tmp); receive_chars()
349 cs->hw.elsa.rcvcnt = 0; receive_chars()
352 static inline void transmit_chars(struct IsdnCardState *cs, int *intr_done) transmit_chars() argument
356 debugl1(cs, "transmit_chars: p(%x) cnt(%x)", cs->hw.elsa.transp, transmit_chars()
357 cs->hw.elsa.transcnt); transmit_chars()
359 if (cs->hw.elsa.transcnt <= 0) { transmit_chars()
360 cs->hw.elsa.IER &= ~UART_IER_THRI; transmit_chars()
361 serial_out(cs, UART_IER, cs->hw.elsa.IER); transmit_chars()
366 serial_outp(cs, UART_TX, cs->hw.elsa.transbuf[cs->hw.elsa.transp++]); transmit_chars()
367 if (cs->hw.elsa.transp >= MAX_MODEM_BUF) transmit_chars()
368 cs->hw.elsa.transp = 0; transmit_chars()
369 if (--cs->hw.elsa.transcnt <= 0) transmit_chars()
372 if ((cs->hw.elsa.transcnt < WAKEUP_CHARS) && (cs->hw.elsa.MFlag == 2)) transmit_chars()
373 modem_fill(cs->hw.elsa.bcs); transmit_chars()
380 if (cs->hw.elsa.transcnt <= 0) { transmit_chars()
381 cs->hw.elsa.IER &= ~UART_IER_THRI; transmit_chars()
382 serial_outp(cs, UART_IER, cs->hw.elsa.IER); transmit_chars()
387 static void rs_interrupt_elsa(struct IsdnCardState *cs) rs_interrupt_elsa() argument
393 printk(KERN_DEBUG "rs_interrupt_single(%d)...", cs->irq); rs_interrupt_elsa()
397 status = serial_inp(cs, UART_LSR); rs_interrupt_elsa()
398 debugl1(cs, "rs LSR %02x", status); rs_interrupt_elsa()
403 receive_chars(cs, &status); rs_interrupt_elsa()
405 transmit_chars(cs, NULL); rs_interrupt_elsa()
410 iir = serial_inp(cs, UART_IIR); rs_interrupt_elsa()
411 debugl1(cs, "rs IIR %02x", iir); rs_interrupt_elsa()
413 msr = serial_inp(cs, UART_MSR); rs_interrupt_elsa()
414 debugl1(cs, "rs MSR %02x", msr); rs_interrupt_elsa()
422 extern int open_hscxstate(struct IsdnCardState *cs, struct BCState *bcs);
447 modem_write_cmd(struct IsdnCardState *cs, u_char *buf, int len) { modem_write_cmd() argument
453 if (len > (MAX_MODEM_BUF - cs->hw.elsa.transcnt)) { modem_write_cmd()
456 fp = cs->hw.elsa.transcnt + cs->hw.elsa.transp; modem_write_cmd()
461 memcpy(cs->hw.elsa.transbuf + fp, msg, count); modem_write_cmd()
462 cs->hw.elsa.transcnt += count; modem_write_cmd()
467 memcpy(cs->hw.elsa.transbuf + fp, msg, count); modem_write_cmd()
468 cs->hw.elsa.transcnt += count; modem_write_cmd()
469 if (cs->hw.elsa.transcnt && modem_write_cmd()
470 !(cs->hw.elsa.IER & UART_IER_THRI)) { modem_write_cmd()
471 cs->hw.elsa.IER |= UART_IER_THRI; modem_write_cmd()
472 serial_outp(cs, UART_IER, cs->hw.elsa.IER); modem_write_cmd()
477 modem_set_init(struct IsdnCardState *cs) { modem_set_init() argument
481 modem_write_cmd(cs, MInit_1, strlen(MInit_1)); modem_set_init()
483 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
485 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
487 modem_write_cmd(cs, MInit_2, strlen(MInit_2)); modem_set_init()
489 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
491 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
493 modem_write_cmd(cs, MInit_3, strlen(MInit_3)); modem_set_init()
495 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
497 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
499 modem_write_cmd(cs, MInit_4, strlen(MInit_4)); modem_set_init()
501 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
503 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
505 modem_write_cmd(cs, MInit_5, strlen(MInit_5)); modem_set_init()
507 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
509 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
511 modem_write_cmd(cs, MInit_6, strlen(MInit_6)); modem_set_init()
513 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
515 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
517 modem_write_cmd(cs, MInit_7, strlen(MInit_7)); modem_set_init()
519 while (timeout-- && cs->hw.elsa.transcnt) modem_set_init()
521 debugl1(cs, "msi tout=%d", timeout); modem_set_init()
526 modem_set_dial(struct IsdnCardState *cs, int outgoing) { modem_set_dial() argument
530 modem_write_cmd(cs, MInit_speed28800, strlen(MInit_speed28800)); modem_set_dial()
532 while (timeout-- && cs->hw.elsa.transcnt) modem_set_dial()
534 debugl1(cs, "msi tout=%d", timeout); modem_set_dial()
537 modem_write_cmd(cs, MInit_dialout, strlen(MInit_dialout)); modem_set_dial()
539 modem_write_cmd(cs, MInit_dialin, strlen(MInit_dialin)); modem_set_dial()
541 while (timeout-- && cs->hw.elsa.transcnt) modem_set_dial()
543 debugl1(cs, "msi tout=%d", timeout); modem_set_dial()
555 spin_lock_irqsave(&bcs->cs->lock, flags); modem_l2l1()
564 spin_unlock_irqrestore(&bcs->cs->lock, flags); modem_l2l1()
568 set_arcofi(bcs->cs, st->l1.bc); modem_l2l1()
569 mstartup(bcs->cs); modem_l2l1()
570 modem_set_dial(bcs->cs, test_bit(FLG_ORIG, &st->l2.flag)); modem_l2l1()
571 bcs->cs->hw.elsa.MFlag = 2; modem_l2l1()
574 bcs->cs->dc.isac.arcofi_bc = st->l1.bc; modem_l2l1()
575 arcofi_fsm(bcs->cs, ARCOFI_START, &ARCOFI_XOP_0); modem_l2l1()
576 wait_event_interruptible(bcs->cs->dc.isac.arcofi_wait, modem_l2l1()
577 bcs->cs->dc.isac.arcofi_state == ARCOFI_NOP); modem_l2l1()
578 bcs->cs->hw.elsa.MFlag = 1; modem_l2l1()
599 bcs->hw.hscx.rcvbuf = bcs->cs->hw.elsa.rcvbuf; setstack_elsa()
608 bcs->cs->hw.elsa.bcs = bcs; setstack_elsa()
620 init_modem(struct IsdnCardState *cs) { init_modem() argument
622 cs->bcs[0].BC_SetStack = setstack_elsa; init_modem()
623 cs->bcs[1].BC_SetStack = setstack_elsa; init_modem()
624 cs->bcs[0].BC_Close = close_elsastate; init_modem()
625 cs->bcs[1].BC_Close = close_elsastate; init_modem()
626 if (!(cs->hw.elsa.rcvbuf = kmalloc(MAX_MODEM_BUF, init_modem()
632 if (!(cs->hw.elsa.transbuf = kmalloc(MAX_MODEM_BUF, init_modem()
636 kfree(cs->hw.elsa.rcvbuf); init_modem()
637 cs->hw.elsa.rcvbuf = NULL; init_modem()
640 if (mstartup(cs)) { init_modem()
643 modem_set_init(cs); init_modem()
647 release_modem(struct IsdnCardState *cs) { release_modem() argument
649 cs->hw.elsa.MFlag = 0; release_modem()
650 if (cs->hw.elsa.transbuf) { release_modem()
651 if (cs->hw.elsa.rcvbuf) { release_modem()
652 mshutdown(cs); release_modem()
653 kfree(cs->hw.elsa.rcvbuf); release_modem()
654 cs->hw.elsa.rcvbuf = NULL; release_modem()
656 kfree(cs->hw.elsa.transbuf); release_modem()
657 cs->hw.elsa.transbuf = NULL; release_modem()
|
| H A D | hfc_2bs0.c | 22 WaitForBusy(struct IsdnCardState *cs) WaitForBusy() argument
27 while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) { WaitForBusy()
28 val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 | WaitForBusy()
29 (cs->hw.hfc.cip & 3)); WaitForBusy()
41 WaitNoBusy(struct IsdnCardState *cs) WaitNoBusy() argument
45 while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) { WaitNoBusy()
62 return (bcs->cs->hw.hfc.fifosize); GetFreeFifoBytes()
65 s += bcs->cs->hw.hfc.fifosize; GetFreeFifoBytes()
66 s = bcs->cs->hw.hfc.fifosize - s; GetFreeFifoBytes()
75 WaitNoBusy(bcs->cs); ReadZReg()
76 val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH); ReadZReg()
77 WaitNoBusy(bcs->cs); ReadZReg()
78 val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW); ReadZReg()
85 struct IsdnCardState *cs = bcs->cs; hfc_clear_fifo() local
90 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hfc_clear_fifo()
91 debugl1(cs, "hfc_clear_fifo"); hfc_clear_fifo()
93 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) { hfc_clear_fifo()
94 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); hfc_clear_fifo()
95 WaitForBusy(cs); hfc_clear_fifo()
97 WaitNoBusy(cs); hfc_clear_fifo()
98 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_clear_fifo()
100 WaitNoBusy(cs); hfc_clear_fifo()
101 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_clear_fifo()
106 if (cs->debug & L1_DEB_HSCX) hfc_clear_fifo()
107 debugl1(cs, "hfc clear %d f1(%d) f2(%d)", hfc_clear_fifo()
111 rcnt += cs->hw.hfc.fifosize; hfc_clear_fifo()
114 if (cs->debug & L1_DEB_HSCX) hfc_clear_fifo()
115 debugl1(cs, "hfc clear %d z1(%x) z2(%x) cnt(%d)", hfc_clear_fifo()
119 while ((idx < rcnt) && WaitNoBusy(cs)) { hfc_clear_fifo()
120 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip); hfc_clear_fifo()
124 WaitNoBusy(cs); hfc_clear_fifo()
125 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC | hfc_clear_fifo()
127 WaitForBusy(cs); hfc_clear_fifo()
130 WaitNoBusy(cs); hfc_clear_fifo()
131 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_clear_fifo()
133 WaitNoBusy(cs); hfc_clear_fifo()
134 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_clear_fifo()
148 struct IsdnCardState *cs = bcs->cs; hfc_empty_fifo() local
153 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hfc_empty_fifo()
154 debugl1(cs, "hfc_empty_fifo"); hfc_empty_fifo()
157 if (cs->debug & L1_DEB_WARN) hfc_empty_fifo()
158 debugl1(cs, "hfc_empty_fifo: incoming packet too large"); hfc_empty_fifo()
160 while ((idx++ < count) && WaitNoBusy(cs)) hfc_empty_fifo()
161 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip); hfc_empty_fifo()
162 WaitNoBusy(cs); hfc_empty_fifo()
163 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC | hfc_empty_fifo()
165 WaitForBusy(cs); hfc_empty_fifo()
169 if (cs->debug & L1_DEB_WARN) hfc_empty_fifo()
170 debugl1(cs, "hfc_empty_fifo: incoming packet too small"); hfc_empty_fifo()
172 while ((idx++ < count) && WaitNoBusy(cs)) hfc_empty_fifo()
173 cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip); hfc_empty_fifo()
174 WaitNoBusy(cs); hfc_empty_fifo()
175 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC | hfc_empty_fifo()
177 WaitForBusy(cs); hfc_empty_fifo()
193 while ((idx < count) && WaitNoBusy(cs)) { hfc_empty_fifo()
194 *ptr++ = cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip); hfc_empty_fifo()
198 debugl1(cs, "RFIFO BUSY error"); hfc_empty_fifo()
202 WaitNoBusy(cs); hfc_empty_fifo()
203 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC | hfc_empty_fifo()
205 WaitForBusy(cs); hfc_empty_fifo()
210 WaitNoBusy(cs); hfc_empty_fifo()
211 chksum = (cs->BC_Read_Reg(cs, HFC_DATA, cip) << 8); hfc_empty_fifo()
212 WaitNoBusy(cs); hfc_empty_fifo()
213 chksum += cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_empty_fifo()
214 WaitNoBusy(cs); hfc_empty_fifo()
215 stat = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_empty_fifo()
216 if (cs->debug & L1_DEB_HSCX) hfc_empty_fifo()
217 debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x", hfc_empty_fifo()
220 debugl1(cs, "FIFO CRC error"); hfc_empty_fifo()
227 WaitNoBusy(cs); hfc_empty_fifo()
228 stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC | hfc_empty_fifo()
230 WaitForBusy(cs); hfc_empty_fifo()
239 struct IsdnCardState *cs = bcs->cs; hfc_fill_fifo() local
251 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) { hfc_fill_fifo()
252 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); hfc_fill_fifo()
253 WaitForBusy(cs); hfc_fill_fifo()
255 WaitNoBusy(cs); hfc_fill_fifo()
257 bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_fill_fifo()
259 WaitNoBusy(cs); hfc_fill_fifo()
260 bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip); hfc_fill_fifo()
262 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
263 debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)", hfc_fill_fifo()
270 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
271 debugl1(cs, "hfc_fill_fifo more as 30 frames"); hfc_fill_fifo()
277 WaitForBusy(cs); hfc_fill_fifo()
282 count += cs->hw.hfc.fifosize; hfc_fill_fifo()
284 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
285 debugl1(cs, "hfc_fill_fifo %d count(%u/%d)", hfc_fill_fifo()
289 if (cs->debug & L1_DEB_HSCX) hfc_fill_fifo()
290 debugl1(cs, "hfc_fill_fifo no fifo mem"); hfc_fill_fifo()
295 while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs)) hfc_fill_fifo()
296 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]); hfc_fill_fifo()
298 debugl1(cs, "FIFO Send BUSY error"); hfc_fill_fifo()
308 WaitForBusy(cs); hfc_fill_fifo()
309 WaitNoBusy(cs); hfc_fill_fifo()
310 cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel)); hfc_fill_fifo()
328 struct IsdnCardState *cs = bcs->cs; main_irq_hfc() local
337 if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) { main_irq_hfc()
338 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); main_irq_hfc()
339 WaitForBusy(cs); main_irq_hfc()
341 WaitNoBusy(cs); main_irq_hfc()
344 f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip); main_irq_hfc()
346 WaitNoBusy(cs); main_irq_hfc()
347 f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip); main_irq_hfc()
349 if (cs->debug & L1_DEB_HSCX) main_irq_hfc()
350 debugl1(cs, "hfc rec %d f1(%d) f2(%d)", main_irq_hfc()
356 WaitForBusy(cs); main_irq_hfc()
361 rcnt += cs->hw.hfc.fifosize; main_irq_hfc()
364 if (cs->debug & L1_DEB_HSCX) main_irq_hfc()
365 debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)", main_irq_hfc()
401 struct IsdnCardState *cs = bcs->cs; mode_hfc() local
403 if (cs->debug & L1_DEB_HSCX) mode_hfc()
404 debugl1(cs, "HFC 2BS0 mode %d bchan %d/%d", mode_hfc()
412 cs->hw.hfc.ctmt &= ~1; mode_hfc()
413 cs->hw.hfc.isac_spcr &= ~0x03; mode_hfc()
416 cs->hw.hfc.ctmt &= ~2; mode_hfc()
417 cs->hw.hfc.isac_spcr &= ~0x0c; mode_hfc()
421 cs->hw.hfc.ctmt &= ~(1 << bc); /* set HDLC mode */ mode_hfc()
422 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); mode_hfc()
425 cs->hw.hfc.ctmt |= 1; mode_hfc()
426 cs->hw.hfc.isac_spcr &= ~0x03; mode_hfc()
427 cs->hw.hfc.isac_spcr |= 0x02; mode_hfc()
429 cs->hw.hfc.ctmt |= 2; mode_hfc()
430 cs->hw.hfc.isac_spcr &= ~0x0c; mode_hfc()
431 cs->hw.hfc.isac_spcr |= 0x08; mode_hfc()
436 cs->hw.hfc.ctmt &= ~1; mode_hfc()
437 cs->hw.hfc.isac_spcr &= ~0x03; mode_hfc()
438 cs->hw.hfc.isac_spcr |= 0x02; mode_hfc()
440 cs->hw.hfc.ctmt &= ~2; mode_hfc()
441 cs->hw.hfc.isac_spcr &= ~0x0c; mode_hfc()
442 cs->hw.hfc.isac_spcr |= 0x08; mode_hfc()
446 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); mode_hfc()
447 cs->writeisac(cs, ISAC_SPCR, cs->hw.hfc.isac_spcr); mode_hfc()
461 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
467 bcs->cs->BC_Send_Data(bcs); hfc_l2l1()
469 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
472 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
478 bcs->cs->BC_Send_Data(bcs); hfc_l2l1()
480 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
490 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
493 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
500 spin_lock_irqsave(&bcs->cs->lock, flags); hfc_l2l1()
504 spin_unlock_irqrestore(&bcs->cs->lock, flags); hfc_l2l1()
528 open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs) open_hfcstate() argument
570 inithfc(struct IsdnCardState *cs) inithfc() argument
572 init_send(&cs->bcs[0]); inithfc()
573 init_send(&cs->bcs[1]); inithfc()
574 cs->BC_Send_Data = &hfc_fill_fifo; inithfc()
575 cs->bcs[0].BC_SetStack = setstack_hfc; inithfc()
576 cs->bcs[1].BC_SetStack = setstack_hfc; inithfc()
577 cs->bcs[0].BC_Close = close_hfcstate; inithfc()
578 cs->bcs[1].BC_Close = close_hfcstate; inithfc()
579 mode_hfc(cs->bcs, 0, 0); inithfc()
580 mode_hfc(cs->bcs + 1, 0, 0); inithfc()
584 releasehfc(struct IsdnCardState *cs) releasehfc() argument
586 kfree(cs->bcs[0].hw.hfc.send); releasehfc()
587 cs->bcs[0].hw.hfc.send = NULL; releasehfc()
588 kfree(cs->bcs[1].hw.hfc.send); releasehfc()
589 cs->bcs[1].hw.hfc.send = NULL; releasehfc()
|
| H A D | enternow_pci.c | 95 /* cs->readisac, macro rByteAMD */
97 ReadByteAmd7930(struct IsdnCardState *cs, unsigned char offset) ReadByteAmd7930() argument
101 return (inb(cs->hw.njet.isac + 4 * offset)); ReadByteAmd7930()
105 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); ReadByteAmd7930()
106 return (inb(cs->hw.njet.isac + 4 * AMD_DR)); ReadByteAmd7930()
110 /* cs->writeisac, macro wByteAMD */
112 WriteByteAmd7930(struct IsdnCardState *cs, unsigned char offset, unsigned char value) WriteByteAmd7930() argument
116 outb(value, cs->hw.njet.isac + 4 * offset); WriteByteAmd7930()
120 outb(offset, cs->hw.njet.isac + 4 * AMD_CR); WriteByteAmd7930()
121 outb(value, cs->hw.njet.isac + 4 * AMD_DR); WriteByteAmd7930()
127 enpci_setIrqMask(struct IsdnCardState *cs, unsigned char val) { enpci_setIrqMask() argument
129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1); enpci_setIrqMask()
131 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); enpci_setIrqMask()
135 static unsigned char dummyrr(struct IsdnCardState *cs, int chan, unsigned char off) dummyrr() argument
140 static void dummywr(struct IsdnCardState *cs, int chan, unsigned char off, unsigned char value) dummywr() argument
150 reset_enpci(struct IsdnCardState *cs) reset_enpci() argument
152 if (cs->debug & L1_DEB_ISAC) reset_enpci()
153 debugl1(cs, "enter:now PCI: reset"); reset_enpci()
156 cs->hw.njet.ctrl_reg = 0x07; reset_enpci()
157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); reset_enpci()
160 cs->hw.njet.ctrl_reg = 0x30; reset_enpci()
161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); reset_enpci()
164 cs->hw.njet.auxd = 0; // LED-status reset_enpci()
165 cs->hw.njet.dmactrl = 0; reset_enpci()
166 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); reset_enpci()
167 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); reset_enpci()
168 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); // LED off reset_enpci()
173 enpci_card_msg(struct IsdnCardState *cs, int mt, void *arg) enpci_card_msg() argument
178 if (cs->debug & L1_DEB_ISAC) enpci_card_msg()
179 debugl1(cs, "enter:now PCI: card_msg: 0x%04X", mt); enpci_card_msg()
183 spin_lock_irqsave(&cs->lock, flags); enpci_card_msg()
184 reset_enpci(cs); enpci_card_msg()
185 Amd7930_init(cs); enpci_card_msg()
186 spin_unlock_irqrestore(&cs->lock, flags); enpci_card_msg()
189 release_io_netjet(cs); enpci_card_msg()
192 reset_enpci(cs); enpci_card_msg()
193 inittiger(cs); enpci_card_msg()
195 Amd7930_init(cs); enpci_card_msg()
201 cs->hw.njet.auxd = TJ_AMD_IRQ << 1; enpci_card_msg()
202 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
206 cs->hw.njet.auxd = 0; enpci_card_msg()
207 outb(0x00, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
213 if (cs->debug & L1_DEB_ISAC) enpci_card_msg()
214 debugl1(cs, "enter:now PCI: assign phys. BC %d in AMD LMR1", *chan); enpci_card_msg()
216 cs->dc.amd7930.ph_command(cs, (cs->dc.amd7930.lmr1 | (*chan + 1)), "MDL_BC_ASSIGN"); enpci_card_msg()
218 cs->hw.njet.auxd |= TJ_AMD_IRQ << 2; enpci_card_msg()
219 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
225 if (cs->debug & L1_DEB_ISAC) enpci_card_msg()
226 debugl1(cs, "enter:now PCI: release phys. BC %d in Amd LMR1", *chan); enpci_card_msg()
228 cs->dc.amd7930.ph_command(cs, (cs->dc.amd7930.lmr1 & ~(*chan + 1)), "MDL_BC_RELEASE"); enpci_card_msg()
230 if (!(cs->dc.amd7930.lmr1 & 3)) { enpci_card_msg()
231 cs->hw.njet.auxd &= ~(TJ_AMD_IRQ << 2); enpci_card_msg()
232 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); enpci_card_msg()
245 struct IsdnCardState *cs = dev_id; enpci_interrupt() local
249 spin_lock_irqsave(&cs->lock, flags); enpci_interrupt()
250 s1val = inb(cs->hw.njet.base + NETJET_IRQSTAT1); enpci_interrupt()
255 ir = ReadByteAmd7930(cs, 0x00); enpci_interrupt()
256 Amd7930_interrupt(cs, ir); enpci_interrupt()
260 s0val = inb(cs->hw.njet.base + NETJET_IRQSTAT0); enpci_interrupt()
262 spin_unlock_irqrestore(&cs->lock, flags); enpci_interrupt()
266 outb(s0val, cs->hw.njet.base + NETJET_IRQSTAT0); enpci_interrupt()
270 if (inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR) < enpci_interrupt()
271 inl(cs->hw.njet.base + NETJET_DMA_WRITE_IRQ)) enpci_interrupt()
276 if (inl(cs->hw.njet.base + NETJET_DMA_READ_ADR) < enpci_interrupt()
277 inl(cs->hw.njet.base + NETJET_DMA_READ_IRQ)) enpci_interrupt()
282 if (s0val != cs->hw.njet.last_is0) /* we have a DMA interrupt */ enpci_interrupt()
284 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { enpci_interrupt()
285 spin_unlock_irqrestore(&cs->lock, flags); enpci_interrupt()
288 cs->hw.njet.irqstat0 = s0val; enpci_interrupt()
289 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_READ) != enpci_interrupt()
290 (cs->hw.njet.last_is0 & NETJET_IRQM0_READ)) enpci_interrupt()
292 read_tiger(cs); enpci_interrupt()
293 if ((cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE) != enpci_interrupt()
294 (cs->hw.njet.last_is0 & NETJET_IRQM0_WRITE)) enpci_interrupt()
296 write_tiger(cs); enpci_interrupt()
297 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); enpci_interrupt()
299 spin_unlock_irqrestore(&cs->lock, flags); enpci_interrupt()
303 static int en_pci_probe(struct pci_dev *dev_netjet, struct IsdnCardState *cs) en_pci_probe() argument
307 cs->irq = dev_netjet->irq; en_pci_probe()
308 if (!cs->irq) { en_pci_probe()
312 cs->hw.njet.base = pci_resource_start(dev_netjet, 0); en_pci_probe()
313 if (!cs->hw.njet.base) { en_pci_probe()
328 static void en_cs_init(struct IsdnCard *card, struct IsdnCardState *cs) en_cs_init() argument
330 cs->hw.njet.auxa = cs->hw.njet.base + NETJET_AUXDATA; en_cs_init()
331 cs->hw.njet.isac = cs->hw.njet.base + 0xC0; // Fenster zum AMD en_cs_init()
334 cs->hw.njet.ctrl_reg = 0x07; // geändert von 0xff en_cs_init()
335 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); en_cs_init()
339 cs->hw.njet.ctrl_reg = 0x30; /* Reset Off and status read clear */ en_cs_init()
340 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); en_cs_init()
343 cs->hw.njet.auxd = 0x00; // war 0xc0 en_cs_init()
344 cs->hw.njet.dmactrl = 0; en_cs_init()
346 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); en_cs_init()
347 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); en_cs_init()
348 outb(cs->hw.njet.auxd, cs->hw.njet.auxa); en_cs_init()
351 static int en_cs_init_rest(struct IsdnCard *card, struct IsdnCardState *cs) en_cs_init_rest() argument
357 cs->hw.njet.base, cs->irq); en_cs_init_rest()
358 if (!request_region(cs->hw.njet.base, bytecnt, "Fn_ISDN")) { en_cs_init_rest()
361 cs->hw.njet.base, en_cs_init_rest()
362 cs->hw.njet.base + bytecnt); en_cs_init_rest()
366 setup_Amd7930(cs); en_cs_init_rest()
367 cs->hw.njet.last_is0 = 0; en_cs_init_rest()
369 cs->readisac = &ReadByteAmd7930; en_cs_init_rest()
371 cs->writeisac = &WriteByteAmd7930; en_cs_init_rest()
372 cs->dc.amd7930.setIrqMask = &enpci_setIrqMask; en_cs_init_rest()
374 cs->BC_Read_Reg = &dummyrr; en_cs_init_rest()
375 cs->BC_Write_Reg = &dummywr; en_cs_init_rest()
376 cs->BC_Send_Data = &netjet_fill_dma; en_cs_init_rest()
377 cs->cardmsg = &enpci_card_msg; en_cs_init_rest()
378 cs->irq_func = &enpci_interrupt; en_cs_init_rest()
379 cs->irq_flags |= IRQF_SHARED; en_cs_init_rest()
390 struct IsdnCardState *cs = card->cs; setup_enternow_pci() local
399 if (cs->typ != ISDN_CTYPE_ENTERNOW) setup_enternow_pci()
401 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); setup_enternow_pci()
407 ret = en_pci_probe(dev_netjet, cs); setup_enternow_pci()
415 en_cs_init(card, cs); setup_enternow_pci()
419 return en_cs_init_rest(card, cs); setup_enternow_pci()
|
| H A D | gazel.c | 104 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
108 switch (cs->subtyp) { ReadISAC()
112 return (readreg(cs->hw.gazel.isac, off2)); ReadISAC()
115 return (readreg_ipac(cs->hw.gazel.ipac, 0x80 + off2)); ReadISAC()
121 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
125 switch (cs->subtyp) { WriteISAC()
129 writereg(cs->hw.gazel.isac, off2, value); WriteISAC()
133 writereg_ipac(cs->hw.gazel.ipac, 0x80 + off2, value); WriteISAC()
139 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
141 switch (cs->subtyp) { ReadISACfifo()
144 read_fifo(cs->hw.gazel.isacfifo, data, size); ReadISACfifo()
148 read_fifo_ipac(cs->hw.gazel.ipac, 0x80, data, size); ReadISACfifo()
154 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
156 switch (cs->subtyp) { WriteISACfifo()
159 write_fifo(cs->hw.gazel.isacfifo, data, size); WriteISACfifo()
163 write_fifo_ipac(cs->hw.gazel.ipac, 0x80, data, size); WriteISACfifo()
169 ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) ReadHSCXfifo() argument
171 switch (cs->subtyp) { ReadHSCXfifo()
174 read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); ReadHSCXfifo()
178 read_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); ReadHSCXfifo()
184 WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u_char *data, int size) WriteHSCXfifo() argument
186 switch (cs->subtyp) { WriteHSCXfifo()
189 write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size); WriteHSCXfifo()
193 write_fifo_ipac(cs->hw.gazel.ipac, hscx * 0x40, data, size); WriteHSCXfifo()
199 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
203 switch (cs->subtyp) { ReadHSCX()
207 return (readreg(cs->hw.gazel.hscx[hscx], off2)); ReadHSCX()
210 return (readreg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2)); ReadHSCX()
216 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
220 switch (cs->subtyp) { WriteHSCX()
224 writereg(cs->hw.gazel.hscx[hscx], off2, value); WriteHSCX()
228 writereg_ipac(cs->hw.gazel.ipac, hscx * 0x40 + off2, value); WriteHSCX()
237 #define READHSCX(cs, nr, reg) ReadHSCX(cs, nr, reg)
238 #define WRITEHSCX(cs, nr, reg, data) WriteHSCX(cs, nr, reg, data)
239 #define READHSCXFIFO(cs, nr, ptr, cnt) ReadHSCXfifo(cs, nr, ptr, cnt)
240 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) WriteHSCXfifo(cs, nr, ptr, cnt)
248 struct IsdnCardState *cs = dev_id; gazel_interrupt() local
253 spin_lock_irqsave(&cs->lock, flags); gazel_interrupt()
255 valhscx = ReadHSCX(cs, 1, HSCX_ISTA); gazel_interrupt()
257 hscx_int_main(cs, valhscx); gazel_interrupt()
258 valisac = ReadISAC(cs, ISAC_ISTA); gazel_interrupt()
260 isac_interrupt(cs, valisac); gazel_interrupt()
264 WriteHSCX(cs, 0, HSCX_MASK, 0xFF); gazel_interrupt()
265 WriteHSCX(cs, 1, HSCX_MASK, 0xFF); gazel_interrupt()
266 WriteISAC(cs, ISAC_MASK, 0xFF); gazel_interrupt()
267 WriteISAC(cs, ISAC_MASK, 0x0); gazel_interrupt()
268 WriteHSCX(cs, 0, HSCX_MASK, 0x0); gazel_interrupt()
269 WriteHSCX(cs, 1, HSCX_MASK, 0x0); gazel_interrupt()
270 spin_unlock_irqrestore(&cs->lock, flags); gazel_interrupt()
278 struct IsdnCardState *cs = dev_id; gazel_interrupt_ipac() local
283 spin_lock_irqsave(&cs->lock, flags); gazel_interrupt_ipac()
284 ista = ReadISAC(cs, IPAC_ISTA - 0x80); gazel_interrupt_ipac()
287 val = ReadHSCX(cs, 1, HSCX_ISTA); gazel_interrupt_ipac()
295 hscx_int_main(cs, val); gazel_interrupt_ipac()
299 val = 0xfe & ReadISAC(cs, ISAC_ISTA); gazel_interrupt_ipac()
301 isac_interrupt(cs, val); gazel_interrupt_ipac()
306 isac_interrupt(cs, val); gazel_interrupt_ipac()
308 ista = ReadISAC(cs, IPAC_ISTA - 0x80); gazel_interrupt_ipac()
313 WriteISAC(cs, IPAC_MASK - 0x80, 0xFF); gazel_interrupt_ipac()
314 WriteISAC(cs, IPAC_MASK - 0x80, 0xC0); gazel_interrupt_ipac()
315 spin_unlock_irqrestore(&cs->lock, flags); gazel_interrupt_ipac()
320 release_io_gazel(struct IsdnCardState *cs) release_io_gazel() argument
324 switch (cs->subtyp) { release_io_gazel()
327 release_region(i + cs->hw.gazel.hscx[0], 16); release_io_gazel()
328 release_region(0xC000 + cs->hw.gazel.hscx[0], 1); release_io_gazel()
332 release_region(cs->hw.gazel.hscx[0], 0x100); release_io_gazel()
333 release_region(cs->hw.gazel.cfg_reg, 0x80); release_io_gazel()
337 release_region(cs->hw.gazel.ipac, 0x8); release_io_gazel()
338 release_region(cs->hw.gazel.cfg_reg, 0x80); release_io_gazel()
342 release_region(cs->hw.gazel.ipac, 8); release_io_gazel()
348 reset_gazel(struct IsdnCardState *cs) reset_gazel() argument
350 unsigned long plxcntrl, addr = cs->hw.gazel.cfg_reg; reset_gazel()
352 switch (cs->subtyp) { reset_gazel()
374 WriteISAC(cs, IPAC_POTA2 - 0x80, 0x20); reset_gazel()
378 WriteISAC(cs, IPAC_POTA2 - 0x80, 0x00); reset_gazel()
379 WriteISAC(cs, IPAC_ACFG - 0x80, 0xff); reset_gazel()
380 WriteISAC(cs, IPAC_AOE - 0x80, 0x0); reset_gazel()
381 WriteISAC(cs, IPAC_MASK - 0x80, 0xff); reset_gazel()
382 WriteISAC(cs, IPAC_CONF - 0x80, 0x1); reset_gazel()
384 WriteISAC(cs, IPAC_MASK - 0x80, 0xc0); reset_gazel()
387 WriteISAC(cs, IPAC_POTA2 - 0x80, 0x20); reset_gazel()
389 WriteISAC(cs, IPAC_POTA2 - 0x80, 0x00); reset_gazel()
390 WriteISAC(cs, IPAC_ACFG - 0x80, 0xff); reset_gazel()
391 WriteISAC(cs, IPAC_AOE - 0x80, 0x0); reset_gazel()
392 WriteISAC(cs, IPAC_MASK - 0x80, 0xff); reset_gazel()
393 WriteISAC(cs, IPAC_CONF - 0x80, 0x1); reset_gazel()
394 WriteISAC(cs, IPAC_MASK - 0x80, 0xc0); reset_gazel()
401 Gazel_card_msg(struct IsdnCardState *cs, int mt, void *arg) Gazel_card_msg() argument
407 spin_lock_irqsave(&cs->lock, flags); Gazel_card_msg()
408 reset_gazel(cs); Gazel_card_msg()
409 spin_unlock_irqrestore(&cs->lock, flags); Gazel_card_msg()
412 release_io_gazel(cs); Gazel_card_msg()
415 spin_lock_irqsave(&cs->lock, flags); Gazel_card_msg()
416 inithscxisac(cs, 1); Gazel_card_msg()
417 if ((cs->subtyp == R647) || (cs->subtyp == R685)) { Gazel_card_msg()
420 cs->bcs[i].hw.hscx.tsaxr0 = 0x1f; Gazel_card_msg()
421 cs->bcs[i].hw.hscx.tsaxr1 = 0x23; Gazel_card_msg()
424 spin_unlock_irqrestore(&cs->lock, flags); Gazel_card_msg()
433 reserve_regions(struct IsdnCard *card, struct IsdnCardState *cs) reserve_regions() argument
437 switch (cs->subtyp) { reserve_regions()
439 base = cs->hw.gazel.hscx[0]; reserve_regions()
455 if (!request_region(adr = cs->hw.gazel.hscx[0], len = 0x100, "gazel")) reserve_regions()
457 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { reserve_regions()
458 release_region(cs->hw.gazel.hscx[0], 0x100); reserve_regions()
464 if (!request_region(adr = cs->hw.gazel.ipac, len = 0x8, "gazel")) reserve_regions()
466 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { reserve_regions()
467 release_region(cs->hw.gazel.ipac, 8); reserve_regions()
473 if (!request_region(adr = cs->hw.gazel.ipac, len = 0x8, "gazel")) reserve_regions()
486 static int setup_gazelisa(struct IsdnCard *card, struct IsdnCardState *cs) setup_gazelisa() argument
494 cs->subtyp = R742; setup_gazelisa()
496 cs->subtyp = R647; setup_gazelisa()
498 setup_isac(cs); setup_gazelisa()
499 cs->hw.gazel.cfg_reg = card->para[1] + 0xC000; setup_gazelisa()
500 cs->hw.gazel.ipac = card->para[1]; setup_gazelisa()
501 cs->hw.gazel.isac = card->para[1] + 0x8000; setup_gazelisa()
502 cs->hw.gazel.hscx[0] = card->para[1]; setup_gazelisa()
503 cs->hw.gazel.hscx[1] = card->para[1] + 0x4000; setup_gazelisa()
504 cs->irq = card->para[0]; setup_gazelisa()
505 cs->hw.gazel.isacfifo = cs->hw.gazel.isac; setup_gazelisa()
506 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0]; setup_gazelisa()
507 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1]; setup_gazelisa()
509 switch (cs->subtyp) { setup_gazelisa()
512 cs->dc.isac.adf2 = 0x87; setup_gazelisa()
515 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); setup_gazelisa()
518 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]); setup_gazelisa()
523 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_gazelisa()
526 cs->irq, cs->hw.gazel.ipac); setup_gazelisa()
536 static int setup_gazelpci(struct IsdnCardState *cs) setup_gazelpci() argument
580 cs->hw.gazel.pciaddr[0] = pci_ioaddr0; setup_gazelpci()
581 cs->hw.gazel.pciaddr[1] = pci_ioaddr1; setup_gazelpci()
582 setup_isac(cs); setup_gazelpci()
584 cs->hw.gazel.cfg_reg = pci_ioaddr0 & 0xfffe; setup_gazelpci()
585 cs->hw.gazel.ipac = pci_ioaddr1; setup_gazelpci()
586 cs->hw.gazel.isac = pci_ioaddr1 + 0x80; setup_gazelpci()
587 cs->hw.gazel.hscx[0] = pci_ioaddr1; setup_gazelpci()
588 cs->hw.gazel.hscx[1] = pci_ioaddr1 + 0x40; setup_gazelpci()
589 cs->hw.gazel.isacfifo = cs->hw.gazel.isac; setup_gazelpci()
590 cs->hw.gazel.hscxfifo[0] = cs->hw.gazel.hscx[0]; setup_gazelpci()
591 cs->hw.gazel.hscxfifo[1] = cs->hw.gazel.hscx[1]; setup_gazelpci()
592 cs->irq = pci_irq; setup_gazelpci()
593 cs->irq_flags |= IRQF_SHARED; setup_gazelpci()
598 cs->subtyp = R685; setup_gazelpci()
599 cs->dc.isac.adf2 = 0x87; setup_gazelpci()
602 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); setup_gazelpci()
605 cs->hw.gazel.hscx[0], cs->hw.gazel.hscx[1]); setup_gazelpci()
611 cs->subtyp = R753; setup_gazelpci()
612 test_and_set_bit(HW_IPAC, &cs->HW_Flags); setup_gazelpci()
615 cs->irq, cs->hw.gazel.ipac, cs->hw.gazel.cfg_reg); setup_gazelpci()
625 struct IsdnCardState *cs = card->cs; setup_gazel() local
632 if (cs->typ != ISDN_CTYPE_GAZEL) setup_gazel()
636 if (setup_gazelisa(card, cs)) setup_gazel()
641 if (setup_gazelpci(cs)) setup_gazel()
649 if (reserve_regions(card, cs)) { setup_gazel()
652 if (reset_gazel(cs)) { setup_gazel()
654 release_io_gazel(cs); setup_gazel()
657 cs->readisac = &ReadISAC; setup_gazel()
658 cs->writeisac = &WriteISAC; setup_gazel()
659 cs->readisacfifo = &ReadISACfifo; setup_gazel()
660 cs->writeisacfifo = &WriteISACfifo; setup_gazel()
661 cs->BC_Read_Reg = &ReadHSCX; setup_gazel()
662 cs->BC_Write_Reg = &WriteHSCX; setup_gazel()
663 cs->BC_Send_Data = &hscx_fill_fifo; setup_gazel()
664 cs->cardmsg = &Gazel_card_msg; setup_gazel()
666 switch (cs->subtyp) { setup_gazel()
669 cs->irq_func = &gazel_interrupt; setup_gazel()
670 ISACVersion(cs, "Gazel:"); setup_gazel()
671 if (HscxVersion(cs, "Gazel:")) { setup_gazel()
674 release_io_gazel(cs); setup_gazel()
680 cs->irq_func = &gazel_interrupt_ipac; setup_gazel()
681 val = ReadISAC(cs, IPAC_ID - 0x80); setup_gazel()
|
| H A D | telespci.c | 181 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
183 return (readisac(cs->hw.teles0.membase, offset)); ReadISAC()
187 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
189 writeisac(cs->hw.teles0.membase, offset, value); WriteISAC()
193 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
195 read_fifo_isac(cs->hw.teles0.membase, data, size); ReadISACfifo()
199 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
201 write_fifo_isac(cs->hw.teles0.membase, data, size); WriteISACfifo()
205 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) ReadHSCX() argument
207 return (readhscx(cs->hw.teles0.membase, hscx, offset)); ReadHSCX()
211 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value) WriteHSCX() argument
213 writehscx(cs->hw.teles0.membase, hscx, offset, value); WriteHSCX()
220 #define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
221 #define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
222 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
223 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
230 struct IsdnCardState *cs = dev_id; telespci_interrupt() local
234 spin_lock_irqsave(&cs->lock, flags); telespci_interrupt()
235 hval = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA); telespci_interrupt()
237 hscx_int_main(cs, hval); telespci_interrupt()
238 ival = readisac(cs->hw.teles0.membase, ISAC_ISTA); telespci_interrupt()
240 spin_unlock_irqrestore(&cs->lock, flags); telespci_interrupt()
244 isac_interrupt(cs, ival); telespci_interrupt()
246 writel(0x70000000, cs->hw.teles0.membase + 0x3C); telespci_interrupt()
248 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF); telespci_interrupt()
249 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF); telespci_interrupt()
250 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0xFF); telespci_interrupt()
251 writeisac(cs->hw.teles0.membase, ISAC_MASK, 0x0); telespci_interrupt()
252 writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0); telespci_interrupt()
253 writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0); telespci_interrupt()
254 spin_unlock_irqrestore(&cs->lock, flags); telespci_interrupt()
259 release_io_telespci(struct IsdnCardState *cs) release_io_telespci() argument
261 iounmap(cs->hw.teles0.membase); release_io_telespci()
265 TelesPCI_card_msg(struct IsdnCardState *cs, int mt, void *arg) TelesPCI_card_msg() argument
273 release_io_telespci(cs); TelesPCI_card_msg()
276 spin_lock_irqsave(&cs->lock, flags); TelesPCI_card_msg()
277 inithscxisac(cs, 3); TelesPCI_card_msg()
278 spin_unlock_irqrestore(&cs->lock, flags); TelesPCI_card_msg()
290 struct IsdnCardState *cs = card->cs; setup_telespci() local
295 if (cs->typ != ISDN_CTYPE_TELESPCI) setup_telespci()
301 cs->irq = dev_tel->irq; setup_telespci()
302 if (!cs->irq) { setup_telespci()
306 cs->hw.teles0.membase = ioremap(pci_resource_start(dev_tel, 0), setup_telespci()
317 writel(0x00000000, cs->hw.teles0.membase + 0x28); setup_telespci()
318 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
319 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
320 writel(0x7BFFFFFF, cs->hw.teles0.membase + 0x2C); setup_telespci()
321 writel(0x70000000, cs->hw.teles0.membase + 0x3C); setup_telespci()
322 writel(0x61000000, cs->hw.teles0.membase + 0x40); setup_telespci()
323 /* writel(0x00800000, cs->hw.teles0.membase + 0x200); */ setup_telespci()
327 cs->irq, setup_telespci()
328 cs->hw.teles0.membase); setup_telespci()
330 setup_isac(cs); setup_telespci()
331 cs->readisac = &ReadISAC; setup_telespci()
332 cs->writeisac = &WriteISAC; setup_telespci()
333 cs->readisacfifo = &ReadISACfifo; setup_telespci()
334 cs->writeisacfifo = &WriteISACfifo; setup_telespci()
335 cs->BC_Read_Reg = &ReadHSCX; setup_telespci()
336 cs->BC_Write_Reg = &WriteHSCX; setup_telespci()
337 cs->BC_Send_Data = &hscx_fill_fifo; setup_telespci()
338 cs->cardmsg = &TelesPCI_card_msg; setup_telespci()
339 cs->irq_func = &telespci_interrupt; setup_telespci()
340 cs->irq_flags |= IRQF_SHARED; setup_telespci()
341 ISACVersion(cs, "TelesPCI:"); setup_telespci()
342 if (HscxVersion(cs, "TelesPCI:")) { setup_telespci()
345 release_io_telespci(cs); setup_telespci()
|
| H A D | hscx_irq.c | 17 waitforCEC(struct IsdnCardState *cs, int hscx) waitforCEC() argument
21 while ((READHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) { waitforCEC()
31 waitforXFW(struct IsdnCardState *cs, int hscx) waitforXFW() argument
35 while (((READHSCX(cs, hscx, HSCX_STAR) & 0x44) != 0x40) && to) { waitforXFW()
44 WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data) WriteHSCXCMDR() argument
46 waitforCEC(cs, hscx); WriteHSCXCMDR()
47 WRITEHSCX(cs, hscx, HSCX_CMDR, data); WriteHSCXCMDR()
56 struct IsdnCardState *cs = bcs->cs; hscx_empty_fifo() local
58 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hscx_empty_fifo()
59 debugl1(cs, "hscx_empty_fifo"); hscx_empty_fifo()
62 if (cs->debug & L1_DEB_WARN) hscx_empty_fifo()
63 debugl1(cs, "hscx_empty_fifo: incoming packet too large"); hscx_empty_fifo()
64 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); hscx_empty_fifo()
70 READHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count); hscx_empty_fifo()
71 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80); hscx_empty_fifo()
72 if (cs->debug & L1_DEB_HSCX_FIFO) { hscx_empty_fifo()
78 debugl1(cs, "%s", bcs->blog); hscx_empty_fifo()
85 struct IsdnCardState *cs = bcs->cs; hscx_fill_fifo() local
87 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32; hscx_fill_fifo()
90 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hscx_fill_fifo()
91 debugl1(cs, "hscx_fill_fifo"); hscx_fill_fifo()
105 waitforXFW(cs, bcs->hw.hscx.hscx); hscx_fill_fifo()
110 WRITEHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count); hscx_fill_fifo()
111 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa); hscx_fill_fifo()
112 if (cs->debug & L1_DEB_HSCX_FIFO) { hscx_fill_fifo()
118 debugl1(cs, "%s", bcs->blog); hscx_fill_fifo()
123 hscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx) hscx_interrupt() argument
126 struct BCState *bcs = cs->bcs + hscx; hscx_interrupt()
128 int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags) ? 64 : 32; hscx_interrupt()
135 r = READHSCX(cs, hscx, HSCX_RSTA); hscx_interrupt()
138 if (cs->debug & L1_DEB_WARN) hscx_interrupt()
139 debugl1(cs, "HSCX invalid frame"); hscx_interrupt()
145 if (cs->debug & L1_DEB_WARN) hscx_interrupt()
146 debugl1(cs, "HSCX RDO mode=%d", hscx_interrupt()
153 if (cs->debug & L1_DEB_WARN) hscx_interrupt()
154 debugl1(cs, "HSCX CRC error"); hscx_interrupt()
159 WriteHSCXCMDR(cs, hscx, 0x80); hscx_interrupt()
161 count = READHSCX(cs, hscx, HSCX_RBCL) & ( hscx_interrupt()
162 test_bit(HW_IPAC, &cs->HW_Flags) ? 0x3f : 0x1f); hscx_interrupt()
167 if (cs->debug & L1_DEB_HSCX_FIFO) hscx_interrupt()
168 debugl1(cs, "HX Frame %d", count); hscx_interrupt()
225 hscx_int_main(struct IsdnCardState *cs, u_char val) hscx_int_main() argument
232 bcs = cs->bcs + 1; hscx_int_main()
233 exval = READHSCX(cs, 1, HSCX_EXIR); hscx_int_main()
249 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); hscx_int_main()
250 if (cs->debug & L1_DEB_WARN) hscx_int_main()
251 debugl1(cs, "HSCX B EXIR %x Lost TX", exval); hscx_int_main()
253 } else if (cs->debug & L1_DEB_HSCX) hscx_int_main()
254 debugl1(cs, "HSCX B EXIR %x", exval); hscx_int_main()
257 if (cs->debug & L1_DEB_HSCX) hscx_int_main()
258 debugl1(cs, "HSCX B interrupt %x", val); hscx_int_main()
259 hscx_interrupt(cs, val, 1); hscx_int_main()
262 bcs = cs->bcs; hscx_int_main()
263 exval = READHSCX(cs, 0, HSCX_EXIR); hscx_int_main()
279 WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01); hscx_int_main()
280 if (cs->debug & L1_DEB_WARN) hscx_int_main()
281 debugl1(cs, "HSCX A EXIR %x Lost TX", exval); hscx_int_main()
283 } else if (cs->debug & L1_DEB_HSCX) hscx_int_main()
284 debugl1(cs, "HSCX A EXIR %x", exval); hscx_int_main()
287 exval = READHSCX(cs, 0, HSCX_ISTA); hscx_int_main()
288 if (cs->debug & L1_DEB_HSCX) hscx_int_main()
289 debugl1(cs, "HSCX A interrupt %x", exval); hscx_int_main()
290 hscx_interrupt(cs, exval, 0); hscx_int_main()
|
| H A D | avm_pci.c | 78 ReadISAC(struct IsdnCardState *cs, u_char offset) ReadISAC() argument
83 outb(idx, cs->hw.avm.cfg_reg + 4); ReadISAC()
84 val = inb(cs->hw.avm.isac + (offset & 0xf)); ReadISAC()
89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) WriteISAC() argument
93 outb(idx, cs->hw.avm.cfg_reg + 4); WriteISAC()
94 outb(value, cs->hw.avm.isac + (offset & 0xf)); WriteISAC()
98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) ReadISACfifo() argument
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); ReadISACfifo()
101 insb(cs->hw.avm.isac, data, size); ReadISACfifo()
105 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) WriteISACfifo() argument
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); WriteISACfifo()
108 outsb(cs->hw.avm.isac, data, size); WriteISACfifo()
112 ReadHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset) ReadHDLCPCI() argument
117 outl(idx, cs->hw.avm.cfg_reg + 4); ReadHDLCPCI()
118 val = inl(cs->hw.avm.isac + offset); ReadHDLCPCI()
123 WriteHDLCPCI(struct IsdnCardState *cs, int chan, u_char offset, u_int value) WriteHDLCPCI() argument
127 outl(idx, cs->hw.avm.cfg_reg + 4); WriteHDLCPCI()
128 outl(value, cs->hw.avm.isac + offset); WriteHDLCPCI()
132 ReadHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset) ReadHDLCPnP() argument
137 outb(idx, cs->hw.avm.cfg_reg + 4); ReadHDLCPnP()
138 val = inb(cs->hw.avm.isac + offset); ReadHDLCPnP()
143 WriteHDLCPnP(struct IsdnCardState *cs, int chan, u_char offset, u_char value) WriteHDLCPnP() argument
147 outb(idx, cs->hw.avm.cfg_reg + 4); WriteHDLCPnP()
148 outb(value, cs->hw.avm.isac + offset); WriteHDLCPnP()
152 ReadHDLC_s(struct IsdnCardState *cs, int chan, u_char offset) ReadHDLC_s() argument
154 return (0xff & ReadHDLCPCI(cs, chan, offset)); ReadHDLC_s()
158 WriteHDLC_s(struct IsdnCardState *cs, int chan, u_char offset, u_char value) WriteHDLC_s() argument
160 WriteHDLCPCI(cs, chan, offset, value); WriteHDLC_s()
164 struct BCState *Sel_BCS(struct IsdnCardState *cs, int channel) Sel_BCS() argument
166 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) Sel_BCS()
167 return (&cs->bcs[0]); Sel_BCS()
168 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) Sel_BCS()
169 return (&cs->bcs[1]); Sel_BCS()
177 if (bcs->cs->debug & L1_DEB_HSCX) write_ctrl()
178 debugl1(bcs->cs, "hdlc %c wr%x ctrl %x", write_ctrl()
180 if (bcs->cs->subtyp == AVM_FRITZ_PCI) { write_ctrl()
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl); write_ctrl()
184 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 2, write_ctrl()
187 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS + 1, write_ctrl()
190 WriteHDLCPnP(bcs->cs, bcs->channel, HDLC_STATUS, write_ctrl()
198 struct IsdnCardState *cs = bcs->cs; modehdlc() local
201 if (cs->debug & L1_DEB_HSCX) modehdlc()
202 debugl1(cs, "hdlc %c mode %d --> %d ichan %d --> %d", modehdlc()
251 struct IsdnCardState *cs = bcs->cs; hdlc_empty_fifo() local
253 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hdlc_empty_fifo()
254 debugl1(cs, "hdlc_empty_fifo %d", count); hdlc_empty_fifo()
256 if (cs->debug & L1_DEB_WARN) hdlc_empty_fifo()
257 debugl1(cs, "hdlc_empty_fifo: incoming packet too large"); hdlc_empty_fifo()
263 if (cs->subtyp == AVM_FRITZ_PCI) { hdlc_empty_fifo()
264 outl(idx, cs->hw.avm.cfg_reg + 4); hdlc_empty_fifo()
267 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE)); hdlc_empty_fifo()
269 *ptr++ = inl(cs->hw.avm.isac); hdlc_empty_fifo()
274 outb(idx, cs->hw.avm.cfg_reg + 4); hdlc_empty_fifo()
276 *p++ = inb(cs->hw.avm.isac); hdlc_empty_fifo()
280 if (cs->debug & L1_DEB_HSCX_FIFO) { hdlc_empty_fifo()
283 if (cs->subtyp == AVM_FRITZ_PNP) hdlc_empty_fifo()
288 debugl1(cs, "%s", bcs->blog); hdlc_empty_fifo()
295 struct IsdnCardState *cs = bcs->cs; hdlc_fill_fifo() local
301 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hdlc_fill_fifo()
302 debugl1(cs, "hdlc_fill_fifo"); hdlc_fill_fifo()
316 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) hdlc_fill_fifo()
317 debugl1(cs, "hdlc_fill_fifo %d/%u", count, bcs->tx_skb->len); hdlc_fill_fifo()
325 if (cs->subtyp == AVM_FRITZ_PCI) { hdlc_fill_fifo()
328 out_be32((unsigned *)(cs->hw.avm.isac + _IO_BASE), *ptr++); hdlc_fill_fifo()
330 outl(*ptr++, cs->hw.avm.isac); hdlc_fill_fifo()
336 outb(*p++, cs->hw.avm.isac); hdlc_fill_fifo()
340 if (cs->debug & L1_DEB_HSCX_FIFO) { hdlc_fill_fifo()
343 if (cs->subtyp == AVM_FRITZ_PNP) hdlc_fill_fifo()
348 debugl1(cs, "%s", bcs->blog); hdlc_fill_fifo()
357 if (bcs->cs->debug & L1_DEB_HSCX) HDLC_irq()
358 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat); HDLC_irq()
361 if (bcs->cs->debug & L1_DEB_HSCX) HDLC_irq()
362 debugl1(bcs->cs, "RDO"); HDLC_irq()
364 debugl1(bcs->cs, "ch%d stat %#x", bcs->channel, stat); HDLC_irq()
388 if (bcs->cs->debug & L1_DEB_HSCX) HDLC_irq()
389 debugl1(bcs->cs, "invalid frame"); HDLC_irq()
391 debugl1(bcs->cs, "ch%d invalid frame %#x", bcs->channel, stat); HDLC_irq()
405 if (bcs->cs->debug & L1_DEB_WARN) HDLC_irq()
406 debugl1(bcs->cs, "ch%d XDU", bcs->channel); HDLC_irq()
407 } else if (bcs->cs->debug & L1_DEB_WARN) HDLC_irq()
408 debugl1(bcs->cs, "ch%d XDU without skb", bcs->channel); HDLC_irq()
446 HDLC_irq_main(struct IsdnCardState *cs) HDLC_irq_main() argument
451 if (cs->subtyp == AVM_FRITZ_PCI) { HDLC_irq_main()
452 stat = ReadHDLCPCI(cs, 0, HDLC_STATUS); HDLC_irq_main()
454 stat = ReadHDLCPnP(cs, 0, HDLC_STATUS); HDLC_irq_main()
456 stat |= (ReadHDLCPnP(cs, 0, HDLC_STATUS + 1)) << 8; HDLC_irq_main()
459 if (!(bcs = Sel_BCS(cs, 0))) { HDLC_irq_main()
460 if (cs->debug) HDLC_irq_main()
461 debugl1(cs, "hdlc spurious channel 0 IRQ"); HDLC_irq_main()
465 if (cs->subtyp == AVM_FRITZ_PCI) { HDLC_irq_main()
466 stat = ReadHDLCPCI(cs, 1, HDLC_STATUS); HDLC_irq_main()
468 stat = ReadHDLCPnP(cs, 1, HDLC_STATUS); HDLC_irq_main()
470 stat |= (ReadHDLCPnP(cs, 1, HDLC_STATUS + 1)) << 8; HDLC_irq_main()
473 if (!(bcs = Sel_BCS(cs, 1))) { HDLC_irq_main()
474 if (cs->debug) HDLC_irq_main()
475 debugl1(cs, "hdlc spurious channel 1 IRQ"); HDLC_irq_main()
490 spin_lock_irqsave(&bcs->cs->lock, flags); hdlc_l2l1()
497 bcs->cs->BC_Send_Data(bcs); hdlc_l2l1()
499 spin_unlock_irqrestore(&bcs->cs->lock, flags); hdlc_l2l1()
502 spin_lock_irqsave(&bcs->cs->lock, flags); hdlc_l2l1()
509 bcs->cs->BC_Send_Data(bcs); hdlc_l2l1()
511 spin_unlock_irqrestore(&bcs->cs->lock, flags); hdlc_l2l1()
521 spin_lock_irqsave(&bcs->cs->lock, flags); hdlc_l2l1()
524 spin_unlock_irqrestore(&bcs->cs->lock, flags); hdlc_l2l1()
531 spin_lock_irqsave(&bcs->cs->lock, flags); hdlc_l2l1()
535 spin_unlock_irqrestore(&bcs->cs->lock, flags); hdlc_l2l1()
561 open_hdlcstate(struct IsdnCardState *cs, struct BCState *bcs) open_hdlcstate() argument
604 clear_pending_hdlc_ints(struct IsdnCardState *cs)
608 if (cs->subtyp == AVM_FRITZ_PCI) {
609 val = ReadHDLCPCI(cs, 0, HDLC_STATUS);
610 debugl1(cs, "HDLC 1 STA %x", val);
611 val = ReadHDLCPCI(cs, 1, HDLC_STATUS);
612 debugl1(cs, "HDLC 2 STA %x", val);
614 val = ReadHDLCPnP(cs, 0, HDLC_STATUS);
615 debugl1(cs, "HDLC 1 STA %x", val);
616 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 1);
617 debugl1(cs, "HDLC 1 RML %x", val);
618 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 2);
619 debugl1(cs, "HDLC 1 MODE %x", val);
620 val = ReadHDLCPnP(cs, 0, HDLC_STATUS + 3);
621 debugl1(cs, "HDLC 1 VIN %x", val);
622 val = ReadHDLCPnP(cs, 1, HDLC_STATUS);
623 debugl1(cs, "HDLC 2 STA %x", val);
624 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 1);
625 debugl1(cs, "HDLC 2 RML %x", val);
626 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 2);
627 debugl1(cs, "HDLC 2 MODE %x", val);
628 val = ReadHDLCPnP(cs, 1, HDLC_STATUS + 3);
629 debugl1(cs, "HDLC 2 VIN %x", val);
635 inithdlc(struct IsdnCardState *cs) inithdlc() argument
637 cs->bcs[0].BC_SetStack = setstack_hdlc; inithdlc()
638 cs->bcs[1].BC_SetStack = setstack_hdlc; inithdlc()
639 cs->bcs[0].BC_Close = close_hdlcstate; inithdlc()
640 cs->bcs[1].BC_Close = close_hdlcstate; inithdlc()
641 modehdlc(cs->bcs, -1, 0); inithdlc()
642 modehdlc(cs->bcs + 1, -1, 1); inithdlc()
648 struct IsdnCardState *cs = dev_id; avm_pcipnp_interrupt() local
653 spin_lock_irqsave(&cs->lock, flags); avm_pcipnp_interrupt()
654 sval = inb(cs->hw.avm.cfg_reg + 2); avm_pcipnp_interrupt()
657 spin_unlock_irqrestore(&cs->lock, flags); avm_pcipnp_interrupt()
661 val = ReadISAC(cs, ISAC_ISTA); avm_pcipnp_interrupt()
662 isac_interrupt(cs, val); avm_pcipnp_interrupt()
665 HDLC_irq_main(cs); avm_pcipnp_interrupt()
667 WriteISAC(cs, ISAC_MASK, 0xFF); avm_pcipnp_interrupt()
668 WriteISAC(cs, ISAC_MASK, 0x0); avm_pcipnp_interrupt()
669 spin_unlock_irqrestore(&cs->lock, flags); avm_pcipnp_interrupt()
674 reset_avmpcipnp(struct IsdnCardState *cs) reset_avmpcipnp() argument
677 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2); reset_avmpcipnp()
679 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2); reset_avmpcipnp()
680 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3); reset_avmpcipnp()
682 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3)); reset_avmpcipnp()
686 AVM_card_msg(struct IsdnCardState *cs, int mt, void *arg) AVM_card_msg() argument
692 spin_lock_irqsave(&cs->lock, flags); AVM_card_msg()
693 reset_avmpcipnp(cs); AVM_card_msg()
694 spin_unlock_irqrestore(&cs->lock, flags); AVM_card_msg()
697 outb(0, cs->hw.avm.cfg_reg + 2); AVM_card_msg()
698 release_region(cs->hw.avm.cfg_reg, 32); AVM_card_msg()
701 spin_lock_irqsave(&cs->lock, flags); AVM_card_msg()
702 reset_avmpcipnp(cs); AVM_card_msg()
703 clear_pending_isac_ints(cs); AVM_card_msg()
704 initisac(cs); AVM_card_msg()
705 inithdlc(cs); AVM_card_msg()
707 cs->hw.avm.cfg_reg + 2); AVM_card_msg()
708 WriteISAC(cs, ISAC_MASK, 0); AVM_card_msg()
710 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2); AVM_card_msg()
712 WriteISAC(cs, ISAC_CMDR, 0x41); AVM_card_msg()
713 spin_unlock_irqrestore(&cs->lock, flags); AVM_card_msg()
721 static int avm_setup_rest(struct IsdnCardState *cs) avm_setup_rest() argument
725 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10; avm_setup_rest()
726 if (!request_region(cs->hw.avm.cfg_reg, 32, avm_setup_rest()
727 (cs->subtyp == AVM_FRITZ_PCI) ? "avm PCI" : "avm PnP")) { avm_setup_rest()
730 cs->hw.avm.cfg_reg, avm_setup_rest()
731 cs->hw.avm.cfg_reg + 31); avm_setup_rest()
734 switch (cs->subtyp) { avm_setup_rest()
736 val = inl(cs->hw.avm.cfg_reg); avm_setup_rest()
740 cs->BC_Read_Reg = &ReadHDLC_s; avm_setup_rest()
741 cs->BC_Write_Reg = &WriteHDLC_s; avm_setup_rest()
744 val = inb(cs->hw.avm.cfg_reg); avm_setup_rest()
745 ver = inb(cs->hw.avm.cfg_reg + 1); avm_setup_rest()
747 cs->BC_Read_Reg = &ReadHDLCPnP; avm_setup_rest()
748 cs->BC_Write_Reg = &WriteHDLCPnP; avm_setup_rest()
751 printk(KERN_WARNING "AVM unknown subtype %d\n", cs->subtyp); avm_setup_rest()
755 (cs->subtyp == AVM_FRITZ_PCI) ? "AVM Fritz!PCI" : "AVM Fritz!PnP", avm_setup_rest()
756 cs->irq, cs->hw.avm.cfg_reg); avm_setup_rest()
758 setup_isac(cs); avm_setup_rest()
759 cs->readisac = &ReadISAC; avm_setup_rest()
760 cs->writeisac = &WriteISAC; avm_setup_rest()
761 cs->readisacfifo = &ReadISACfifo; avm_setup_rest()
762 cs->writeisacfifo = &WriteISACfifo; avm_setup_rest()
763 cs->BC_Send_Data = &hdlc_fill_fifo; avm_setup_rest()
764 cs->cardmsg = &AVM_card_msg; avm_setup_rest()
765 cs->irq_func = &avm_pcipnp_interrupt; avm_setup_rest()
766 cs->writeisac(cs, ISAC_MASK, 0xFF); avm_setup_rest()
767 ISACVersion(cs, (cs->subtyp == AVM_FRITZ_PCI) ? "AVM PCI:" : "AVM PnP:"); avm_setup_rest()
773 static int avm_pnp_setup(struct IsdnCardState *cs) avm_pnp_setup() argument
782 static int avm_pnp_setup(struct IsdnCardState *cs) avm_pnp_setup() argument
804 cs->hw.avm.cfg_reg = avm_pnp_setup()
806 cs->irq = pnp_irq(pnp_avm_d, 0); avm_pnp_setup()
807 if (!cs->irq) { avm_pnp_setup()
811 if (!cs->hw.avm.cfg_reg) { avm_pnp_setup()
815 cs->subtyp = AVM_FRITZ_PNP; avm_pnp_setup()
828 static int avm_pci_setup(struct IsdnCardState *cs) avm_pci_setup() argument
837 static int avm_pci_setup(struct IsdnCardState *cs) avm_pci_setup() argument
845 cs->irq = dev_avm->irq; avm_pci_setup()
846 if (!cs->irq) { avm_pci_setup()
851 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1); avm_pci_setup()
852 if (!cs->hw.avm.cfg_reg) { avm_pci_setup()
857 cs->subtyp = AVM_FRITZ_PCI; avm_pci_setup()
863 cs->irq_flags |= IRQF_SHARED; avm_pci_setup()
872 struct IsdnCardState *cs = card->cs; setup_avm_pcipnp() local
879 if (cs->typ != ISDN_CTYPE_FRITZPCI) setup_avm_pcipnp()
884 cs->hw.avm.cfg_reg = card->para[1]; setup_avm_pcipnp()
885 cs->irq = card->para[0]; setup_avm_pcipnp()
886 cs->subtyp = AVM_FRITZ_PNP; setup_avm_pcipnp()
890 rc = avm_pnp_setup(cs); setup_avm_pcipnp()
896 rc = avm_pci_setup(cs); setup_avm_pcipnp()
901 return avm_setup_rest(cs); setup_avm_pcipnp()
|
| H A D | isar.c | 31 static void isar_setup(struct IsdnCardState *cs);
36 waitforHIA(struct IsdnCardState *cs, int timeout) waitforHIA() argument
39 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) { waitforHIA()
50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, sendmsg() argument
55 if (!waitforHIA(cs, 4000)) sendmsg()
58 if (cs->debug & L1_DEB_HSCX) sendmsg()
59 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len); sendmsg()
61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); sendmsg()
62 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len); sendmsg()
63 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0); sendmsg()
65 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]); sendmsg()
67 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]); sendmsg()
69 if (cs->debug & L1_DEB_HSCX_FIFO) { sendmsg()
77 debugl1(cs, "%s", tmp); sendmsg()
83 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his); sendmsg()
84 waitforHIA(cs, 10000); sendmsg()
90 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg) rcv_mbox() argument
94 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0); rcv_mbox()
96 msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX); rcv_mbox()
98 msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX); rcv_mbox()
100 if (cs->debug & L1_DEB_HSCX_FIFO) { rcv_mbox()
108 debugl1(cs, "%s", tmp); rcv_mbox()
114 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); rcv_mbox()
119 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg) get_irq_infos() argument
121 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS); get_irq_infos()
122 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H); get_irq_infos()
123 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L); get_irq_infos()
125 if (cs->debug & L1_DEB_HSCX) get_irq_infos()
126 debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb, get_irq_infos()
132 waitrecmsg(struct IsdnCardState *cs, u_char *len, waitrecmsg() argument
136 struct isar_reg *ir = cs->bcs[0].hw.isar.reg; waitrecmsg()
139 while ((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) && waitrecmsg()
146 get_irq_infos(cs, ir); waitrecmsg()
147 rcv_mbox(cs, ir, msg); waitrecmsg()
153 ISARVersion(struct IsdnCardState *cs, char *s) ISARVersion() argument
162 cs->cardmsg(cs, CARD_RESET, NULL); ISARVersion()
163 spin_lock_irqsave(&cs->lock, flags); ISARVersion()
165 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); ISARVersion()
166 debug = cs->debug; ISARVersion()
167 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO); ISARVersion()
168 if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) { ISARVersion()
169 spin_unlock_irqrestore(&cs->lock, flags); ISARVersion()
172 if (!waitrecmsg(cs, &len, tmp, 100000)) { ISARVersion()
173 spin_unlock_irqrestore(&cs->lock, flags); ISARVersion()
176 cs->debug = debug; ISARVersion()
177 if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) { ISARVersion()
185 spin_unlock_irqrestore(&cs->lock, flags); ISARVersion()
190 isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf) isar_load_firmware() argument
198 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg; isar_load_firmware()
206 if (1 != (ret = ISARVersion(cs, "Testing"))) { isar_load_firmware()
210 debug = cs->debug; isar_load_firmware()
212 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO); isar_load_firmware()
224 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
234 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
236 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
237 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
257 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
258 if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) { isar_load_firmware()
262 if (!waitrecmsg(cs, &len, tmp, 100000)) { isar_load_firmware()
271 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
307 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
308 if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) { isar_load_firmware()
312 if (!waitrecmsg(cs, &len, tmp, 100000)) { isar_load_firmware()
321 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
333 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
334 if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) { isar_load_firmware()
338 if (!waitrecmsg(cs, &len, tmp, 100000)) { isar_load_firmware()
350 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA); isar_load_firmware()
351 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
368 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
370 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) { isar_load_firmware()
375 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
393 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
395 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) { isar_load_firmware()
399 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
419 spin_lock_irqsave(&cs->lock, flags); isar_load_firmware()
420 cs->debug = debug; isar_load_firmware()
421 isar_setup(cs); isar_load_firmware()
425 spin_unlock_irqrestore(&cs->lock, flags); isar_load_firmware()
427 cs->debug = debug; isar_load_firmware()
430 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
491 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs) isar_rcv_frame() argument
498 debugl1(cs, "isar zero len frame"); isar_rcv_frame()
499 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
504 debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x", isar_rcv_frame()
508 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
513 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb)); isar_rcv_frame()
518 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
523 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
524 debugl1(cs, "isar_rcv_frame: incoming packet too large"); isar_rcv_frame()
525 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
528 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
529 debugl1(cs, "isar frame error %x len %d", isar_rcv_frame()
538 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
544 rcv_mbox(cs, ireg, ptr); isar_rcv_frame()
547 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
548 debugl1(cs, "isar frame to short %d", isar_rcv_frame()
564 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
565 debugl1(cs, "isar_rcv_frame: not ACTIV"); isar_rcv_frame()
566 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
571 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf); isar_rcv_frame()
574 if (cs->debug & L1_DEB_HSCX) isar_rcv_frame()
575 debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)", isar_rcv_frame()
583 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
584 debugl1(cs, "isar_rcv_frame: no more data"); isar_rcv_frame()
587 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | isar_rcv_frame()
599 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
600 debugl1(cs, "isar_rcv_frame: unknown fax mode %x", isar_rcv_frame()
602 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
608 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
609 debugl1(cs, "isar_rcv_frame: incoming packet too large"); isar_rcv_frame()
610 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
613 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
614 debugl1(cs, "isar frame error %x len %d", isar_rcv_frame()
617 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
624 rcv_mbox(cs, ireg, ptr); isar_rcv_frame()
629 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
630 debugl1(cs, "isar frame to short %d", isar_rcv_frame()
650 if (cs->debug & L1_DEB_WARN) isar_rcv_frame()
651 debugl1(cs, "isar_rcv_frame: no more data"); isar_rcv_frame()
653 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | isar_rcv_frame()
664 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
672 struct IsdnCardState *cs = bcs->cs; isar_fill_fifo() local
677 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) isar_fill_fifo()
678 debugl1(cs, "isar_fill_fifo"); isar_fill_fifo()
715 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, isar_fill_fifo()
719 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, isar_fill_fifo()
724 if (cs->debug & L1_DEB_WARN) isar_fill_fifo()
725 debugl1(cs, "isar_fill_fifo: not ACTIV"); isar_fill_fifo()
727 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, isar_fill_fifo()
730 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA, isar_fill_fifo()
733 if (cs->debug & L1_DEB_WARN) isar_fill_fifo()
734 debugl1(cs, "isar_fill_fifo: not FTH/FTM"); isar_fill_fifo()
738 if (cs->debug) isar_fill_fifo()
739 debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode); isar_fill_fifo()
746 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath) sel_bcs_isar() argument
750 if (cs->bcs[0].hw.isar.dpath == dpath) sel_bcs_isar()
751 return (&cs->bcs[0]); sel_bcs_isar()
752 if (cs->bcs[1].hw.isar.dpath == dpath) sel_bcs_isar()
753 return (&cs->bcs[1]); sel_bcs_isar()
799 sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) | send_frames()
813 check_send(struct IsdnCardState *cs, u_char rdm) check_send() argument
818 if ((bcs = sel_bcs_isar(cs, 1))) { check_send()
825 if ((bcs = sel_bcs_isar(cs, 2))) { check_send()
844 struct IsdnCardState *cs = bcs->cs; isar_pump_status_rsp() local
851 if (cs->debug & L1_DEB_WARN) isar_pump_status_rsp()
852 debugl1(cs, "wrong pstrsp ril=%d", ril); isar_pump_status_rsp()
892 if (cs->debug & L1_DEB_HSCX) isar_pump_status_rsp()
893 debugl1(cs, "pump strsp %s", bcs->conmsg); isar_pump_status_rsp()
898 struct IsdnCardState *cs = bcs->cs; isar_pump_statev_modem() local
903 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
904 debugl1(cs, "pump stev TIMER"); isar_pump_statev_modem()
907 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
908 debugl1(cs, "pump stev CONNECT"); isar_pump_statev_modem()
912 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
913 debugl1(cs, "pump stev NO CONNECT"); isar_pump_statev_modem()
914 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); isar_pump_statev_modem()
918 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
919 debugl1(cs, "pump stev V24 OFF"); isar_pump_statev_modem()
922 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
923 debugl1(cs, "pump stev CTS ON"); isar_pump_statev_modem()
926 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
927 debugl1(cs, "pump stev CTS OFF"); isar_pump_statev_modem()
930 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
931 debugl1(cs, "pump stev CARRIER ON"); isar_pump_statev_modem()
933 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); isar_pump_statev_modem()
936 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
937 debugl1(cs, "pump stev CARRIER OFF"); isar_pump_statev_modem()
940 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
941 debugl1(cs, "pump stev DSR ON"); isar_pump_statev_modem()
944 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
945 debugl1(cs, "pump stev DSR_OFF"); isar_pump_statev_modem()
948 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
949 debugl1(cs, "pump stev REMOTE RETRAIN"); isar_pump_statev_modem()
952 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
953 debugl1(cs, "pump stev REMOTE RENEGOTIATE"); isar_pump_statev_modem()
956 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
957 debugl1(cs, "pump stev GSTN CLEAR"); isar_pump_statev_modem()
960 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_modem()
961 debugl1(cs, "unknown pump stev %x", devt); isar_pump_statev_modem()
972 if (bcs->cs->debug & L1_DEB_HSCX) ll_deliver_faxstat()
973 debugl1(bcs->cs, "HL->LL FAXIND %x", status); ll_deliver_faxstat()
974 ic.driver = bcs->cs->myid; ll_deliver_faxstat()
978 bcs->cs->iif.statcallb(&ic); ll_deliver_faxstat()
983 struct IsdnCardState *cs = bcs->cs; isar_pump_statev_fax() local
989 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
990 debugl1(cs, "pump stev TIMER"); isar_pump_statev_fax()
993 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
994 debugl1(cs, "pump stev RSP_READY"); isar_pump_statev_fax()
1005 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1006 debugl1(cs, "pump stev LINE_TX_H"); isar_pump_statev_fax()
1008 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); isar_pump_statev_fax()
1010 if (cs->debug & L1_DEB_WARN) isar_pump_statev_fax()
1011 debugl1(cs, "pump stev LINE_TX_H wrong st %x", isar_pump_statev_fax()
1017 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1018 debugl1(cs, "pump stev LINE_RX_H"); isar_pump_statev_fax()
1020 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); isar_pump_statev_fax()
1022 if (cs->debug & L1_DEB_WARN) isar_pump_statev_fax()
1023 debugl1(cs, "pump stev LINE_RX_H wrong st %x", isar_pump_statev_fax()
1029 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1030 debugl1(cs, "pump stev LINE_TX_B"); isar_pump_statev_fax()
1032 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); isar_pump_statev_fax()
1034 if (cs->debug & L1_DEB_WARN) isar_pump_statev_fax()
1035 debugl1(cs, "pump stev LINE_TX_B wrong st %x", isar_pump_statev_fax()
1041 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1042 debugl1(cs, "pump stev LINE_RX_B"); isar_pump_statev_fax()
1044 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL); isar_pump_statev_fax()
1046 if (cs->debug & L1_DEB_WARN) isar_pump_statev_fax()
1047 debugl1(cs, "pump stev LINE_RX_B wrong st %x", isar_pump_statev_fax()
1053 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1054 debugl1(cs, "pump stev RSP_CONN"); isar_pump_statev_fax()
1057 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); isar_pump_statev_fax()
1072 if (cs->debug & L1_DEB_WARN) isar_pump_statev_fax()
1073 debugl1(cs, "pump stev RSP_CONN wrong st %x", isar_pump_statev_fax()
1078 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1079 debugl1(cs, "pump stev FLAGS_DET"); isar_pump_statev_fax()
1082 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1083 debugl1(cs, "pump stev RSP_DISC"); isar_pump_statev_fax()
1093 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, isar_pump_statev_fax()
1105 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, isar_pump_statev_fax()
1111 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1112 debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd); isar_pump_statev_fax()
1131 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1132 debugl1(cs, "pump stev RSP_SILDET"); isar_pump_statev_fax()
1138 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, isar_pump_statev_fax()
1145 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1146 debugl1(cs, "pump stev RSP_SILOFF"); isar_pump_statev_fax()
1150 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1151 debugl1(cs, "pump stev RSP_FCERR try %d", isar_pump_statev_fax()
1154 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, isar_pump_statev_fax()
1160 if (cs->debug & L1_DEB_HSCX) isar_pump_statev_fax()
1161 debugl1(cs, "pump stev RSP_FCERR"); isar_pump_statev_fax()
1163 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL); isar_pump_statev_fax()
1174 isar_int_main(struct IsdnCardState *cs) isar_int_main() argument
1176 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg; isar_int_main()
1179 get_irq_infos(cs, ireg); isar_int_main()
1182 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { isar_int_main()
1183 isar_rcv_frame(cs, bcs); isar_int_main()
1185 debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x", isar_int_main()
1187 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1191 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1193 check_send(cs, ireg->cmsb); isar_int_main()
1197 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { isar_int_main()
1204 if (cs->debug & L1_DEB_WARN) isar_int_main()
1205 debugl1(cs, "Buffer STEV dpath%d msb(%x)", isar_int_main()
1207 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1210 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { isar_int_main()
1211 rcv_mbox(cs, ireg, (u_char *)ireg->par); isar_int_main()
1217 if (cs->debug & L1_DEB_HSCX) isar_int_main()
1218 debugl1(cs, "pump stev TIMER"); isar_int_main()
1220 if (cs->debug & L1_DEB_WARN) isar_int_main()
1221 debugl1(cs, "isar IIS_PSTEV pmode %d stat %x", isar_int_main()
1225 debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x", isar_int_main()
1227 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1231 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) { isar_int_main()
1232 rcv_mbox(cs, ireg, (u_char *)ireg->par); isar_int_main()
1235 debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x", isar_int_main()
1237 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1243 rcv_mbox(cs, ireg, (u_char *)ireg->par); isar_int_main()
1244 if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO)) isar_int_main()
1251 debugl1(cs, "%s", debbuf); isar_int_main()
1255 rcv_mbox(cs, ireg, debbuf); isar_int_main()
1256 if (cs->debug & L1_DEB_WARN) isar_int_main()
1257 debugl1(cs, "invalid msg his:%x", isar_int_main()
1261 rcv_mbox(cs, ireg, debbuf); isar_int_main()
1262 if (cs->debug & L1_DEB_WARN) isar_int_main()
1263 debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)", isar_int_main()
1271 if (bcs->cs->debug) ftimer_handler()
1272 debugl1(bcs->cs, "ftimer flags %04lx", ftimer_handler()
1285 struct IsdnCardState *cs = bcs->cs; setup_pump() local
1293 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL); setup_pump()
1309 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param); setup_pump()
1320 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param); setup_pump()
1328 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL); setup_pump()
1334 struct IsdnCardState *cs = bcs->cs; setup_sart() local
1340 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0, setup_sart()
1344 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2, setup_sart()
1349 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1, setup_sart()
1356 sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2, setup_sart()
1364 sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL); setup_sart()
1370 struct IsdnCardState *cs = bcs->cs; setup_iom2() local
1390 sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg); setup_iom2()
1392 sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL); setup_iom2()
1399 struct IsdnCardState *cs = bcs->cs; modeisar() local
1432 debugl1(cs, "isar modeisar analog functions only with DP1"); modeisar()
1438 if (cs->debug & L1_DEB_HSCX) modeisar()
1439 debugl1(cs, "isar dp%d mode %d->%d ichan %d", modeisar()
1459 struct IsdnCardState *cs = bcs->cs; isar_pump_cmd() local
1567 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1); isar_pump_cmd()
1571 isar_setup(struct IsdnCardState *cs) isar_setup() argument
1580 sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) | isar_setup()
1582 cs->bcs[i].hw.isar.mml = msg; isar_setup()
1583 cs->bcs[i].mode = 0; isar_setup()
1584 cs->bcs[i].hw.isar.dpath = i + 1; isar_setup()
1585 modeisar(&cs->bcs[i], 0, 0); isar_setup()
1586 INIT_WORK(&cs->bcs[i].tqueue, isar_bh); isar_setup()
1600 spin_lock_irqsave(&bcs->cs->lock, flags); isar_l2l1()
1606 if (bcs->cs->debug & L1_DEB_HSCX) isar_l2l1()
1607 debugl1(bcs->cs, "DRQ set BC_FLG_BUSY"); isar_l2l1()
1609 bcs->cs->BC_Send_Data(bcs); isar_l2l1()
1611 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1614 spin_lock_irqsave(&bcs->cs->lock, flags); isar_l2l1()
1619 if (bcs->cs->debug & L1_DEB_HSCX) isar_l2l1()
1620 debugl1(bcs->cs, "PUI set BC_FLG_BUSY"); isar_l2l1()
1623 bcs->cs->BC_Send_Data(bcs); isar_l2l1()
1625 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1635 spin_lock_irqsave(&bcs->cs->lock, flags); isar_l2l1()
1646 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1655 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1660 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1668 spin_lock_irqsave(&bcs->cs->lock, flags); isar_l2l1()
1680 if (bcs->cs->debug & L1_DEB_HSCX) isar_l2l1()
1681 debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY"); isar_l2l1()
1683 spin_unlock_irqrestore(&bcs->cs->lock, flags); isar_l2l1()
1702 if (bcs->cs->debug & L1_DEB_HSCX) close_isarstate()
1703 debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY"); close_isarstate()
1710 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs) open_isarstate() argument
1723 if (cs->debug & L1_DEB_HSCX) open_isarstate()
1724 debugl1(cs, "openisar clear BC_FLG_BUSY"); open_isarstate()
1746 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) { isar_auxcmd() argument
1751 if (cs->debug & L1_DEB_HSCX) isar_auxcmd()
1752 debugl1(cs, "isar_auxcmd cmd/ch %x/%ld", ic->command, ic->arg); isar_auxcmd()
1755 bcs = cs->channel[ic->arg].bcs; isar_auxcmd()
1756 if (cs->debug & L1_DEB_HSCX) isar_auxcmd()
1757 debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d", isar_auxcmd()
1769 cs->iif.statcallb(ic); isar_auxcmd()
1775 cs->iif.statcallb(ic); isar_auxcmd()
1778 if (cs->debug & L1_DEB_HSCX) isar_auxcmd()
1779 debugl1(cs, "isar_auxcmd %s=%d", isar_auxcmd()
1785 cs->iif.statcallb(ic); isar_auxcmd()
1796 if (cs->debug) isar_auxcmd()
1797 debugl1(cs, "isar FTS=%d and FTI busy", isar_auxcmd()
1801 if (cs->debug) isar_auxcmd()
1802 debugl1(cs, "isar FTS=%d and isar.state not ready(%x)", isar_auxcmd()
1807 cs->iif.statcallb(ic); isar_auxcmd()
1819 cs->iif.statcallb(ic); isar_auxcmd()
1830 cs->iif.statcallb(ic); isar_auxcmd()
1833 if (cs->debug & L1_DEB_HSCX) isar_auxcmd()
1834 debugl1(cs, "isar_auxcmd %s=%d", isar_auxcmd()
1852 cs->iif.statcallb(ic); isar_auxcmd()
1862 if (isar_load_firmware(cs, (u_char __user *)adr)) isar_auxcmd()
1865 ll_run(cs, features); isar_auxcmd()
1899 void initisar(struct IsdnCardState *cs) initisar() argument
1901 cs->bcs[0].BC_SetStack = setstack_isar; initisar()
1902 cs->bcs[1].BC_SetStack = setstack_isar; initisar()
1903 cs->bcs[0].BC_Close = close_isarstate; initisar()
1904 cs->bcs[1].BC_Close = close_isarstate; initisar()
1905 cs->bcs[0].hw.isar.ftimer.function = (void *) ftimer_handler; initisar()
1906 cs->bcs[0].hw.isar.ftimer.data = (long) &cs->bcs[0]; initisar()
1907 init_timer(&cs->bcs[0].hw.isar.ftimer); initisar()
1908 cs->bcs[1].hw.isar.ftimer.function = (void *) ftimer_handler; initisar()
1909 cs->bcs[1].hw.isar.ftimer.data = (long) &cs->bcs[1]; initisar()
1910 init_timer(&cs->bcs[1].hw.isar.ftimer); initisar()
|
| H A D | netjet.c | 31 NETjet_ReadIC(struct IsdnCardState *cs, u_char offset) NETjet_ReadIC() argument
35 cs->hw.njet.auxd &= 0xfc; NETjet_ReadIC()
36 cs->hw.njet.auxd |= (offset >> 4) & 3; NETjet_ReadIC()
37 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_ReadIC()
38 ret = bytein(cs->hw.njet.isac + ((offset & 0xf) << 2)); NETjet_ReadIC()
43 NETjet_WriteIC(struct IsdnCardState *cs, u_char offset, u_char value) NETjet_WriteIC() argument
45 cs->hw.njet.auxd &= 0xfc; NETjet_WriteIC()
46 cs->hw.njet.auxd |= (offset >> 4) & 3; NETjet_WriteIC()
47 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_WriteIC()
48 byteout(cs->hw.njet.isac + ((offset & 0xf) << 2), value); NETjet_WriteIC()
52 NETjet_ReadICfifo(struct IsdnCardState *cs, u_char *data, int size) NETjet_ReadICfifo() argument
54 cs->hw.njet.auxd &= 0xfc; NETjet_ReadICfifo()
55 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_ReadICfifo()
56 insb(cs->hw.njet.isac, data, size); NETjet_ReadICfifo()
60 NETjet_WriteICfifo(struct IsdnCardState *cs, u_char *data, int size) NETjet_WriteICfifo() argument
62 cs->hw.njet.auxd &= 0xfc; NETjet_WriteICfifo()
63 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); NETjet_WriteICfifo()
64 outsb(cs->hw.njet.isac, data, size); NETjet_WriteICfifo()
89 struct IsdnCardState *cs = bcs->cs; mode_tiger() local
92 if (cs->debug & L1_DEB_HSCX) mode_tiger()
93 debugl1(cs, "Tiger mode %d bchan %d/%d", mode_tiger()
101 if (cs->debug & L1_DEB_HSCX) mode_tiger()
102 debugl1(cs, "Tiger stat rec %d/%d send %d", mode_tiger()
105 if ((cs->bcs[0].mode == L1_MODE_NULL) && mode_tiger()
106 (cs->bcs[1].mode == L1_MODE_NULL)) { mode_tiger()
107 cs->hw.njet.dmactrl = 0; mode_tiger()
108 byteout(cs->hw.njet.base + NETJET_DMACTRL, mode_tiger()
109 cs->hw.njet.dmactrl); mode_tiger()
110 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0); mode_tiger()
112 if (cs->typ == ISDN_CTYPE_NETJET_S) mode_tiger()
118 cs->hw.njet.auxd &= led; mode_tiger()
119 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); mode_tiger()
134 if (!cs->hw.njet.dmactrl) { mode_tiger()
137 cs->hw.njet.dmactrl = 1; mode_tiger()
138 byteout(cs->hw.njet.base + NETJET_DMACTRL, mode_tiger()
139 cs->hw.njet.dmactrl); mode_tiger()
140 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0x0f); mode_tiger()
146 if (cs->typ == ISDN_CTYPE_NETJET_S) mode_tiger()
151 cs->hw.njet.auxd |= led; mode_tiger()
152 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); mode_tiger()
156 if (cs->debug & L1_DEB_HSCX) mode_tiger()
157 debugl1(cs, "tiger: set %x %x %x %x/%x pulse=%d", mode_tiger()
158 bytein(cs->hw.njet.base + NETJET_DMACTRL), mode_tiger()
159 bytein(cs->hw.njet.base + NETJET_IRQMASK0), mode_tiger()
160 bytein(cs->hw.njet.base + NETJET_IRQSTAT0), mode_tiger()
161 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR), mode_tiger()
162 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR), mode_tiger()
163 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); mode_tiger()
166 static void printframe(struct IsdnCardState *cs, u_char *buf, int count, char *s) { printframe() argument
179 debugl1(cs, "%s", tmp); printframe()
227 debugl1(bcs->cs, "tiger make_raw: NULL skb"); make_raw_data()
256 if (bcs->cs->debug & L1_DEB_HSCX) make_raw_data()
257 debugl1(bcs->cs, "tiger make_raw: in %u out %d.%d", make_raw_data()
317 debugl1(bcs->cs, "tiger make_raw_56k: NULL skb"); make_raw_data_56k()
363 if (bcs->cs->debug & L1_DEB_HSCX) make_raw_data_56k()
364 debugl1(bcs->cs, "tiger make_raw_56k: in %u out %d.%d", make_raw_data_56k()
392 if (bcs->cs->debug & L1_DEB_RECEIVE_FRAME) got_frame()
393 printframe(bcs->cs, bcs->hw.tiger.rcvbuf, count, "rec"); got_frame()
438 if (bcs->cs->debug & L1_DEB_HSCX) read_raw()
439 debugl1(bcs->cs, "tiger read_raw: zBit(%d,%d,%d) %x", read_raw()
453 if (bcs->cs->debug & L1_DEB_HSCX) read_raw()
454 debugl1(bcs->cs, "tiger read_raw: flag(%d,%d,%d) %x", read_raw()
489 if (bcs->cs->debug & L1_DEB_HSCX) read_raw()
490 debugl1(bcs->cs, "tiger read_raw: byte1(%d,%d,%d) rval %x val %x i %x", read_raw()
492 bcs->cs->hw.njet.irqstat0); read_raw()
511 debugl1(bcs->cs, "tiger: frame not byte aligned"); read_raw()
518 if (bcs->cs->debug & L1_DEB_HSCX) read_raw()
519 debugl1(bcs->cs, "tiger frame end(%d,%d): fcs(%x) i %x", read_raw()
520 i, j, bcs->hw.tiger.r_fcs, bcs->cs->hw.njet.irqstat0); read_raw()
524 if (bcs->cs->debug) { read_raw()
525 debugl1(bcs->cs, "tiger FCS error"); read_raw()
526 printframe(bcs->cs, bcs->hw.tiger.rcvbuf, read_raw()
551 debugl1(bcs->cs, "tiger: frame too big"); read_raw()
575 void read_tiger(struct IsdnCardState *cs) { read_tiger() argument
579 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_READ) { read_tiger()
580 debugl1(cs, "tiger warn read double dma %x/%x", read_tiger()
581 cs->hw.njet.irqstat0, cs->hw.njet.last_is0); read_tiger()
583 if (cs->bcs[0].mode) read_tiger()
584 cs->bcs[0].err_rdo++; read_tiger()
585 if (cs->bcs[1].mode) read_tiger()
586 cs->bcs[1].err_rdo++; read_tiger()
590 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_READ; read_tiger()
591 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ); read_tiger()
593 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_READ_1) read_tiger()
594 p = cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1; read_tiger()
596 p = cs->bcs[0].hw.tiger.rec + cnt - 1; read_tiger()
597 if ((cs->bcs[0].mode == L1_MODE_HDLC) || (cs->bcs[0].mode == L1_MODE_HDLC_56K)) read_tiger()
598 read_raw(cs->bcs, p, cnt); read_tiger()
600 if ((cs->bcs[1].mode == L1_MODE_HDLC) || (cs->bcs[1].mode == L1_MODE_HDLC_56K)) read_tiger()
601 read_raw(cs->bcs + 1, p, cnt); read_tiger()
602 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_READ; read_tiger()
614 if (bcs->cs->debug & L1_DEB_HSCX) netjet_fill_dma()
615 debugl1(bcs->cs, "tiger fill_dma1: c%d %4lx", bcs->channel, netjet_fill_dma()
627 if (bcs->cs->debug & L1_DEB_HSCX) netjet_fill_dma()
628 debugl1(bcs->cs, "tiger fill_dma2: c%d %4lx", bcs->channel, netjet_fill_dma()
633 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR)); netjet_fill_dma()
654 p = bus_to_virt(inl(bcs->cs->hw.njet.base + NETJET_DMA_READ_ADR)); netjet_fill_dma()
669 if (bcs->cs->debug & L1_DEB_HSCX) netjet_fill_dma()
670 debugl1(bcs->cs, "tiger fill_dma3: c%d %4lx", bcs->channel, netjet_fill_dma()
701 if (bcs->cs->debug & L1_DEB_HSCX) write_raw()
702 debugl1(bcs->cs, "tiger write_raw: c%d %p-%p %d/%d %d %x", bcs->channel, write_raw()
704 bcs->hw.tiger.sendcnt, bcs->cs->hw.njet.irqstat0); write_raw()
705 if (bcs->cs->debug & L1_DEB_HSCX_FIFO) write_raw()
706 printframe(bcs->cs, bcs->hw.tiger.sp, s_cnt, "snd"); write_raw()
711 debugl1(bcs->cs, "tiger write_raw: NULL skb s_cnt %d", s_cnt); write_raw()
742 if (bcs->cs->debug & L1_DEB_HSCX) write_raw()
743 debugl1(bcs->cs, "tiger write_raw: fill rest %d", write_raw()
754 if (bcs->cs->debug & L1_DEB_HSCX) write_raw()
755 debugl1(bcs->cs, "tiger write_raw: fill half"); write_raw()
759 if (bcs->cs->debug & L1_DEB_HSCX) write_raw()
760 debugl1(bcs->cs, "tiger write_raw: fill full"); write_raw()
764 void write_tiger(struct IsdnCardState *cs) { write_tiger() argument
767 if ((cs->hw.njet.irqstat0 & cs->hw.njet.last_is0) & NETJET_IRQM0_WRITE) { write_tiger()
768 debugl1(cs, "tiger warn write double dma %x/%x", write_tiger()
769 cs->hw.njet.irqstat0, cs->hw.njet.last_is0); write_tiger()
771 if (cs->bcs[0].mode) write_tiger()
772 cs->bcs[0].err_tx++; write_tiger()
773 if (cs->bcs[1].mode) write_tiger()
774 cs->bcs[1].err_tx++; write_tiger()
778 cs->hw.njet.last_is0 &= ~NETJET_IRQM0_WRITE; write_tiger()
779 cs->hw.njet.last_is0 |= (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE); write_tiger()
781 if (cs->hw.njet.irqstat0 & NETJET_IRQM0_WRITE_1) write_tiger()
782 p = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1; write_tiger()
784 p = cs->bcs[0].hw.tiger.send + cnt - 1; write_tiger()
785 if ((cs->bcs[0].mode == L1_MODE_HDLC) || (cs->bcs[0].mode == L1_MODE_HDLC_56K)) write_tiger()
786 write_raw(cs->bcs, p, cnt); write_tiger()
787 if ((cs->bcs[1].mode == L1_MODE_HDLC) || (cs->bcs[1].mode == L1_MODE_HDLC_56K)) write_tiger()
788 write_raw(cs->bcs + 1, p, cnt); write_tiger()
789 cs->hw.njet.irqstat0 &= ~NETJET_IRQM0_WRITE; write_tiger()
801 spin_lock_irqsave(&bcs->cs->lock, flags); tiger_l2l1()
806 bcs->cs->BC_Send_Data(bcs); tiger_l2l1()
808 spin_unlock_irqrestore(&bcs->cs->lock, flags); tiger_l2l1()
811 spin_lock_irqsave(&bcs->cs->lock, flags); tiger_l2l1()
816 bcs->cs->BC_Send_Data(bcs); tiger_l2l1()
818 spin_unlock_irqrestore(&bcs->cs->lock, flags); tiger_l2l1()
828 spin_lock_irqsave(&bcs->cs->lock, flags); tiger_l2l1()
832 spin_unlock_irqrestore(&bcs->cs->lock, flags); tiger_l2l1()
833 bcs->cs->cardmsg(bcs->cs, MDL_BC_ASSIGN, (void *)(&st->l1.bc)); tiger_l2l1()
838 bcs->cs->cardmsg(bcs->cs, MDL_BC_RELEASE, (void *)(&st->l1.bc)); tiger_l2l1()
842 spin_lock_irqsave(&bcs->cs->lock, flags); tiger_l2l1()
846 spin_unlock_irqrestore(&bcs->cs->lock, flags); tiger_l2l1()
873 open_tigerstate(struct IsdnCardState *cs, struct BCState *bcs) open_tigerstate() argument
913 inittiger(struct IsdnCardState *cs) inittiger() argument
915 if (!(cs->bcs[0].hw.tiger.send = kmalloc(NETJET_DMA_TXSIZE * sizeof(unsigned int), inittiger()
921 cs->bcs[0].hw.tiger.s_irq = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE / 2 - 1; inittiger()
922 cs->bcs[0].hw.tiger.s_end = cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1; inittiger()
923 cs->bcs[1].hw.tiger.send = cs->bcs[0].hw.tiger.send; inittiger()
924 cs->bcs[1].hw.tiger.s_irq = cs->bcs[0].hw.tiger.s_irq; inittiger()
925 cs->bcs[1].hw.tiger.s_end = cs->bcs[0].hw.tiger.s_end; inittiger()
927 memset(cs->bcs[0].hw.tiger.send, 0xff, NETJET_DMA_TXSIZE * sizeof(unsigned int)); inittiger()
928 debugl1(cs, "tiger: send buf %p - %p", cs->bcs[0].hw.tiger.send, inittiger()
929 cs->bcs[0].hw.tiger.send + NETJET_DMA_TXSIZE - 1); inittiger()
930 outl(virt_to_bus(cs->bcs[0].hw.tiger.send), inittiger()
931 cs->hw.njet.base + NETJET_DMA_READ_START); inittiger()
932 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_irq), inittiger()
933 cs->hw.njet.base + NETJET_DMA_READ_IRQ); inittiger()
934 outl(virt_to_bus(cs->bcs[0].hw.tiger.s_end), inittiger()
935 cs->hw.njet.base + NETJET_DMA_READ_END); inittiger()
936 if (!(cs->bcs[0].hw.tiger.rec = kmalloc(NETJET_DMA_RXSIZE * sizeof(unsigned int), inittiger()
942 debugl1(cs, "tiger: rec buf %p - %p", cs->bcs[0].hw.tiger.rec, inittiger()
943 cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1); inittiger()
944 cs->bcs[1].hw.tiger.rec = cs->bcs[0].hw.tiger.rec; inittiger()
945 memset(cs->bcs[0].hw.tiger.rec, 0xff, NETJET_DMA_RXSIZE * sizeof(unsigned int)); inittiger()
946 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec), inittiger()
947 cs->hw.njet.base + NETJET_DMA_WRITE_START); inittiger()
948 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE / 2 - 1), inittiger()
949 cs->hw.njet.base + NETJET_DMA_WRITE_IRQ); inittiger()
950 outl(virt_to_bus(cs->bcs[0].hw.tiger.rec + NETJET_DMA_RXSIZE - 1), inittiger()
951 cs->hw.njet.base + NETJET_DMA_WRITE_END); inittiger()
952 debugl1(cs, "tiger: dmacfg %x/%x pulse=%d", inittiger()
953 inl(cs->hw.njet.base + NETJET_DMA_WRITE_ADR), inittiger()
954 inl(cs->hw.njet.base + NETJET_DMA_READ_ADR), inittiger()
955 bytein(cs->hw.njet.base + NETJET_PULSE_CNT)); inittiger()
956 cs->hw.njet.last_is0 = 0; inittiger()
957 cs->bcs[0].BC_SetStack = setstack_tiger; inittiger()
958 cs->bcs[1].BC_SetStack = setstack_tiger; inittiger()
959 cs->bcs[0].BC_Close = close_tigerstate; inittiger()
960 cs->bcs[1].BC_Close = close_tigerstate; inittiger()
964 releasetiger(struct IsdnCardState *cs) releasetiger() argument
966 kfree(cs->bcs[0].hw.tiger.send); releasetiger()
967 cs->bcs[0].hw.tiger.send = NULL; releasetiger()
968 cs->bcs[1].hw.tiger.send = NULL; releasetiger()
969 kfree(cs->bcs[0].hw.tiger.rec); releasetiger()
970 cs->bcs[0].hw.tiger.rec = NULL; releasetiger()
971 cs->bcs[1].hw.tiger.rec = NULL; releasetiger()
975 release_io_netjet(struct IsdnCardState *cs) release_io_netjet() argument
977 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0); release_io_netjet()
978 byteout(cs->hw.njet.base + NETJET_IRQMASK1, 0); release_io_netjet()
979 releasetiger(cs); release_io_netjet()
980 release_region(cs->hw.njet.base, 256); release_io_netjet()
|
| H A D | config.c | 579 if (cards[i].cs) hisax_findcard()
580 if (cards[i].cs->myid == driverid) hisax_findcard()
581 return cards[i].cs; hisax_findcard()
592 if (cards[cardnr - 1].cs)
593 return cards[cardnr - 1].cs;
602 struct IsdnCardState *cs = hisax_findcard(id); HiSax_readstatus() local
604 if (cs) { HiSax_readstatus()
610 count = cs->status_end - cs->status_read + 1; HiSax_readstatus()
613 if (copy_to_user(p, cs->status_read, count)) HiSax_readstatus()
615 cs->status_read += count; HiSax_readstatus()
616 if (cs->status_read > cs->status_end) HiSax_readstatus()
617 cs->status_read = cs->status_buf; HiSax_readstatus()
625 if (copy_to_user(p, cs->status_read, cnt)) HiSax_readstatus()
628 cs->status_read += cnt % HISAX_STATUS_BUFSIZE; HiSax_readstatus()
662 void VHiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, VHiSax_putstatus() argument
673 if (!cs) { VHiSax_putstatus()
677 spin_lock_irqsave(&cs->statlock, flags); VHiSax_putstatus()
692 spin_unlock_irqrestore(&cs->statlock, flags); VHiSax_putstatus()
698 i = cs->status_end - cs->status_write + 1; VHiSax_putstatus()
702 memcpy(cs->status_write, p, i); VHiSax_putstatus()
703 cs->status_write += i; VHiSax_putstatus()
704 if (cs->status_write > cs->status_end) VHiSax_putstatus()
705 cs->status_write = cs->status_buf; VHiSax_putstatus()
708 memcpy(cs->status_write, p, len); VHiSax_putstatus()
709 cs->status_write += len; VHiSax_putstatus()
717 *cs->status_write++ = *p; VHiSax_putstatus()
718 if (cs->status_write > cs->status_end) VHiSax_putstatus()
719 cs->status_write = cs->status_buf; VHiSax_putstatus()
723 spin_unlock_irqrestore(&cs->statlock, flags); VHiSax_putstatus()
726 ic.driver = cs->myid; VHiSax_putstatus()
728 cs->iif.statcallb(&ic); VHiSax_putstatus()
732 void HiSax_putstatus(struct IsdnCardState *cs, char *head, char *fmt, ...) HiSax_putstatus() argument
737 VHiSax_putstatus(cs, head, fmt, args); HiSax_putstatus()
741 int ll_run(struct IsdnCardState *cs, int addfeatures) ll_run() argument
745 ic.driver = cs->myid; ll_run()
747 cs->iif.features |= addfeatures; ll_run()
748 cs->iif.statcallb(&ic); ll_run()
752 static void ll_stop(struct IsdnCardState *cs) ll_stop() argument
757 ic.driver = cs->myid; ll_stop()
758 cs->iif.statcallb(&ic); ll_stop()
759 // CallcFreeChan(cs); ll_stop()
762 static void ll_unload(struct IsdnCardState *cs) ll_unload() argument
767 ic.driver = cs->myid; ll_unload()
768 cs->iif.statcallb(&ic); ll_unload()
769 kfree(cs->status_buf); ll_unload()
770 cs->status_read = NULL; ll_unload()
771 cs->status_write = NULL; ll_unload()
772 cs->status_end = NULL; ll_unload()
773 kfree(cs->dlog); ll_unload()
774 cs->dlog = NULL; ll_unload()
779 struct IsdnCardState *csta = cards[cardnr].cs; closecard()
806 struct IsdnCardState *cs = dev_id; card_irq() local
807 irqreturn_t ret = cs->irq_func(intno, cs); card_irq()
810 cs->irq_cnt++; card_irq()
814 static int init_card(struct IsdnCardState *cs) init_card() argument
818 if (!cs->irq) { init_card()
819 ret = cs->cardmsg(cs, CARD_INIT, NULL); init_card()
822 irq_cnt = cs->irq_cnt = 0; init_card()
823 printk(KERN_INFO "%s: IRQ %d count %d\n", CardType[cs->typ], init_card()
824 cs->irq, irq_cnt); init_card()
825 if (request_irq(cs->irq, card_irq, cs->irq_flags, "HiSax", cs)) { init_card()
827 cs->irq); init_card()
831 cs->cardmsg(cs, CARD_INIT, NULL); init_card()
835 CardType[cs->typ], cs->irq, cs->irq_cnt); init_card()
836 if (cs->irq_cnt == irq_cnt) { init_card()
839 CardType[cs->typ], cs->irq, 4 - cnt); init_card()
841 free_irq(cs->irq, cs); init_card()
844 cs->cardmsg(cs, CARD_RESET, NULL); init_card()
848 cs->cardmsg(cs, CARD_TEST, NULL); init_card()
1028 struct IsdnCardState *cs; hisax_cs_new() local
1032 cs = kzalloc(sizeof(struct IsdnCardState), GFP_ATOMIC); hisax_cs_new()
1033 if (!cs) { hisax_cs_new()
1039 card->cs = cs; hisax_cs_new()
1040 spin_lock_init(&cs->statlock); hisax_cs_new()
1041 spin_lock_init(&cs->lock); hisax_cs_new()
1042 cs->chanlimit = 2; /* maximum B-channel number */ hisax_cs_new()
1043 cs->logecho = 0; /* No echo logging */ hisax_cs_new()
1044 cs->cardnr = cardnr; hisax_cs_new()
1045 cs->debug = L1_DEB_WARN; hisax_cs_new()
1046 cs->HW_Flags = 0; hisax_cs_new()
1047 cs->busy_flag = busy_flag; hisax_cs_new()
1048 cs->irq_flags = I4L_IRQ_FLAG; hisax_cs_new()
1051 test_and_set_bit(FLG_TWO_DCHAN, &cs->HW_Flags); hisax_cs_new()
1053 test_and_set_bit(FLG_TWO_DCHAN, &cs->HW_Flags); hisax_cs_new()
1055 cs->protocol = card->protocol; hisax_cs_new()
1062 if (!(cs->dlog = kmalloc(MAX_DLOG_SPACE, GFP_ATOMIC))) { hisax_cs_new()
1067 if (!(cs->status_buf = kmalloc(HISAX_STATUS_BUFSIZE, GFP_ATOMIC))) { hisax_cs_new()
1073 cs->stlist = NULL; hisax_cs_new()
1074 cs->status_read = cs->status_buf; hisax_cs_new()
1075 cs->status_write = cs->status_buf; hisax_cs_new()
1076 cs->status_end = cs->status_buf + HISAX_STATUS_BUFSIZE - 1; hisax_cs_new()
1077 cs->typ = card->typ; hisax_cs_new()
1079 cs->iif.owner = lockowner; hisax_cs_new()
1081 strcpy(cs->iif.id, id); hisax_cs_new()
1082 cs->iif.channels = 2; hisax_cs_new()
1083 cs->iif.maxbufsize = MAX_DATA_SIZE; hisax_cs_new()
1084 cs->iif.hl_hdrlen = MAX_HEADER_LEN; hisax_cs_new()
1085 cs->iif.features = hisax_cs_new()
1102 cs->iif.command = HiSax_command; hisax_cs_new()
1103 cs->iif.writecmd = NULL; hisax_cs_new()
1104 cs->iif.writebuf_skb = HiSax_writebuf_skb; hisax_cs_new()
1105 cs->iif.readstat = HiSax_readstatus; hisax_cs_new()
1106 register_isdn(&cs->iif); hisax_cs_new()
1107 cs->myid = cs->iif.channels; hisax_cs_new()
1109 *cs_out = cs; hisax_cs_new()
1113 kfree(cs->dlog); hisax_cs_new()
1115 kfree(cs); hisax_cs_new()
1116 card->cs = NULL; hisax_cs_new()
1122 struct IsdnCardState *cs) hisax_cs_setup()
1126 if (!(cs->rcvbuf = kmalloc(MAX_DFRAME_LEN_L1, GFP_ATOMIC))) { hisax_cs_setup()
1128 ll_unload(cs); hisax_cs_setup()
1131 cs->rcvidx = 0; hisax_cs_setup()
1132 cs->tx_skb = NULL; hisax_cs_setup()
1133 cs->tx_cnt = 0; hisax_cs_setup()
1134 cs->event = 0; hisax_cs_setup()
1136 skb_queue_head_init(&cs->rq); hisax_cs_setup()
1137 skb_queue_head_init(&cs->sq); hisax_cs_setup()
1139 init_bcstate(cs, 0); hisax_cs_setup()
1140 init_bcstate(cs, 1); hisax_cs_setup()
1149 ret = init_card(cs); hisax_cs_setup()
1156 init_tei(cs, cs->protocol); hisax_cs_setup()
1157 ret = CallcNewChan(cs); hisax_cs_setup()
1163 if (!test_bit(HW_ISAR, &cs->HW_Flags)) hisax_cs_setup()
1164 ll_run(cs, 0); hisax_cs_setup()
1169 kfree(cs); hisax_cs_setup()
1170 card->cs = NULL; hisax_cs_setup()
1179 struct IsdnCardState *cs; checkcard() local
1181 ret = hisax_cs_new(cardnr, id, card, &cs, busy_flag, lockowner); checkcard()
1191 "NONE", cs->iif.id, cs->myid); checkcard()
1195 ll_unload(cs); checkcard()
1199 ret = hisax_cs_setup(cardnr, card, cs); checkcard()
1203 kfree(cs); checkcard()
1204 card->cs = NULL; checkcard()
1271 if (cards[cardnr].cs) { HiSax_closecard()
1272 ll_stop(cards[cardnr].cs); HiSax_closecard()
1273 release_tei(cards[cardnr].cs); HiSax_closecard()
1274 CallcFreeChan(cards[cardnr].cs); HiSax_closecard()
1277 if (cards[cardnr].cs->irq) HiSax_closecard()
1278 free_irq(cards[cardnr].cs->irq, cards[cardnr].cs); HiSax_closecard()
1279 kfree((void *) cards[cardnr].cs); HiSax_closecard()
1280 cards[cardnr].cs = NULL; HiSax_closecard()
1292 struct IsdnCardState *cs = cards[cardnr].cs; HiSax_reportcard() local
1295 printk(KERN_DEBUG "HiSax: Type %s\n", CardType[cs->typ]); HiSax_reportcard()
1296 printk(KERN_DEBUG "HiSax: debuglevel %x\n", cs->debug); HiSax_reportcard()
1299 printk(KERN_DEBUG "HiSax: cs 0x%lX\n", (ulong) cs); HiSax_reportcard()
1301 cs->HW_Flags, cs->bcs[0].Flag, cs->bcs[1].Flag); HiSax_reportcard()
1303 cs->bcs[0].mode, cs->bcs[0].channel); HiSax_reportcard()
1305 cs->bcs[1].mode, cs->bcs[1].channel); HiSax_reportcard()
1308 cs->err_rx, cs->err_crc, cs->err_tx); HiSax_reportcard()
1311 cs->bcs[0].err_inv, cs->bcs[0].err_rdo, cs->bcs[0].err_crc, HiSax_reportcard()
1312 cs->bcs[0].err_tx); HiSax_reportcard()
1315 cs->bcs[1].err_inv, cs->bcs[1].err_rdo, cs->bcs[1].err_crc, HiSax_reportcard()
1316 cs->bcs[1].err_tx); HiSax_reportcard()
1318 cs->err_rx = 0; HiSax_reportcard()
1319 cs->err_crc = 0; HiSax_reportcard()
1320 cs->err_tx = 0; HiSax_reportcard()
1321 cs->bcs[0].err_inv = 0; HiSax_reportcard()
1322 cs->bcs[0].err_rdo = 0; HiSax_reportcard()
1323 cs->bcs[0].err_crc = 0; HiSax_reportcard()
1324 cs->bcs[0].err_tx = 0; HiSax_reportcard()
1325 cs->bcs[1].err_inv = 0; HiSax_reportcard()
1326 cs->bcs[1].err_rdo = 0; HiSax_reportcard()
1327 cs->bcs[1].err_crc = 0; HiSax_reportcard()
1328 cs->bcs[1].err_tx = 0; HiSax_reportcard()
1578 static int hisax_cardmsg(struct IsdnCardState *cs, int mt, void *arg);
1594 struct IsdnCardState *cs; hisax_register() local
1615 cs = cards[i].cs; hisax_register()
1616 hisax_d_if->cs = cs; hisax_register()
1617 cs->hw.hisax_d_if = hisax_d_if; hisax_register()
1618 cs->cardmsg = hisax_cardmsg; hisax_register()
1619 INIT_WORK(&cs->tqueue, hisax_bh); hisax_register()
1620 cs->channel[0].d_st->l2.l2l1 = hisax_d_l2l1; hisax_register()
1622 cs->bcs[i].BC_SetStack = hisax_bc_setstack; hisax_register()
1623 cs->bcs[i].BC_Close = hisax_bc_close; hisax_register()
1638 cards[hisax_d_if->cs->cardnr].typ = 0; hisax_unregister()
1639 HiSax_closecard(hisax_d_if->cs->cardnr); hisax_unregister()
1645 static void hisax_sched_event(struct IsdnCardState *cs, int event) hisax_sched_event() argument
1647 test_and_set_bit(event, &cs->event); hisax_sched_event()
1648 schedule_work(&cs->tqueue); hisax_sched_event()
1653 struct IsdnCardState *cs = hisax_bh() local
1658 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) hisax_bh()
1659 DChannel_proc_rcv(cs); hisax_bh()
1660 if (test_and_clear_bit(E_RCVBUFREADY, &cs->event)) hisax_bh()
1661 EChannel_proc_rcv(cs->hw.hisax_d_if); hisax_bh()
1662 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { hisax_bh()
1663 if (test_bit(0, &cs->hw.hisax_d_if->ph_state)) hisax_bh()
1667 for (st = cs->stlist; st; st = st->next) hisax_bh()
1694 struct IsdnCardState *cs = d_if->cs; hisax_d_l1l2() local
1701 hisax_sched_event(cs, D_L1STATECHANGE); hisax_d_l1l2()
1705 hisax_sched_event(cs, D_L1STATECHANGE); hisax_d_l1l2()
1708 skb_queue_tail(&cs->rq, arg); hisax_d_l1l2()
1709 hisax_sched_event(cs, D_RCVBUFREADY); hisax_d_l1l2()
1712 skb = skb_dequeue(&cs->sq); hisax_d_l1l2()
1717 clear_bit(FLG_L1_DBUSY, &cs->HW_Flags); hisax_d_l1l2()
1718 for (st = cs->stlist; st; st = st->next) { hisax_d_l1l2()
1727 hisax_sched_event(cs, E_RCVBUFREADY); hisax_d_l1l2()
1784 struct IsdnCardState *cs = st->l1.hardware; hisax_d_l2l1() local
1785 struct hisax_d_if *hisax_d_if = cs->hw.hisax_d_if; hisax_d_l2l1()
1791 if (cs->debug & DEB_DLOG_HEX) hisax_d_l2l1()
1792 LogFrame(cs, skb->data, skb->len); hisax_d_l2l1()
1793 if (cs->debug & DEB_DLOG_VERBOSE) hisax_d_l2l1()
1794 dlogframe(cs, skb, 0); hisax_d_l2l1()
1795 Logl2Frame(cs, skb, "PH_DATA_REQ", 0); hisax_d_l2l1()
1797 if (!test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags)) hisax_d_l2l1()
1800 skb_queue_tail(&cs->sq, skb); hisax_d_l2l1()
1803 if (!test_bit(FLG_L1_DBUSY, &cs->HW_Flags)) hisax_d_l2l1()
1814 static int hisax_cardmsg(struct IsdnCardState *cs, int mt, void *arg) hisax_cardmsg() argument
1854 struct IsdnCardState *cs = st->l1.hardware; hisax_bc_setstack() local
1855 struct hisax_d_if *hisax_d_if = cs->hw.hisax_d_if; hisax_bc_setstack()
1882 struct IsdnCardState *cs = d_if->cs; EChannel_proc_rcv() local
1887 if (cs->debug & DEB_DLOG_HEX) { EChannel_proc_rcv()
1888 ptr = cs->dlog; EChannel_proc_rcv()
1899 HiSax_putstatus(cs, NULL, "%s", cs->dlog); EChannel_proc_rcv()
1901 HiSax_putstatus(cs, "LogEcho: ", EChannel_proc_rcv()
1121 hisax_cs_setup(int cardnr, struct IsdnCard *card, struct IsdnCardState *cs) hisax_cs_setup() argument
|
| H A D | jade_irq.c | 14 waitforCEC(struct IsdnCardState *cs, int jade, int reg) waitforCEC() argument
18 while ((READJADE(cs, jade, jade_HDLC_STAR) & mask) && to) { waitforCEC()
28 waitforXFW(struct IsdnCardState *cs, int jade) waitforXFW() argument
34 WriteJADECMDR(struct IsdnCardState *cs, int jade, int reg, u_char data) WriteJADECMDR() argument
36 waitforCEC(cs, jade, reg); WriteJADECMDR()
37 WRITEJADE(cs, jade, reg, data); WriteJADECMDR()
46 struct IsdnCardState *cs = bcs->cs; jade_empty_fifo() local
48 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) jade_empty_fifo()
49 debugl1(cs, "jade_empty_fifo"); jade_empty_fifo()
52 if (cs->debug & L1_DEB_WARN) jade_empty_fifo()
53 debugl1(cs, "jade_empty_fifo: incoming packet too large"); jade_empty_fifo()
54 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); jade_empty_fifo()
60 READJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count); jade_empty_fifo()
61 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_RCMD, jadeRCMD_RMC); jade_empty_fifo()
62 if (cs->debug & L1_DEB_HSCX_FIFO) { jade_empty_fifo()
68 debugl1(cs, "%s", bcs->blog); jade_empty_fifo()
75 struct IsdnCardState *cs = bcs->cs; jade_fill_fifo() local
80 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) jade_fill_fifo()
81 debugl1(cs, "jade_fill_fifo"); jade_fill_fifo()
95 waitforXFW(cs, bcs->hw.hscx.hscx); jade_fill_fifo()
100 WRITEJADEFIFO(cs, bcs->hw.hscx.hscx, ptr, count); jade_fill_fifo()
101 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, more ? jadeXCMD_XF : (jadeXCMD_XF | jadeXCMD_XME)); jade_fill_fifo()
102 if (cs->debug & L1_DEB_HSCX_FIFO) { jade_fill_fifo()
108 debugl1(cs, "%s", bcs->blog); jade_fill_fifo()
114 jade_interrupt(struct IsdnCardState *cs, u_char val, u_char jade) jade_interrupt() argument
117 struct BCState *bcs = cs->bcs + jade; jade_interrupt()
127 r = READJADE(cs, i_jade, jade_HDLC_RSTA); jade_interrupt()
130 if (cs->debug & L1_DEB_WARN) jade_interrupt()
131 debugl1(cs, "JADE %s invalid frame", (jade ? "B" : "A")); jade_interrupt()
133 if (cs->debug & L1_DEB_WARN) jade_interrupt()
134 debugl1(cs, "JADE %c RDO mode=%d", 'A' + jade, bcs->mode); jade_interrupt()
136 if (cs->debug & L1_DEB_WARN) jade_interrupt()
137 debugl1(cs, "JADE %c CRC error", 'A' + jade); jade_interrupt()
138 WriteJADECMDR(cs, jade, jade_HDLC_RCMD, jadeRCMD_RMC); jade_interrupt()
140 count = READJADE(cs, i_jade, jade_HDLC_RBCL) & 0x1F; jade_interrupt()
145 if (cs->debug & L1_DEB_HSCX_FIFO) jade_interrupt()
146 debugl1(cs, "HX Frame %d", count); jade_interrupt()
203 jade_int_main(struct IsdnCardState *cs, u_char val, int jade) jade_int_main() argument
206 bcs = cs->bcs + jade; jade_int_main()
226 WriteJADECMDR(cs, bcs->hw.hscx.hscx, jade_HDLC_XCMD, jadeXCMD_XRES); jade_int_main()
227 if (cs->debug & L1_DEB_WARN) jade_int_main()
228 debugl1(cs, "JADE %c EXIR %x Lost TX", 'A' + jade, val); jade_int_main()
232 if (cs->debug & L1_DEB_HSCX) jade_int_main()
233 debugl1(cs, "JADE %c interrupt %x", 'A' + jade, val); jade_int_main()
234 jade_interrupt(cs, val, jade); jade_int_main()
|
| H A D | isdnl1.h | 25 void debugl1(struct IsdnCardState *cs, char *fmt, ...);
26 void DChannel_proc_xmt(struct IsdnCardState *cs);
27 void DChannel_proc_rcv(struct IsdnCardState *cs);
28 void l1_msg(struct IsdnCardState *cs, int pr, void *arg);
30 void Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf,
|
| H A D | arcofi.h | 25 extern int arcofi_fsm(struct IsdnCardState *cs, int event, void *data);
26 extern void init_arcofi(struct IsdnCardState *cs);
27 extern void clear_arcofi(struct IsdnCardState *cs);
|
| H A D | netjet.h | 58 u_char NETjet_ReadIC(struct IsdnCardState *cs, u_char offset);
59 void NETjet_WriteIC(struct IsdnCardState *cs, u_char offset, u_char value);
60 void NETjet_ReadICfifo(struct IsdnCardState *cs, u_char *data, int size);
61 void NETjet_WriteICfifo(struct IsdnCardState *cs, u_char *data, int size);
63 void read_tiger(struct IsdnCardState *cs);
64 void write_tiger(struct IsdnCardState *cs);
68 void inittiger(struct IsdnCardState *cs);
69 void release_io_netjet(struct IsdnCardState *cs);
|
| H A D | isdnl1.c | 130 debugl1(struct IsdnCardState *cs, char *fmt, ...) debugl1() argument
136 sprintf(tmp, "Card%d ", cs->cardnr + 1); debugl1()
137 VHiSax_putstatus(cs, tmp, fmt, args); debugl1()
146 struct IsdnCardState *cs = st->l1.hardware; l1m_debug() local
150 sprintf(tmp, "Card%d ", cs->cardnr + 1); l1m_debug()
151 VHiSax_putstatus(cs, tmp, fmt, args); l1m_debug()
156 L1activated(struct IsdnCardState *cs) L1activated() argument
160 st = cs->stlist; L1activated()
171 L1deactivated(struct IsdnCardState *cs) L1deactivated() argument
175 st = cs->stlist; L1deactivated()
177 if (test_bit(FLG_L1_DBUSY, &cs->HW_Flags)) L1deactivated()
182 test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags); L1deactivated()
186 DChannel_proc_xmt(struct IsdnCardState *cs) DChannel_proc_xmt() argument
190 if (cs->tx_skb) DChannel_proc_xmt()
193 stptr = cs->stlist; DChannel_proc_xmt()
204 DChannel_proc_rcv(struct IsdnCardState *cs) DChannel_proc_rcv() argument
207 struct PStack *stptr = cs->stlist; DChannel_proc_rcv()
213 while ((skb = skb_dequeue(&cs->rq))) { DChannel_proc_rcv()
215 if (cs->debug & L1_DEB_LAPD) DChannel_proc_rcv()
216 Logl2Frame(cs, skb, "PH_DATA", 1); DChannel_proc_rcv()
218 stptr = cs->stlist; DChannel_proc_rcv()
220 debugl1(cs, "D-channel frame too short(%d)", skb->len); DChannel_proc_rcv()
225 debugl1(cs, "D-channel frame wrong EA0/EA1"); DChannel_proc_rcv()
231 if (cs->debug & DEB_DLOG_HEX) DChannel_proc_rcv()
232 LogFrame(cs, skb->data, skb->len); DChannel_proc_rcv()
233 if (cs->debug & DEB_DLOG_VERBOSE) DChannel_proc_rcv()
234 dlogframe(cs, skb, 1); DChannel_proc_rcv()
276 debugl1(bcs->cs, "BC_BUSY Error"); BChannel_proc_xmt()
334 HiSax_addlist(struct IsdnCardState *cs, HiSax_addlist() argument
337 st->next = cs->stlist; HiSax_addlist()
338 cs->stlist = st; HiSax_addlist()
342 HiSax_rmlist(struct IsdnCardState *cs, HiSax_rmlist() argument
348 if (cs->stlist == st) HiSax_rmlist()
349 cs->stlist = st->next; HiSax_rmlist()
351 p = cs->stlist; HiSax_rmlist()
362 init_bcstate(struct IsdnCardState *cs, int bc) init_bcstate() argument
364 struct BCState *bcs = cs->bcs + bc; init_bcstate()
366 bcs->cs = cs; init_bcstate()
442 Logl2Frame(struct IsdnCardState *cs, struct sk_buff *skb, char *buf, int dir) Logl2Frame() argument
449 debugl1(cs, "Address not LAPD"); Logl2Frame()
451 debugl1(cs, "%s %s: %s%c (sapi %d, tei %d)", Logl2Frame()
803 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; dch_l2l1() local
812 if (cs->debug) dch_l2l1()
813 debugl1(cs, "PH_ACTIVATE_REQ %s", dch_l2l1()
824 debugl1(cs, "PH_TEST_LOOP B1"); dch_l2l1()
826 debugl1(cs, "PH_TEST_LOOP B2"); dch_l2l1()
828 debugl1(cs, "PH_TEST_LOOP DISABLED"); dch_l2l1()
832 if (cs->debug) dch_l2l1()
833 debugl1(cs, "dch_l2l1 msg %04X unhandled", pr); dch_l2l1()
839 l1_msg(struct IsdnCardState *cs, int pr, void *arg) { l1_msg() argument
842 st = cs->stlist; l1_msg()
869 if (cs->debug) l1_msg()
870 debugl1(cs, "%s %04X unhandled", __func__, pr); l1_msg()
890 setstack_HiSax(struct PStack *st, struct IsdnCardState *cs) setstack_HiSax() argument
892 st->l1.hardware = cs; setstack_HiSax()
893 st->protocol = cs->protocol; setstack_HiSax()
898 if (test_bit(FLG_HW_L1_UINT, &cs->HW_Flags)) { setstack_HiSax()
904 st->l1.l1m.debug = cs->debug; setstack_HiSax()
911 st->l1.stlistp = &(cs->stlist); setstack_HiSax()
913 if (cs->setstack_d) setstack_HiSax()
914 cs->setstack_d(st, cs); setstack_HiSax()
920 struct IsdnCardState *cs = st->l1.hardware; setstack_l1_B() local
924 st->l1.l1m.debug = cs->debug; setstack_l1_B()
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| H A D | hscx.h | 37 extern int HscxVersion(struct IsdnCardState *cs, char *s);
39 extern void clear_pending_hscx_ints(struct IsdnCardState *cs);
40 extern void inithscx(struct IsdnCardState *cs);
41 extern void inithscxisac(struct IsdnCardState *cs, int part);
|
| H A D | icc.h | 68 extern void ICCVersion(struct IsdnCardState *cs, char *s);
69 extern void initicc(struct IsdnCardState *cs);
70 extern void icc_interrupt(struct IsdnCardState *cs, u_char val);
71 extern void clear_pending_icc_ints(struct IsdnCardState *cs);
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| H A D | callc.c | 62 if (cards[i].cs) hisax_findcard()
63 if (cards[i].cs->myid == driverid) hisax_findcard()
64 return (cards[i].cs); hisax_findcard()
77 VHiSax_putstatus(chanp->cs, tmp, fmt, args); link_debug()
178 ic.driver = chanp->cs->myid; HL_LL()
181 chanp->cs->iif.statcallb(&ic); HL_LL()
193 ic.driver = chanp->cs->myid; lli_deliver_cause()
196 if (chanp->cs->protocol == ISDN_PTYPE_EURO) lli_deliver_cause()
202 chanp->cs->iif.statcallb(&ic); lli_deliver_cause()
212 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); lli_close()
224 chanp->cs->cardmsg(chanp->cs, MDL_INFO_SETUP, (void *) (long)chanp->chan); lli_leased_in()
228 ic.driver = chanp->cs->myid; lli_leased_in()
236 sprintf(ic.parm.setup.phone, "LEASED%d", chanp->cs->myid); lli_leased_in()
237 ret = chanp->cs->iif.statcallb(&ic); lli_leased_in()
241 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); lli_leased_in()
272 chanp->cs->cardmsg(chanp->cs, MDL_INFO_SETUP, (void *) (long)chanp->chan); lli_prep_dialout()
290 chanp->cs->cardmsg(chanp->cs, MDL_INFO_SETUP, (void *) (long)chanp->chan); lli_resume()
314 ic.driver = chanp->cs->myid; lli_go_active()
317 chanp->cs->iif.statcallb(&ic); lli_go_active()
318 chanp->cs->cardmsg(chanp->cs, MDL_INFO_CONN, (void *) (long)chanp->chan); lli_go_active()
335 chanp->cs->cardmsg(chanp->cs, MDL_INFO_SETUP, (void *) (long)chanp->chan); lli_deliver_call()
345 ic.driver = chanp->cs->myid; lli_deliver_call()
354 ret = chanp->cs->iif.statcallb(&ic); lli_deliver_call()
383 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); lli_deliver_call()
389 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); lli_deliver_call()
467 ic.driver = chanp->cs->myid; lli_leased_hup()
471 chanp->cs->iif.statcallb(&ic); lli_leased_hup()
685 ic.driver = chanp->cs->myid; lli_charge_info()
689 chanp->cs->iif.statcallb(&ic); lli_charge_info()
728 ic.driver = chanp->cs->myid; lli_failure_l()
732 chanp->cs->iif.statcallb(&ic); lli_failure_l()
735 chanp->cs->cardmsg(chanp->cs, MDL_INFO_REL, (void *) (long)chanp->chan); lli_failure_l()
878 struct IsdnCardState *cs = st->l1.hardware; selectfreechannel() local
882 if (test_bit(FLG_TWO_DCHAN, &cs->HW_Flags)) selectfreechannel()
892 while (i < ((bch) ? cs->chanlimit : (2 + MAX_WAITING_CALLS))) { selectfreechannel()
913 static void stat_redir_result(struct IsdnCardState *cs, int chan, ulong result) stat_redir_result() argument
916 ic.driver = cs->myid; stat_redir_result()
920 cs->iif.statcallb(&ic); stat_redir_result()
927 struct IsdnCardState *cs = st->l1.hardware; dchan_l3l4() local
997 stat_redir_result(cs, chanp->chan, pc->redir_result); dchan_l3l4()
1001 HiSax_putstatus(chanp->cs, "Ch", dchan_l3l4()
1037 struct IsdnCardState *cs = chanp->cs; init_d_st() local
1046 HiSax_addlist(cs, st); init_d_st()
1047 setstack_HiSax(st, cs); init_d_st()
1059 if (test_bit(FLG_TWO_DCHAN, &cs->HW_Flags)) init_d_st()
1080 VHiSax_putstatus(chanp->cs, tmp, fmt, args); callc_debug()
1090 chanp->cs = csta; init_chan()
1194 chanp->cs->iif.rcvcallb_skb(chanp->cs->myid, chanp->chan, skb); lldata_handler()
1226 chanp->cs->iif.rcvcallb_skb(chanp->cs->myid, chanp->chan, skb); lltrans_handler()
1255 ic.driver = chanp->cs->myid; lli_writewakeup()
1259 chanp->cs->iif.statcallb(&ic); lli_writewakeup()
1266 struct IsdnCardState *cs = chanp->cs; init_b_st() local
1269 st->l1.hardware = cs; init_b_st()
1374 if (test_bit(FLG_TWO_DCHAN, &chanp->cs->HW_Flags)) leased_l1l2()
1427 HiSax_putstatus(chanp->cs, "Ch", "%d CAPIMSG %s", chanp->chan, tmpbuf); capi_debug()
1456 lli_got_manufacturer(struct Channel *chanp, struct IsdnCardState *cs, capi_msg *cm) { lli_got_manufacturer() argument
1457 if ((cs->typ == ISDN_CTYPE_ELSA) || (cs->typ == ISDN_CTYPE_ELSA_PNP) || lli_got_manufacturer()
1458 (cs->typ == ISDN_CTYPE_ELSA_PCI)) { lli_got_manufacturer()
1459 if (cs->hw.elsa.MFlag) { lli_got_manufacturer()
1460 cs->cardmsg(cs, CARD_AUX_IND, cm->para); lli_got_manufacturer()
1470 set_channel_limit(struct IsdnCardState *cs, int chanmax) set_channel_limit() argument
1477 cs->chanlimit = 0; set_channel_limit()
1479 ic.driver = cs->myid; set_channel_limit()
1486 i = cs->iif.statcallb(&ic); set_channel_limit()
1489 cs->chanlimit++; set_channel_limit()
1675 HiSax_putstatus(cards[0].cs, "l1 debugging ", HiSax_command()
1684 HiSax_putstatus(cards[0].cs, "l3 debugging ", HiSax_command()
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| H A D | tei.c | 152 struct IsdnCardState *cs; tei_id_assign() local
170 cs = (struct IsdnCardState *) st->l1.hardware; tei_id_assign()
171 cs->cardmsg(cs, MDL_ASSIGN | REQUEST, NULL); tei_id_assign()
233 struct IsdnCardState *cs; tei_id_remove() local
244 cs = (struct IsdnCardState *) st->l1.hardware; tei_id_remove()
245 cs->cardmsg(cs, MDL_REMOVE | REQUEST, NULL); tei_id_remove()
267 struct IsdnCardState *cs; tei_id_req_tout() local
280 cs = (struct IsdnCardState *) st->l1.hardware; tei_id_req_tout()
281 cs->cardmsg(cs, MDL_REMOVE | REQUEST, NULL); tei_id_req_tout()
290 struct IsdnCardState *cs; tei_id_ver_tout() local
303 cs = (struct IsdnCardState *) st->l1.hardware; tei_id_ver_tout()
304 cs->cardmsg(cs, MDL_REMOVE | REQUEST, NULL); tei_id_ver_tout()
368 struct IsdnCardState *cs; tei_l2tei() local
376 cs = (struct IsdnCardState *) st->l1.hardware; tei_l2tei()
377 cs->cardmsg(cs, MDL_ASSIGN | REQUEST, NULL); tei_l2tei()
421 init_tei(struct IsdnCardState *cs, int protocol) init_tei() argument
426 release_tei(struct IsdnCardState *cs) release_tei() argument
428 struct PStack *st = cs->stlist; release_tei()
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| H A D | hfc_2bds0.h | 125 extern void init2bds0(struct IsdnCardState *cs);
126 extern void release2bds0(struct IsdnCardState *cs);
127 extern void hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val);
128 extern void set_cs_func(struct IsdnCardState *cs);
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| H A D | hfc_2bs0.h | 59 extern void inithfc(struct IsdnCardState *cs);
60 extern void releasehfc(struct IsdnCardState *cs);
|
| H A D | jade.h | 130 extern int JadeVersion(struct IsdnCardState *cs, char *s);
131 extern void clear_pending_jade_ints(struct IsdnCardState *cs);
132 extern void initjade(struct IsdnCardState *cs);
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| H A D | hisax_cfg.h | 60 IsdnCardState_t *cs; member in struct:IsdnCard
|
| H A D | hisax_if.h | 56 struct IsdnCardState *cs; member in struct:hisax_d_if
|
| H A D | isar.h | 218 extern int ISARVersion(struct IsdnCardState *cs, char *s);
219 extern void isar_int_main(struct IsdnCardState *cs);
220 extern void initisar(struct IsdnCardState *cs);
222 extern int isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic);
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| H A D | w6692.h | 21 #define READW6692BFIFO(cs, bchan, ptr, count) \
22 insb(cs->hw.w6692.iobase + W_B_RFIFO + (bchan ? 0x40 : 0), ptr, count)
24 #define WRITEW6692BFIFO(cs, bchan, ptr, count) \
25 outsb(cs->hw.w6692.iobase + W_B_XFIFO + (bchan ? 0x40 : 0), ptr, count)
|
| /linux-4.1.27/tools/build/feature/ |
| H A D | test-pthread-attr-setaffinity-np.c | 9 cpu_set_t cs; main() local
12 CPU_ZERO(&cs); main()
14 ret = pthread_attr_setaffinity_np(&thread_attr, sizeof(cs), &cs); main()
|
| /linux-4.1.27/drivers/isdn/gigaset/ |
| H A D | interface.c | 21 static int if_lock(struct cardstate *cs, int *arg) if_lock() argument
25 gig_dbg(DEBUG_IF, "%u: if_lock (%d)", cs->minor_index, cmd); if_lock()
31 *arg = cs->mstate == MS_LOCKED; if_lock()
35 if (!cmd && cs->mstate == MS_LOCKED && cs->connected) { if_lock()
36 cs->ops->set_modem_ctrl(cs, 0, TIOCM_DTR | TIOCM_RTS); if_lock()
37 cs->ops->baud_rate(cs, B115200); if_lock()
38 cs->ops->set_line_ctrl(cs, CS8); if_lock()
39 cs->control_state = TIOCM_DTR | TIOCM_RTS; if_lock()
42 cs->waiting = 1; if_lock()
43 if (!gigaset_add_event(cs, &cs->at_state, EV_IF_LOCK, if_lock()
45 cs->waiting = 0; if_lock()
48 gigaset_schedule_event(cs); if_lock()
50 wait_event(cs->waitqueue, !cs->waiting); if_lock()
52 if (cs->cmd_result >= 0) { if_lock()
53 *arg = cs->cmd_result; if_lock()
57 return cs->cmd_result; if_lock()
60 static int if_version(struct cardstate *cs, unsigned arg[4]) if_version() argument
66 gig_dbg(DEBUG_IF, "%u: if_version (%d)", cs->minor_index, cmd); if_version()
76 cs->waiting = 1; if_version()
77 if (!gigaset_add_event(cs, &cs->at_state, EV_IF_VER, if_version()
79 cs->waiting = 0; if_version()
82 gigaset_schedule_event(cs); if_version()
84 wait_event(cs->waitqueue, !cs->waiting); if_version()
86 if (cs->cmd_result >= 0) if_version()
89 return cs->cmd_result; if_version()
95 static int if_config(struct cardstate *cs, int *arg) if_config() argument
97 gig_dbg(DEBUG_IF, "%u: if_config (%d)", cs->minor_index, *arg); if_config()
102 if (cs->mstate != MS_LOCKED) if_config()
105 if (!cs->connected) { if_config()
111 return gigaset_enterconfigmode(cs); if_config()
118 struct cardstate *cs; if_open() local
123 cs = gigaset_get_cs_by_tty(tty); if_open()
124 if (!cs || !try_module_get(cs->driver->owner)) if_open()
127 if (mutex_lock_interruptible(&cs->mutex)) { if_open()
128 module_put(cs->driver->owner); if_open()
131 tty->driver_data = cs; if_open()
133 ++cs->port.count; if_open()
135 if (cs->port.count == 1) { if_open()
136 tty_port_tty_set(&cs->port, tty); if_open()
137 cs->port.low_latency = 1; if_open()
140 mutex_unlock(&cs->mutex); if_open()
146 struct cardstate *cs = tty->driver_data; if_close() local
148 if (!cs) { /* happens if we didn't find cs in open */ if_close()
153 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_close()
155 mutex_lock(&cs->mutex); if_close()
157 if (!cs->connected) if_close()
159 else if (!cs->port.count) if_close()
160 dev_warn(cs->dev, "%s: device not opened\n", __func__); if_close()
161 else if (!--cs->port.count) if_close()
162 tty_port_tty_set(&cs->port, NULL); if_close()
164 mutex_unlock(&cs->mutex); if_close()
166 module_put(cs->driver->owner); if_close()
172 struct cardstate *cs = tty->driver_data; if_ioctl() local
178 gig_dbg(DEBUG_IF, "%u: %s(0x%x)", cs->minor_index, __func__, cmd); if_ioctl()
180 if (mutex_lock_interruptible(&cs->mutex)) if_ioctl()
183 if (!cs->connected) { if_ioctl()
192 retval = if_lock(cs, &int_arg); if_ioctl()
199 retval = if_config(cs, &int_arg); if_ioctl()
210 retval = cs->ops->brkchars(cs, buf); if_ioctl()
218 retval = if_version(cs, version); if_ioctl()
231 mutex_unlock(&cs->mutex); if_ioctl()
238 struct cardstate *cs = tty->driver_data; if_tiocmget() local
241 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_tiocmget()
243 if (mutex_lock_interruptible(&cs->mutex)) if_tiocmget()
246 retval = cs->control_state & (TIOCM_RTS | TIOCM_DTR); if_tiocmget()
248 mutex_unlock(&cs->mutex); if_tiocmget()
256 struct cardstate *cs = tty->driver_data; if_tiocmset() local
261 cs->minor_index, __func__, set, clear); if_tiocmset()
263 if (mutex_lock_interruptible(&cs->mutex)) if_tiocmset()
266 if (!cs->connected) { if_tiocmset()
270 mc = (cs->control_state | set) & ~clear & (TIOCM_RTS | TIOCM_DTR); if_tiocmset()
271 retval = cs->ops->set_modem_ctrl(cs, cs->control_state, mc); if_tiocmset()
272 cs->control_state = mc; if_tiocmset()
275 mutex_unlock(&cs->mutex); if_tiocmset()
282 struct cardstate *cs = tty->driver_data; if_write() local
286 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_write()
288 if (mutex_lock_interruptible(&cs->mutex)) if_write()
291 if (!cs->connected) { if_write()
296 if (cs->mstate != MS_LOCKED) { if_write()
297 dev_warn(cs->dev, "can't write to unlocked device\n"); if_write()
309 dev_err(cs->dev, "%s: out of memory\n", __func__); if_write()
318 cb->wake_tasklet = &cs->if_wake_tasklet; if_write()
319 retval = cs->ops->write_cmd(cs, cb); if_write()
321 mutex_unlock(&cs->mutex); if_write()
327 struct cardstate *cs = tty->driver_data; if_write_room() local
330 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_write_room()
332 if (mutex_lock_interruptible(&cs->mutex)) if_write_room()
335 if (!cs->connected) { if_write_room()
338 } else if (cs->mstate != MS_LOCKED) { if_write_room()
339 dev_warn(cs->dev, "can't write to unlocked device\n"); if_write_room()
342 retval = cs->ops->write_room(cs); if_write_room()
344 mutex_unlock(&cs->mutex); if_write_room()
351 struct cardstate *cs = tty->driver_data; if_chars_in_buffer() local
354 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_chars_in_buffer()
356 mutex_lock(&cs->mutex); if_chars_in_buffer()
358 if (!cs->connected) if_chars_in_buffer()
360 else if (cs->mstate != MS_LOCKED) if_chars_in_buffer()
361 dev_warn(cs->dev, "can't write to unlocked device\n"); if_chars_in_buffer()
363 retval = cs->ops->chars_in_buffer(cs); if_chars_in_buffer()
365 mutex_unlock(&cs->mutex); if_chars_in_buffer()
372 struct cardstate *cs = tty->driver_data; if_throttle() local
374 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_throttle()
376 mutex_lock(&cs->mutex); if_throttle()
378 if (!cs->connected) if_throttle()
383 mutex_unlock(&cs->mutex); if_throttle()
388 struct cardstate *cs = tty->driver_data; if_unthrottle() local
390 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_unthrottle()
392 mutex_lock(&cs->mutex); if_unthrottle()
394 if (!cs->connected) if_unthrottle()
399 mutex_unlock(&cs->mutex); if_unthrottle()
404 struct cardstate *cs = tty->driver_data; if_set_termios() local
410 gig_dbg(DEBUG_IF, "%u: %s()", cs->minor_index, __func__); if_set_termios()
412 mutex_lock(&cs->mutex); if_set_termios()
414 if (!cs->connected) { if_set_termios()
423 cs->minor_index, iflag, cflag, old_cflag); if_set_termios()
426 control_state = cs->control_state; if_set_termios()
442 cs->minor_index, if_set_termios()
444 cs->ops->set_modem_ctrl(cs, control_state, new_state); if_set_termios()
448 cs->ops->baud_rate(cs, cflag & CBAUD); if_set_termios()
452 gig_dbg(DEBUG_IF, "%u: to B0 - drop DTR/RTS", cs->minor_index); if_set_termios()
454 cs->ops->set_modem_ctrl(cs, control_state, new_state); if_set_termios()
462 cs->ops->set_line_ctrl(cs, cflag); if_set_termios()
465 cs->control_state = control_state; if_set_termios()
468 mutex_unlock(&cs->mutex); if_set_termios()
489 struct cardstate *cs = (struct cardstate *)data; if_wake() local
491 tty_port_tty_wakeup(&cs->port); if_wake()
496 void gigaset_if_init(struct cardstate *cs) gigaset_if_init() argument
500 drv = cs->driver; gigaset_if_init()
504 tasklet_init(&cs->if_wake_tasklet, if_wake, (unsigned long) cs); gigaset_if_init()
506 mutex_lock(&cs->mutex); gigaset_if_init()
507 cs->tty_dev = tty_port_register_device(&cs->port, drv->tty, gigaset_if_init()
508 cs->minor_index, NULL); gigaset_if_init()
510 if (!IS_ERR(cs->tty_dev)) gigaset_if_init()
511 dev_set_drvdata(cs->tty_dev, cs); gigaset_if_init()
514 cs->tty_dev = NULL; gigaset_if_init()
516 mutex_unlock(&cs->mutex); gigaset_if_init()
519 void gigaset_if_free(struct cardstate *cs) gigaset_if_free() argument
523 drv = cs->driver; gigaset_if_free()
527 tasklet_disable(&cs->if_wake_tasklet); gigaset_if_free()
528 tasklet_kill(&cs->if_wake_tasklet); gigaset_if_free()
529 cs->tty_dev = NULL; gigaset_if_free()
530 tty_unregister_device(drv->tty, cs->minor_index); gigaset_if_free()
535 * @cs: device descriptor structure.
542 void gigaset_if_receive(struct cardstate *cs, gigaset_if_receive() argument
545 tty_insert_flip_string(&cs->port, buffer, len); gigaset_if_receive()
546 tty_flip_buffer_push(&cs->port); gigaset_if_receive()
|
| H A D | ev-layer.c | 407 static void add_cid_event(struct cardstate *cs, int cid, int type, add_cid_event() argument
416 spin_lock_irqsave(&cs->ev_lock, flags); add_cid_event()
418 tail = cs->ev_tail; add_cid_event()
420 if (unlikely(next == cs->ev_head)) { add_cid_event()
421 dev_err(cs->dev, "event queue full\n"); add_cid_event()
424 event = cs->events + tail; add_cid_event()
431 cs->ev_tail = next; add_cid_event()
434 spin_unlock_irqrestore(&cs->ev_lock, flags); add_cid_event()
439 * @cs: device descriptor structure.
443 * already in the cs structure.
445 void gigaset_handle_modem_response(struct cardstate *cs) gigaset_handle_modem_response() argument
453 if (!cs->cbytes) { gigaset_handle_modem_response()
455 gig_dbg(DEBUG_MCMD, "skipped EOL [%02X]", cs->respdata[0]); gigaset_handle_modem_response()
458 cs->respdata[cs->cbytes] = 0; gigaset_handle_modem_response()
460 if (cs->at_state.getstring) { gigaset_handle_modem_response()
462 cs->at_state.getstring = 0; gigaset_handle_modem_response()
463 ptr = kstrdup(cs->respdata, GFP_ATOMIC); gigaset_handle_modem_response()
465 add_cid_event(cs, 0, RSP_STRING, ptr, 0); gigaset_handle_modem_response()
471 eoc = skip_prefix(cs->respdata, rt->response); gigaset_handle_modem_response()
476 add_cid_event(cs, 0, RSP_NONE, NULL, 0); gigaset_handle_modem_response()
478 cs->respdata); gigaset_handle_modem_response()
483 psep = strrchr(cs->respdata, ';'); gigaset_handle_modem_response()
494 gig_dbg(DEBUG_EVENT, "CMD received: %s", cs->respdata); gigaset_handle_modem_response()
504 add_cid_event(cs, cid, rt->resp_code, NULL, 0); gigaset_handle_modem_response()
514 add_cid_event(cs, 0, rt->resp_code, NULL, cid); gigaset_handle_modem_response()
528 dev_warn(cs->dev, gigaset_handle_modem_response()
547 add_cid_event(cs, cid, rt->resp_code, ptr, 0); gigaset_handle_modem_response()
555 add_cid_event(cs, cid, rt->resp_code, NULL, ZSAU_NONE); gigaset_handle_modem_response()
568 add_cid_event(cs, cid, rt->resp_code, NULL, zr->code); gigaset_handle_modem_response()
580 add_cid_event(cs, cid, rt->resp_code, ptr, 0); gigaset_handle_modem_response()
599 add_cid_event(cs, cid, rt->resp_code, NULL, parameter); gigaset_handle_modem_response()
613 cs->dle = parameter; gigaset_handle_modem_response()
615 add_cid_event(cs, cid, rt->resp_code, NULL, parameter); gigaset_handle_modem_response()
620 dev_warn(cs->dev, "bad parameter in response '%s'\n", gigaset_handle_modem_response()
621 cs->respdata); gigaset_handle_modem_response()
622 add_cid_event(cs, cid, rt->resp_code, NULL, -1); gigaset_handle_modem_response()
626 dev_err(cs->dev, "%s: internal error on '%s'\n", gigaset_handle_modem_response()
627 __func__, cs->respdata); gigaset_handle_modem_response()
637 struct cardstate *cs) disconnect_nobc()
641 spin_lock_irqsave(&cs->lock, flags); disconnect_nobc()
645 if (!cs->cidmode) { disconnect_nobc()
646 cs->at_state.pending_commands |= PC_UMMODE; disconnect_nobc()
648 cs->commands_pending = 1; disconnect_nobc()
658 spin_unlock_irqrestore(&cs->lock, flags); disconnect_nobc()
666 struct cardstate *cs, struct bc_state *bcs) disconnect_bc()
670 spin_lock_irqsave(&cs->lock, flags); disconnect_bc()
674 if (!cs->cidmode) { disconnect_bc()
675 cs->at_state.pending_commands |= PC_UMMODE; disconnect_bc()
677 cs->commands_pending = 1; disconnect_bc()
679 spin_unlock_irqrestore(&cs->lock, flags); disconnect_bc()
682 cs->ops->close_bchannel(bcs); disconnect_bc()
697 static inline struct at_state_t *get_free_channel(struct cardstate *cs, get_free_channel() argument
708 for (i = 0; i < cs->channels; ++i) get_free_channel()
709 if (gigaset_get_channel(cs->bcs + i) >= 0) { get_free_channel()
710 ret = &cs->bcs[i].at_state; get_free_channel()
715 spin_lock_irqsave(&cs->lock, flags); get_free_channel()
718 gigaset_at_init(ret, NULL, cs, cid); get_free_channel()
719 list_add(&ret->list, &cs->temp_at_states); get_free_channel()
721 spin_unlock_irqrestore(&cs->lock, flags); get_free_channel()
725 static void init_failed(struct cardstate *cs, int mode) init_failed() argument
730 cs->at_state.pending_commands &= ~PC_INIT; init_failed()
731 cs->mode = mode; init_failed()
732 cs->mstate = MS_UNINITIALIZED; init_failed()
733 gigaset_free_channels(cs); init_failed()
734 for (i = 0; i < cs->channels; ++i) { init_failed()
735 at_state = &cs->bcs[i].at_state; init_failed()
739 cs->commands_pending = 1; init_failed()
744 static void schedule_init(struct cardstate *cs, int state) schedule_init() argument
746 if (cs->at_state.pending_commands & PC_INIT) { schedule_init()
750 cs->mstate = state; schedule_init()
751 cs->mode = M_UNKNOWN; schedule_init()
752 gigaset_block_channels(cs); schedule_init()
753 cs->at_state.pending_commands |= PC_INIT; schedule_init()
755 cs->commands_pending = 1; schedule_init()
761 static void send_command(struct cardstate *cs, const char *cmd, send_command() argument
771 dev_err(cs->dev, "%s: out of memory\n", __func__); send_command()
776 cs->dle ? "\020(AT%d%s\020)" : "AT%d%s", send_command()
780 cs->dle ? "\020(AT%s\020)" : "AT%s", send_command()
785 cs->ops->write_cmd(cs, cb); send_command()
788 static struct at_state_t *at_state_from_cid(struct cardstate *cs, int cid) at_state_from_cid() argument
795 return &cs->at_state; at_state_from_cid()
797 for (i = 0; i < cs->channels; ++i) at_state_from_cid()
798 if (cid == cs->bcs[i].at_state.cid) at_state_from_cid()
799 return &cs->bcs[i].at_state; at_state_from_cid()
801 spin_lock_irqsave(&cs->lock, flags); at_state_from_cid()
803 list_for_each_entry(at_state, &cs->temp_at_states, list) at_state_from_cid()
805 spin_unlock_irqrestore(&cs->lock, flags); at_state_from_cid()
809 spin_unlock_irqrestore(&cs->lock, flags); at_state_from_cid()
834 dev_notice(bcs->cs->dev, "%s: B channel already up\n", bchannel_up()
847 struct cardstate *cs = at_state->cs; start_dial() local
854 spin_lock_irqsave(&cs->lock, flags); start_dial()
856 spin_unlock_irqrestore(&cs->lock, flags); start_dial()
859 spin_unlock_irqrestore(&cs->lock, flags); start_dial()
868 cs->commands_pending = 1; start_dial()
878 cs->commands_pending = 1; start_dial()
884 struct cardstate *cs = at_state->cs; start_accept() local
896 dev_err(at_state->cs->dev, "out of memory\n"); start_accept()
900 cs->commands_pending = 1; start_accept()
909 cs->commands_pending = 1; start_accept()
912 static void do_start(struct cardstate *cs) do_start() argument
914 gigaset_free_channels(cs); do_start()
916 if (cs->mstate != MS_LOCKED) do_start()
917 schedule_init(cs, MS_INIT); do_start()
919 cs->isdn_up = 1; do_start()
920 gigaset_isdn_start(cs); do_start()
922 cs->waiting = 0; do_start()
923 wake_up(&cs->waitqueue); do_start()
926 static void finish_shutdown(struct cardstate *cs) finish_shutdown() argument
928 if (cs->mstate != MS_LOCKED) { finish_shutdown()
929 cs->mstate = MS_UNINITIALIZED; finish_shutdown()
930 cs->mode = M_UNKNOWN; finish_shutdown()
934 if (cs->isdn_up) { finish_shutdown()
935 cs->isdn_up = 0; finish_shutdown()
936 gigaset_isdn_stop(cs); finish_shutdown()
941 cs->cmd_result = -ENODEV; finish_shutdown()
942 cs->waiting = 0; finish_shutdown()
943 wake_up(&cs->waitqueue); finish_shutdown()
946 static void do_shutdown(struct cardstate *cs) do_shutdown() argument
948 gigaset_block_channels(cs); do_shutdown()
950 if (cs->mstate == MS_READY) { do_shutdown()
951 cs->mstate = MS_SHUTDOWN; do_shutdown()
952 cs->at_state.pending_commands |= PC_SHUTDOWN; do_shutdown()
954 cs->commands_pending = 1; do_shutdown()
956 finish_shutdown(cs); do_shutdown()
959 static void do_stop(struct cardstate *cs) do_stop() argument
963 spin_lock_irqsave(&cs->lock, flags); do_stop()
964 cs->connected = 0; do_stop()
965 spin_unlock_irqrestore(&cs->lock, flags); do_stop()
967 do_shutdown(cs); do_stop()
978 static int reinit_and_retry(struct cardstate *cs, int channel) reinit_and_retry() argument
982 if (--cs->retry_count <= 0) reinit_and_retry()
985 for (i = 0; i < cs->channels; ++i) reinit_and_retry()
986 if (cs->bcs[i].at_state.cid > 0) reinit_and_retry()
990 dev_warn(cs->dev, reinit_and_retry()
993 dev_warn(cs->dev, reinit_and_retry()
995 cs->bcs[channel].at_state.pending_commands |= PC_CID; reinit_and_retry()
997 schedule_init(cs, MS_INIT); reinit_and_retry()
1001 static int at_state_invalid(struct cardstate *cs, at_state_invalid() argument
1009 spin_lock_irqsave(&cs->lock, flags); at_state_invalid()
1011 if (test_ptr == &cs->at_state) at_state_invalid()
1014 list_for_each_entry(at_state, &cs->temp_at_states, list) at_state_invalid()
1018 for (channel = 0; channel < cs->channels; ++channel) at_state_invalid()
1019 if (&cs->bcs[channel].at_state == test_ptr) at_state_invalid()
1024 spin_unlock_irqrestore(&cs->lock, flags); at_state_invalid()
1028 static void handle_icall(struct cardstate *cs, struct bc_state *bcs, handle_icall() argument
1038 dev_err(cs->dev, "internal error: disposition=%d\n", retval); handle_icall()
1047 cs->commands_pending = 1; handle_icall()
1052 static int do_lock(struct cardstate *cs) do_lock() argument
1057 switch (cs->mstate) { do_lock()
1060 if (cs->cur_at_seq || !list_empty(&cs->temp_at_states) || do_lock()
1061 cs->at_state.pending_commands) do_lock()
1064 for (i = 0; i < cs->channels; ++i) do_lock()
1065 if (cs->bcs[i].at_state.pending_commands) do_lock()
1068 if (gigaset_get_channels(cs) < 0) do_lock()
1078 mode = cs->mode; do_lock()
1079 cs->mstate = MS_LOCKED; do_lock()
1080 cs->mode = M_UNKNOWN; do_lock()
1085 static int do_unlock(struct cardstate *cs) do_unlock() argument
1087 if (cs->mstate != MS_LOCKED) do_unlock()
1090 cs->mstate = MS_UNINITIALIZED; do_unlock()
1091 cs->mode = M_UNKNOWN; do_unlock()
1092 gigaset_free_channels(cs); do_unlock()
1093 if (cs->connected) do_unlock()
1094 schedule_init(cs, MS_INIT); do_unlock()
1099 static void do_action(int action, struct cardstate *cs, do_action() argument
1122 cs->at_state.pending_commands &= ~PC_INIT; do_action()
1123 cs->cur_at_seq = SEQ_NONE; do_action()
1124 cs->mode = M_UNIMODEM; do_action()
1125 spin_lock_irqsave(&cs->lock, flags); do_action()
1126 if (!cs->cidmode) { do_action()
1127 spin_unlock_irqrestore(&cs->lock, flags); do_action()
1128 gigaset_free_channels(cs); do_action()
1129 cs->mstate = MS_READY; do_action()
1132 spin_unlock_irqrestore(&cs->lock, flags); do_action()
1133 cs->at_state.pending_commands |= PC_CIDMODE; do_action()
1135 cs->commands_pending = 1; do_action()
1138 dev_warn(cs->dev, "Could not initialize the device.\n"); do_action()
1139 cs->dle = 0; do_action()
1140 init_failed(cs, M_UNKNOWN); do_action()
1141 cs->cur_at_seq = SEQ_NONE; do_action()
1144 init_failed(cs, M_CONFIG); do_action()
1145 cs->cur_at_seq = SEQ_NONE; do_action()
1148 cs->dle = 1; do_action()
1149 /* cs->inbuf[0].inputstate |= INS_command | INS_DLE_command; */ do_action()
1150 cs->inbuf[0].inputstate &= do_action()
1154 cs->dle = 0; do_action()
1155 cs->inbuf[0].inputstate = do_action()
1156 (cs->inbuf[0].inputstate & ~INS_DLE_command) do_action()
1160 if (cs->mstate == MS_INIT || cs->mstate == MS_RECOVER) { do_action()
1161 gigaset_free_channels(cs); do_action()
1162 cs->mstate = MS_READY; do_action()
1164 cs->mode = M_CID; do_action()
1165 cs->cur_at_seq = SEQ_NONE; do_action()
1168 cs->mode = M_UNIMODEM; do_action()
1169 cs->cur_at_seq = SEQ_NONE; do_action()
1172 cs->cur_at_seq = SEQ_NONE; do_action()
1173 if (cs->mstate == MS_INIT || cs->mstate == MS_RECOVER) { do_action()
1174 init_failed(cs, M_UNKNOWN); do_action()
1177 if (reinit_and_retry(cs, -1) < 0) do_action()
1178 schedule_init(cs, MS_RECOVER); do_action()
1181 cs->cur_at_seq = SEQ_NONE; do_action()
1182 schedule_init(cs, MS_RECOVER); do_action()
1186 if (cs->connected) { do_action()
1191 dev_err(cs->dev, "%s: out of memory\n", do_action()
1200 cs->ops->write_cmd(cs, cb); do_action()
1205 at_state = get_free_channel(cs, ev->parameter); do_action()
1207 dev_warn(cs->dev, do_action()
1222 spin_lock_irqsave(&cs->lock, flags); do_action()
1225 spin_unlock_irqrestore(&cs->lock, flags); do_action()
1228 handle_icall(cs, bcs, at_state); do_action()
1231 dev_warn(cs->dev, "Could not shut down the device.\n"); do_action()
1235 cs->cur_at_seq = SEQ_NONE; do_action()
1236 finish_shutdown(cs); do_action()
1239 if (cs->onechannel) { do_action()
1241 cs->commands_pending = 1; do_action()
1246 cs->ops->init_bchannel(bcs); do_action()
1249 cs->cur_at_seq = SEQ_NONE; do_action()
1250 bcs = cs->bcs + cs->curchannel; do_action()
1254 cs->ops->init_bchannel(bcs); do_action()
1260 cs->cur_at_seq = SEQ_NONE; do_action()
1263 disconnect_nobc(p_at_state, cs); do_action()
1264 } else if (cs->onechannel && cs->dle) { do_action()
1269 cs->commands_pending = 1; do_action()
1271 disconnect_bc(at_state, cs, bcs); do_action()
1276 cs->dle = 0; do_action()
1279 cs->cur_at_seq = SEQ_NONE; do_action()
1280 bcs2 = cs->bcs + cs->curchannel; do_action()
1281 disconnect_bc(&bcs2->at_state, cs, bcs2); do_action()
1284 cs->cur_at_seq = SEQ_NONE; do_action()
1285 dev_warn(cs->dev, "Could not hang up.\n"); do_action()
1288 disconnect_nobc(p_at_state, cs); do_action()
1289 else if (cs->onechannel) do_action()
1292 disconnect_bc(at_state, cs, bcs); do_action()
1293 schedule_init(cs, MS_RECOVER); do_action()
1296 cs->cur_at_seq = SEQ_NONE; do_action()
1297 dev_warn(cs->dev, "Error leaving DLE mode.\n"); do_action()
1298 cs->dle = 0; do_action()
1299 bcs2 = cs->bcs + cs->curchannel; do_action()
1300 disconnect_bc(&bcs2->at_state, cs, bcs2); do_action()
1301 schedule_init(cs, MS_RECOVER); do_action()
1304 cs->cur_at_seq = SEQ_NONE; do_action()
1305 dev_warn(cs->dev, do_action()
1307 channel = cs->curchannel; do_action()
1308 cs->bcs[channel].at_state.pending_commands |= PC_HUP; do_action()
1309 cs->commands_pending = 1; do_action()
1313 cs->cur_at_seq = SEQ_NONE; do_action()
1314 channel = cs->curchannel; do_action()
1316 cs->bcs[channel].at_state.cid = ev->parameter; do_action()
1317 cs->bcs[channel].at_state.pending_commands |= do_action()
1319 cs->commands_pending = 1; do_action()
1324 cs->cur_at_seq = SEQ_NONE; do_action()
1325 channel = cs->curchannel; do_action()
1326 if (reinit_and_retry(cs, channel) < 0) { do_action()
1327 dev_warn(cs->dev, do_action()
1329 bcs2 = cs->bcs + channel; do_action()
1330 disconnect_bc(&bcs2->at_state, cs, bcs2); do_action()
1334 cs->cur_at_seq = SEQ_NONE; do_action()
1335 bcs2 = cs->bcs + cs->curchannel; do_action()
1336 disconnect_bc(&bcs2->at_state, cs, bcs2); do_action()
1341 cs->cur_at_seq = SEQ_NONE; do_action()
1346 disconnect_bc(at_state, cs, bcs); do_action()
1348 disconnect_nobc(p_at_state, cs); do_action()
1352 cs->cur_at_seq = SEQ_NONE; do_action()
1354 cs->commands_pending = 1; do_action()
1361 cs->commands_pending = 1; do_action()
1393 cs->fwver[i] = val; do_action()
1400 cs->gotfwver = 0; do_action()
1403 if (cs->gotfwver == 0) { do_action()
1404 cs->gotfwver = 1; do_action()
1407 cs->fwver[0], cs->fwver[1], do_action()
1408 cs->fwver[2], cs->fwver[3]); do_action()
1413 cs->gotfwver = -1; do_action()
1414 dev_err(cs->dev, "could not read firmware version.\n"); do_action()
1419 cs->cur_at_seq = SEQ_NONE; do_action()
1426 dev_warn(cs->dev, "%s: resp_code %d in ConState %d!\n", do_action()
1430 dev_warn(cs->dev, "cause code %04x in connection state %d.\n", do_action()
1450 cs->commands_pending = 1; do_action()
1456 do_stop(cs); do_action()
1459 do_start(cs); do_action()
1465 cs->cmd_result = ev->parameter ? do_lock(cs) : do_unlock(cs); do_action()
1466 cs->waiting = 0; do_action()
1467 wake_up(&cs->waitqueue); do_action()
1471 cs->cmd_result = -EINVAL; do_action()
1472 else if (cs->gotfwver != 1) { do_action()
1473 cs->cmd_result = -ENOENT; do_action()
1475 memcpy(ev->arg, cs->fwver, sizeof cs->fwver); do_action()
1476 cs->cmd_result = 0; do_action()
1478 cs->waiting = 0; do_action()
1479 wake_up(&cs->waitqueue); do_action()
1485 spin_lock_irqsave(&cs->lock, flags); do_action()
1486 if (ev->parameter != cs->cidmode) { do_action()
1487 cs->cidmode = ev->parameter; do_action()
1489 cs->at_state.pending_commands |= PC_CIDMODE; do_action()
1492 cs->at_state.pending_commands |= PC_UMMODE; do_action()
1495 cs->commands_pending = 1; do_action()
1497 spin_unlock_irqrestore(&cs->lock, flags); do_action()
1498 cs->waiting = 0; do_action()
1499 wake_up(&cs->waitqueue); do_action()
1511 do_shutdown(cs); do_action()
1523 dev_err(cs->dev, "%s: action==%d!\n", __func__, action); do_action()
1528 static void process_event(struct cardstate *cs, struct event_t *ev) process_event() argument
1542 at_state = at_state_from_cid(cs, ev->cid); process_event()
1546 gigaset_add_event(cs, &cs->at_state, RSP_WRONG_CID, process_event()
1552 if (at_state_invalid(cs, at_state)) { process_event()
1567 spin_lock_irqsave(&cs->lock, flags); process_event()
1580 spin_unlock_irqrestore(&cs->lock, flags); process_event()
1604 dev_warn(cs->dev, "%s: rcode=RSP_LAST: " process_event()
1623 do_action(rep->action[curact], cs, bcs, &at_state, &p_command, process_event()
1635 spin_lock_irqsave(&cs->lock, flags); process_event()
1638 spin_unlock_irqrestore(&cs->lock, flags); process_event()
1639 gigaset_add_event(cs, at_state, resp_code, NULL, 0, NULL); process_event()
1643 if (cs->connected) process_event()
1644 send_command(cs, p_command, at_state); process_event()
1646 gigaset_add_event(cs, at_state, RSP_NODEV, process_event()
1650 spin_lock_irqsave(&cs->lock, flags); process_event()
1659 spin_unlock_irqrestore(&cs->lock, flags); process_event()
1663 static void schedule_sequence(struct cardstate *cs, schedule_sequence() argument
1666 cs->cur_at_seq = sequence; schedule_sequence()
1667 gigaset_add_event(cs, at_state, RSP_INIT, NULL, sequence, NULL); schedule_sequence()
1670 static void process_command_flags(struct cardstate *cs) process_command_flags() argument
1678 cs->commands_pending = 0; process_command_flags()
1680 if (cs->cur_at_seq) { process_command_flags()
1690 if (cs->at_state.pending_commands & PC_SHUTDOWN) { process_command_flags()
1691 cs->at_state.pending_commands &= ~PC_CIDMODE; process_command_flags()
1692 for (i = 0; i < cs->channels; ++i) { process_command_flags()
1693 bcs = cs->bcs + i; process_command_flags()
1707 if (cs->at_state.pending_commands & PC_INIT) { process_command_flags()
1708 cs->at_state.pending_commands &= ~PC_CIDMODE; process_command_flags()
1709 for (i = 0; i < cs->channels; ++i) { process_command_flags()
1710 bcs = cs->bcs + i; process_command_flags()
1716 if (cs->mstate == MS_RECOVER) { process_command_flags()
1727 spin_lock_irqsave(&cs->lock, flags); process_command_flags()
1728 if (cs->at_state.pending_commands == PC_UMMODE process_command_flags()
1729 && !cs->cidmode process_command_flags()
1730 && list_empty(&cs->temp_at_states) process_command_flags()
1731 && cs->mode == M_CID) { process_command_flags()
1733 at_state = &cs->at_state; process_command_flags()
1734 for (i = 0; i < cs->channels; ++i) { process_command_flags()
1735 bcs = cs->bcs + i; process_command_flags()
1743 spin_unlock_irqrestore(&cs->lock, flags); process_command_flags()
1744 cs->at_state.pending_commands &= ~PC_UMMODE; process_command_flags()
1746 schedule_sequence(cs, at_state, sequence); process_command_flags()
1750 for (i = 0; i < cs->channels; ++i) { process_command_flags()
1751 bcs = cs->bcs + i; process_command_flags()
1753 if (cs->dle) { process_command_flags()
1754 cs->curchannel = bcs->channel; process_command_flags()
1755 schedule_sequence(cs, &cs->at_state, SEQ_DLE0); process_command_flags()
1764 schedule_sequence(cs, &bcs->at_state, SEQ_HUP); process_command_flags()
1770 cs->curchannel = bcs->channel; process_command_flags()
1771 schedule_sequence(cs, &cs->at_state, SEQ_NOCID); process_command_flags()
1775 cs->curchannel = bcs->channel; process_command_flags()
1776 schedule_sequence(cs, &cs->at_state, SEQ_DLE0); process_command_flags()
1781 list_for_each_entry(at_state, &cs->temp_at_states, list) process_command_flags()
1784 schedule_sequence(cs, at_state, SEQ_HUP); process_command_flags()
1788 if (cs->at_state.pending_commands & PC_INIT) { process_command_flags()
1789 cs->at_state.pending_commands &= ~PC_INIT; process_command_flags()
1790 cs->dle = 0; process_command_flags()
1791 cs->inbuf->inputstate = INS_command; process_command_flags()
1792 schedule_sequence(cs, &cs->at_state, SEQ_INIT); process_command_flags()
1795 if (cs->at_state.pending_commands & PC_SHUTDOWN) { process_command_flags()
1796 cs->at_state.pending_commands &= ~PC_SHUTDOWN; process_command_flags()
1797 schedule_sequence(cs, &cs->at_state, SEQ_SHUTDOWN); process_command_flags()
1800 if (cs->at_state.pending_commands & PC_CIDMODE) { process_command_flags()
1801 cs->at_state.pending_commands &= ~PC_CIDMODE; process_command_flags()
1802 if (cs->mode == M_UNIMODEM) { process_command_flags()
1803 cs->retry_count = 1; process_command_flags()
1804 schedule_sequence(cs, &cs->at_state, SEQ_CIDMODE); process_command_flags()
1809 for (i = 0; i < cs->channels; ++i) { process_command_flags()
1810 bcs = cs->bcs + i; process_command_flags()
1813 cs->curchannel = bcs->channel; process_command_flags()
1814 schedule_sequence(cs, &cs->at_state, SEQ_DLE1); process_command_flags()
1819 schedule_sequence(cs, &bcs->at_state, SEQ_ACCEPT); process_command_flags()
1824 schedule_sequence(cs, &bcs->at_state, SEQ_DIAL); process_command_flags()
1828 switch (cs->mode) { process_command_flags()
1830 cs->at_state.pending_commands |= PC_CIDMODE; process_command_flags()
1832 cs->commands_pending = 1; process_command_flags()
1835 schedule_init(cs, MS_INIT); process_command_flags()
1839 cs->curchannel = bcs->channel; process_command_flags()
1840 cs->retry_count = 2; process_command_flags()
1841 schedule_sequence(cs, &cs->at_state, SEQ_CID); process_command_flags()
1847 static void process_events(struct cardstate *cs) process_events() argument
1856 spin_lock_irqsave(&cs->ev_lock, flags); process_events()
1857 head = cs->ev_head; process_events()
1860 tail = cs->ev_tail; process_events()
1862 if (!check_flags && !cs->commands_pending) process_events()
1865 spin_unlock_irqrestore(&cs->ev_lock, flags); process_events()
1866 process_command_flags(cs); process_events()
1867 spin_lock_irqsave(&cs->ev_lock, flags); process_events()
1868 tail = cs->ev_tail; process_events()
1870 if (!cs->commands_pending) process_events()
1876 ev = cs->events + head; process_events()
1877 was_busy = cs->cur_at_seq != SEQ_NONE; process_events()
1878 spin_unlock_irqrestore(&cs->ev_lock, flags); process_events()
1879 process_event(cs, ev); process_events()
1880 spin_lock_irqsave(&cs->ev_lock, flags); process_events()
1883 if (was_busy && cs->cur_at_seq == SEQ_NONE) process_events()
1887 cs->ev_head = head; process_events()
1890 spin_unlock_irqrestore(&cs->ev_lock, flags); process_events()
1893 dev_err(cs->dev, process_events()
1904 struct cardstate *cs = (struct cardstate *) data; gigaset_handle_event() local
1907 if (cs->inbuf->head != cs->inbuf->tail) { gigaset_handle_event()
1909 cs->ops->handle_input(cs->inbuf); gigaset_handle_event()
1912 process_events(cs); gigaset_handle_event()
636 disconnect_nobc(struct at_state_t **at_state_p, struct cardstate *cs) disconnect_nobc() argument
665 disconnect_bc(struct at_state_t *at_state, struct cardstate *cs, struct bc_state *bcs) disconnect_bc() argument
|
| H A D | common.c | 89 static int setflags(struct cardstate *cs, unsigned flags, unsigned delay) setflags() argument
93 r = cs->ops->set_modem_ctrl(cs, cs->control_state, flags); setflags()
94 cs->control_state = flags; setflags()
106 int gigaset_enterconfigmode(struct cardstate *cs) gigaset_enterconfigmode() argument
110 cs->control_state = TIOCM_RTS; gigaset_enterconfigmode()
112 r = setflags(cs, TIOCM_DTR, 200); gigaset_enterconfigmode()
115 r = setflags(cs, 0, 200); gigaset_enterconfigmode()
119 r = setflags(cs, TIOCM_RTS, 100); gigaset_enterconfigmode()
122 r = setflags(cs, 0, 100); gigaset_enterconfigmode()
126 r = setflags(cs, TIOCM_RTS | TIOCM_DTR, 800); gigaset_enterconfigmode()
133 dev_err(cs->dev, "error %d on setuartbits\n", -r); gigaset_enterconfigmode()
134 cs->control_state = TIOCM_RTS | TIOCM_DTR; gigaset_enterconfigmode()
135 cs->ops->set_modem_ctrl(cs, 0, TIOCM_RTS | TIOCM_DTR); gigaset_enterconfigmode()
151 gigaset_add_event(at_state->cs, at_state, EV_TIMEOUT, NULL, test_timeout()
158 struct cardstate *cs = (struct cardstate *) data; timer_tick() local
164 spin_lock_irqsave(&cs->lock, flags); timer_tick()
166 for (channel = 0; channel < cs->channels; ++channel) timer_tick()
167 if (test_timeout(&cs->bcs[channel].at_state)) timer_tick()
170 if (test_timeout(&cs->at_state)) timer_tick()
173 list_for_each_entry(at_state, &cs->temp_at_states, list) timer_tick()
177 if (cs->running) { timer_tick()
178 mod_timer(&cs->timer, jiffies + msecs_to_jiffies(GIG_TICK)); timer_tick()
181 tasklet_schedule(&cs->event_tasklet); timer_tick()
185 spin_unlock_irqrestore(&cs->lock, flags); timer_tick()
192 spin_lock_irqsave(&bcs->cs->lock, flags); gigaset_get_channel()
193 if (bcs->use_count || !try_module_get(bcs->cs->driver->owner)) { gigaset_get_channel()
196 spin_unlock_irqrestore(&bcs->cs->lock, flags); gigaset_get_channel()
202 spin_unlock_irqrestore(&bcs->cs->lock, flags); gigaset_get_channel()
206 struct bc_state *gigaset_get_free_channel(struct cardstate *cs) gigaset_get_free_channel() argument
211 spin_lock_irqsave(&cs->lock, flags); gigaset_get_free_channel()
212 if (!try_module_get(cs->driver->owner)) { gigaset_get_free_channel()
215 spin_unlock_irqrestore(&cs->lock, flags); gigaset_get_free_channel()
218 for (i = 0; i < cs->channels; ++i) gigaset_get_free_channel()
219 if (!cs->bcs[i].use_count) { gigaset_get_free_channel()
220 ++cs->bcs[i].use_count; gigaset_get_free_channel()
221 cs->bcs[i].busy = 1; gigaset_get_free_channel()
222 spin_unlock_irqrestore(&cs->lock, flags); gigaset_get_free_channel()
224 return cs->bcs + i; gigaset_get_free_channel()
226 module_put(cs->driver->owner); gigaset_get_free_channel()
227 spin_unlock_irqrestore(&cs->lock, flags); gigaset_get_free_channel()
236 spin_lock_irqsave(&bcs->cs->lock, flags); gigaset_free_channel()
240 spin_unlock_irqrestore(&bcs->cs->lock, flags); gigaset_free_channel()
245 module_put(bcs->cs->driver->owner); gigaset_free_channel()
247 spin_unlock_irqrestore(&bcs->cs->lock, flags); gigaset_free_channel()
250 int gigaset_get_channels(struct cardstate *cs) gigaset_get_channels() argument
255 spin_lock_irqsave(&cs->lock, flags); gigaset_get_channels()
256 for (i = 0; i < cs->channels; ++i) gigaset_get_channels()
257 if (cs->bcs[i].use_count) { gigaset_get_channels()
258 spin_unlock_irqrestore(&cs->lock, flags); gigaset_get_channels()
263 for (i = 0; i < cs->channels; ++i) gigaset_get_channels()
264 ++cs->bcs[i].use_count; gigaset_get_channels()
265 spin_unlock_irqrestore(&cs->lock, flags); gigaset_get_channels()
272 void gigaset_free_channels(struct cardstate *cs) gigaset_free_channels() argument
278 spin_lock_irqsave(&cs->lock, flags); gigaset_free_channels()
279 for (i = 0; i < cs->channels; ++i) gigaset_free_channels()
280 --cs->bcs[i].use_count; gigaset_free_channels()
281 spin_unlock_irqrestore(&cs->lock, flags); gigaset_free_channels()
284 void gigaset_block_channels(struct cardstate *cs) gigaset_block_channels() argument
290 spin_lock_irqsave(&cs->lock, flags); gigaset_block_channels()
291 for (i = 0; i < cs->channels; ++i) gigaset_block_channels()
292 ++cs->bcs[i].use_count; gigaset_block_channels()
293 spin_unlock_irqrestore(&cs->lock, flags); gigaset_block_channels()
296 static void clear_events(struct cardstate *cs) clear_events() argument
302 spin_lock_irqsave(&cs->ev_lock, flags); clear_events()
304 head = cs->ev_head; clear_events()
305 tail = cs->ev_tail; clear_events()
308 ev = cs->events + head; clear_events()
313 cs->ev_head = tail; clear_events()
315 spin_unlock_irqrestore(&cs->ev_lock, flags); clear_events()
320 * @cs: device descriptor structure.
332 struct event_t *gigaset_add_event(struct cardstate *cs, gigaset_add_event() argument
342 spin_lock_irqsave(&cs->ev_lock, flags); gigaset_add_event()
344 tail = cs->ev_tail; gigaset_add_event()
346 if (unlikely(next == cs->ev_head)) gigaset_add_event()
347 dev_err(cs->dev, "event queue full\n"); gigaset_add_event()
349 event = cs->events + tail; gigaset_add_event()
356 cs->ev_tail = next; gigaset_add_event()
359 spin_unlock_irqrestore(&cs->ev_lock, flags); gigaset_add_event()
375 static void dealloc_temp_at_states(struct cardstate *cs) dealloc_temp_at_states() argument
379 list_for_each_entry_safe(cur, next, &cs->temp_at_states, list) { dealloc_temp_at_states()
391 bcs->cs->ops->freebcshw(bcs); gigaset_freebcs()
409 struct cardstate *cs; alloc_cs() local
416 cs = drv->cs + i; alloc_cs()
417 if (!(cs->flags & VALID_MINOR)) { alloc_cs()
418 cs->flags = VALID_MINOR; alloc_cs()
419 ret = cs; alloc_cs()
428 static void free_cs(struct cardstate *cs) free_cs() argument
430 cs->flags = 0; free_cs()
433 static void make_valid(struct cardstate *cs, unsigned mask) make_valid() argument
436 struct gigaset_driver *drv = cs->driver; make_valid()
438 cs->flags |= mask; make_valid()
442 static void make_invalid(struct cardstate *cs, unsigned mask) make_invalid() argument
445 struct gigaset_driver *drv = cs->driver; make_invalid()
447 cs->flags &= ~mask; make_invalid()
453 * @cs: device descriptor structure.
457 * @cs and all structures referenced from it.
460 void gigaset_freecs(struct cardstate *cs) gigaset_freecs() argument
465 if (!cs) gigaset_freecs()
468 mutex_lock(&cs->mutex); gigaset_freecs()
470 spin_lock_irqsave(&cs->lock, flags); gigaset_freecs()
471 cs->running = 0; gigaset_freecs()
472 spin_unlock_irqrestore(&cs->lock, flags); /* event handler and timer are gigaset_freecs()
475 tasklet_kill(&cs->event_tasklet); gigaset_freecs()
476 del_timer_sync(&cs->timer); gigaset_freecs()
478 switch (cs->cs_init) { gigaset_freecs()
481 for (i = 0; i < cs->channels; ++i) { gigaset_freecs()
483 gigaset_freebcs(cs->bcs + i); gigaset_freecs()
487 gigaset_free_dev_sysfs(cs); gigaset_freecs()
489 gigaset_if_free(cs); gigaset_freecs()
492 cs->ops->freecshw(cs); gigaset_freecs()
497 make_invalid(cs, VALID_ID); gigaset_freecs()
498 gigaset_isdn_unregdev(cs); gigaset_freecs()
503 clear_at_state(&cs->at_state); gigaset_freecs()
504 dealloc_temp_at_states(cs); gigaset_freecs()
505 clear_events(cs); gigaset_freecs()
506 tty_port_destroy(&cs->port); gigaset_freecs()
511 kfree(cs->inbuf); gigaset_freecs()
512 kfree(cs->bcs); gigaset_freecs()
515 mutex_unlock(&cs->mutex); gigaset_freecs()
516 free_cs(cs); gigaset_freecs()
521 struct cardstate *cs, int cid) gigaset_at_init()
539 at_state->cs = cs; gigaset_at_init()
543 at_state->replystruct = cs->tabnocid; gigaset_at_init()
545 at_state->replystruct = cs->tabcid; gigaset_at_init()
549 static void gigaset_inbuf_init(struct inbuf_t *inbuf, struct cardstate *cs) gigaset_inbuf_init() argument
554 inbuf->cs = cs; gigaset_inbuf_init()
589 dev_err(inbuf->cs->dev, gigaset_fill_inbuf()
608 static int gigaset_initbcs(struct bc_state *bcs, struct cardstate *cs, gigaset_initbcs() argument
622 gigaset_at_init(&bcs->at_state, bcs, cs, -1); gigaset_initbcs()
633 bcs->cs = cs; gigaset_initbcs()
638 bcs->ignore = cs->ignoreframes; gigaset_initbcs()
648 return cs->ops->initbcshw(bcs); gigaset_initbcs()
673 struct cardstate *cs; gigaset_initcs() local
677 gig_dbg(DEBUG_INIT, "allocating cs"); gigaset_initcs()
678 cs = alloc_cs(drv); gigaset_initcs()
679 if (!cs) { gigaset_initcs()
684 cs->cs_init = 0; gigaset_initcs()
685 cs->channels = channels; gigaset_initcs()
686 cs->onechannel = onechannel; gigaset_initcs()
687 cs->ignoreframes = ignoreframes; gigaset_initcs()
688 INIT_LIST_HEAD(&cs->temp_at_states); gigaset_initcs()
689 cs->running = 0; gigaset_initcs()
690 init_timer(&cs->timer); /* clear next & prev */ gigaset_initcs()
691 spin_lock_init(&cs->ev_lock); gigaset_initcs()
692 cs->ev_tail = 0; gigaset_initcs()
693 cs->ev_head = 0; gigaset_initcs()
695 tasklet_init(&cs->event_tasklet, gigaset_handle_event, gigaset_initcs()
696 (unsigned long) cs); gigaset_initcs()
697 tty_port_init(&cs->port); gigaset_initcs()
698 cs->commands_pending = 0; gigaset_initcs()
699 cs->cur_at_seq = 0; gigaset_initcs()
700 cs->gotfwver = -1; gigaset_initcs()
701 cs->dev = NULL; gigaset_initcs()
702 cs->tty_dev = NULL; gigaset_initcs()
703 cs->cidmode = cidmode != 0; gigaset_initcs()
704 cs->tabnocid = gigaset_tab_nocid; gigaset_initcs()
705 cs->tabcid = gigaset_tab_cid; gigaset_initcs()
707 init_waitqueue_head(&cs->waitqueue); gigaset_initcs()
708 cs->waiting = 0; gigaset_initcs()
710 cs->mode = M_UNKNOWN; gigaset_initcs()
711 cs->mstate = MS_UNINITIALIZED; gigaset_initcs()
713 cs->bcs = kmalloc(channels * sizeof(struct bc_state), GFP_KERNEL); gigaset_initcs()
714 cs->inbuf = kmalloc(sizeof(struct inbuf_t), GFP_KERNEL); gigaset_initcs()
715 if (!cs->bcs || !cs->inbuf) { gigaset_initcs()
719 ++cs->cs_init; gigaset_initcs()
722 spin_lock_init(&cs->lock); gigaset_initcs()
723 gigaset_at_init(&cs->at_state, NULL, cs, 0); gigaset_initcs()
724 cs->dle = 0; gigaset_initcs()
725 cs->cbytes = 0; gigaset_initcs()
728 gigaset_inbuf_init(cs->inbuf, cs); gigaset_initcs()
730 cs->connected = 0; gigaset_initcs()
731 cs->isdn_up = 0; gigaset_initcs()
734 cs->cmdbuf = cs->lastcmdbuf = NULL; gigaset_initcs()
735 spin_lock_init(&cs->cmdlock); gigaset_initcs()
736 cs->curlen = 0; gigaset_initcs()
737 cs->cmdbytes = 0; gigaset_initcs()
740 if (gigaset_isdn_regdev(cs, modulename) < 0) { gigaset_initcs()
745 make_valid(cs, VALID_ID); gigaset_initcs()
746 ++cs->cs_init; gigaset_initcs()
748 if (cs->ops->initcshw(cs) < 0) gigaset_initcs()
751 ++cs->cs_init; gigaset_initcs()
754 gigaset_if_init(cs); gigaset_initcs()
757 gigaset_init_dev_sysfs(cs); gigaset_initcs()
762 if (gigaset_initbcs(cs->bcs + i, cs, i) < 0) { gigaset_initcs()
768 spin_lock_irqsave(&cs->lock, flags); gigaset_initcs()
769 cs->running = 1; gigaset_initcs()
770 spin_unlock_irqrestore(&cs->lock, flags); gigaset_initcs()
771 setup_timer(&cs->timer, timer_tick, (unsigned long) cs); gigaset_initcs()
772 cs->timer.expires = jiffies + msecs_to_jiffies(GIG_TICK); gigaset_initcs()
773 add_timer(&cs->timer); gigaset_initcs()
775 gig_dbg(DEBUG_INIT, "cs initialized"); gigaset_initcs()
776 return cs; gigaset_initcs()
780 gigaset_freecs(cs); gigaset_initcs()
789 struct cardstate *cs = bcs->cs; gigaset_bcs_reinit() local
795 spin_lock_irqsave(&cs->lock, flags); gigaset_bcs_reinit()
801 spin_unlock_irqrestore(&cs->lock, flags); gigaset_bcs_reinit()
812 bcs->ignore = cs->ignoreframes; gigaset_bcs_reinit()
816 cs->ops->reinitbcshw(bcs); gigaset_bcs_reinit()
819 static void cleanup_cs(struct cardstate *cs) cleanup_cs() argument
825 spin_lock_irqsave(&cs->lock, flags); cleanup_cs()
827 cs->mode = M_UNKNOWN; cleanup_cs()
828 cs->mstate = MS_UNINITIALIZED; cleanup_cs()
830 clear_at_state(&cs->at_state); cleanup_cs()
831 dealloc_temp_at_states(cs); cleanup_cs()
832 gigaset_at_init(&cs->at_state, NULL, cs, 0); cleanup_cs()
834 cs->inbuf->inputstate = INS_command; cleanup_cs()
835 cs->inbuf->head = 0; cleanup_cs()
836 cs->inbuf->tail = 0; cleanup_cs()
838 cb = cs->cmdbuf; cleanup_cs()
844 cs->cmdbuf = cs->lastcmdbuf = NULL; cleanup_cs()
845 cs->curlen = 0; cleanup_cs()
846 cs->cmdbytes = 0; cleanup_cs()
847 cs->gotfwver = -1; cleanup_cs()
848 cs->dle = 0; cleanup_cs()
849 cs->cur_at_seq = 0; cleanup_cs()
850 cs->commands_pending = 0; cleanup_cs()
851 cs->cbytes = 0; cleanup_cs()
853 spin_unlock_irqrestore(&cs->lock, flags); cleanup_cs()
855 for (i = 0; i < cs->channels; ++i) { cleanup_cs()
856 gigaset_freebcs(cs->bcs + i); cleanup_cs()
857 if (gigaset_initbcs(cs->bcs + i, cs, i) < 0) cleanup_cs()
861 if (cs->waiting) { cleanup_cs()
862 cs->cmd_result = -ENODEV; cleanup_cs()
863 cs->waiting = 0; cleanup_cs()
864 wake_up_interruptible(&cs->waitqueue); cleanup_cs()
871 * @cs: device descriptor structure.
880 int gigaset_start(struct cardstate *cs) gigaset_start() argument
884 if (mutex_lock_interruptible(&cs->mutex)) gigaset_start()
887 spin_lock_irqsave(&cs->lock, flags); gigaset_start()
888 cs->connected = 1; gigaset_start()
889 spin_unlock_irqrestore(&cs->lock, flags); gigaset_start()
891 if (cs->mstate != MS_LOCKED) { gigaset_start()
892 cs->ops->set_modem_ctrl(cs, 0, TIOCM_DTR | TIOCM_RTS); gigaset_start()
893 cs->ops->baud_rate(cs, B115200); gigaset_start()
894 cs->ops->set_line_ctrl(cs, CS8); gigaset_start()
895 cs->control_state = TIOCM_DTR | TIOCM_RTS; gigaset_start()
898 cs->waiting = 1; gigaset_start()
900 if (!gigaset_add_event(cs, &cs->at_state, EV_START, NULL, 0, NULL)) { gigaset_start()
901 cs->waiting = 0; gigaset_start()
904 gigaset_schedule_event(cs); gigaset_start()
906 wait_event(cs->waitqueue, !cs->waiting); gigaset_start()
908 mutex_unlock(&cs->mutex); gigaset_start()
912 mutex_unlock(&cs->mutex); gigaset_start()
919 * @cs: device descriptor structure.
927 int gigaset_shutdown(struct cardstate *cs) gigaset_shutdown() argument
929 mutex_lock(&cs->mutex); gigaset_shutdown()
931 if (!(cs->flags & VALID_MINOR)) { gigaset_shutdown()
932 mutex_unlock(&cs->mutex); gigaset_shutdown()
936 cs->waiting = 1; gigaset_shutdown()
938 if (!gigaset_add_event(cs, &cs->at_state, EV_SHUTDOWN, NULL, 0, NULL)) gigaset_shutdown()
940 gigaset_schedule_event(cs); gigaset_shutdown()
942 wait_event(cs->waitqueue, !cs->waiting); gigaset_shutdown()
944 cleanup_cs(cs); gigaset_shutdown()
947 mutex_unlock(&cs->mutex); gigaset_shutdown()
954 * @cs: device descriptor structure.
959 void gigaset_stop(struct cardstate *cs) gigaset_stop() argument
961 mutex_lock(&cs->mutex); gigaset_stop()
963 cs->waiting = 1; gigaset_stop()
965 if (!gigaset_add_event(cs, &cs->at_state, EV_STOP, NULL, 0, NULL)) gigaset_stop()
967 gigaset_schedule_event(cs); gigaset_stop()
969 wait_event(cs->waitqueue, !cs->waiting); gigaset_stop()
971 cleanup_cs(cs); gigaset_stop()
974 mutex_unlock(&cs->mutex); gigaset_stop()
985 struct cardstate *cs; gigaset_get_cs_by_id() local
993 cs = drv->cs + i; gigaset_get_cs_by_id()
994 if ((cs->flags & VALID_ID) && cs->myid == id) { gigaset_get_cs_by_id()
995 ret = cs; gigaset_get_cs_by_id()
1020 if (drv->cs[index].flags & VALID_MINOR) gigaset_get_cs_by_minor()
1021 ret = drv->cs + index; gigaset_get_cs_by_minor()
1053 kfree(drv->cs); gigaset_freedriver()
1093 drv->cs = kmalloc(minors * sizeof *drv->cs, GFP_KERNEL); gigaset_initdriver()
1094 if (!drv->cs) gigaset_initdriver()
1098 drv->cs[i].flags = 0; gigaset_initdriver()
1099 drv->cs[i].driver = drv; gigaset_initdriver()
1100 drv->cs[i].ops = drv->ops; gigaset_initdriver()
1101 drv->cs[i].minor_index = i; gigaset_initdriver()
1102 mutex_init(&drv->cs[i].mutex); gigaset_initdriver()
520 gigaset_at_init(struct at_state_t *at_state, struct bc_state *bcs, struct cardstate *cs, int cid) gigaset_at_init() argument
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| H A D | proc.c | 21 struct cardstate *cs = dev_get_drvdata(dev); show_cidmode() local
23 return sprintf(buf, "%u\n", cs->cidmode); show_cidmode()
29 struct cardstate *cs = dev_get_drvdata(dev); set_cidmode() local
40 if (mutex_lock_interruptible(&cs->mutex)) set_cidmode()
43 cs->waiting = 1; set_cidmode()
44 if (!gigaset_add_event(cs, &cs->at_state, EV_PROC_CIDMODE, set_cidmode()
46 cs->waiting = 0; set_cidmode()
47 mutex_unlock(&cs->mutex); set_cidmode()
50 gigaset_schedule_event(cs); set_cidmode()
52 wait_event(cs->waitqueue, !cs->waiting); set_cidmode()
54 mutex_unlock(&cs->mutex); set_cidmode()
62 void gigaset_free_dev_sysfs(struct cardstate *cs) gigaset_free_dev_sysfs() argument
64 if (!cs->tty_dev) gigaset_free_dev_sysfs()
68 device_remove_file(cs->tty_dev, &dev_attr_cidmode); gigaset_free_dev_sysfs()
72 void gigaset_init_dev_sysfs(struct cardstate *cs) gigaset_init_dev_sysfs() argument
74 if (!cs->tty_dev) gigaset_init_dev_sysfs()
78 if (device_create_file(cs->tty_dev, &dev_attr_cidmode)) gigaset_init_dev_sysfs()
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| H A D | ser-gigaset.c | 63 static int write_modem(struct cardstate *cs) write_modem() argument
65 struct tty_struct *tty = cs->hw.ser->tty; write_modem()
66 struct bc_state *bcs = &cs->bcs[0]; /* only one channel */ write_modem()
85 flush_send_queue(cs); write_modem()
105 static int send_cb(struct cardstate *cs) send_cb() argument
107 struct tty_struct *tty = cs->hw.ser->tty; send_cb()
115 cb = cs->cmdbuf; send_cb()
125 flush_send_queue(cs); send_cb()
131 sent, cb->len, cs->cmdbytes); send_cb()
135 spin_lock_irqsave(&cs->cmdlock, flags); send_cb()
136 cs->cmdbytes -= cs->curlen; send_cb()
138 cs->cmdbuf = cb = cb->next; send_cb()
141 cs->curlen = cb->len; send_cb()
143 cs->lastcmdbuf = NULL; send_cb()
144 cs->curlen = 0; send_cb()
146 spin_unlock_irqrestore(&cs->cmdlock, flags); send_cb()
163 struct cardstate *cs = (struct cardstate *) data; gigaset_modem_fill() local
168 if (!cs) { gigaset_modem_fill()
172 bcs = cs->bcs; gigaset_modem_fill()
179 sent = send_cb(cs); gigaset_modem_fill()
198 if (write_modem(cs) < 0) gigaset_modem_fill()
205 static void flush_send_queue(struct cardstate *cs) flush_send_queue() argument
212 spin_lock_irqsave(&cs->cmdlock, flags); flush_send_queue()
213 while ((cb = cs->cmdbuf) != NULL) { flush_send_queue()
214 cs->cmdbuf = cb->next; flush_send_queue()
219 cs->cmdbuf = cs->lastcmdbuf = NULL; flush_send_queue()
220 cs->cmdbytes = cs->curlen = 0; flush_send_queue()
221 spin_unlock_irqrestore(&cs->cmdlock, flags); flush_send_queue()
224 if (cs->bcs->tx_skb) flush_send_queue()
225 dev_kfree_skb_any(cs->bcs->tx_skb); flush_send_queue()
226 while ((skb = skb_dequeue(&cs->bcs->squeue)) != NULL) flush_send_queue()
237 * cs controller state structure
244 static int gigaset_write_cmd(struct cardstate *cs, struct cmdbuf_t *cb) gigaset_write_cmd() argument
248 gigaset_dbg_buffer(cs->mstate != MS_LOCKED ? gigaset_write_cmd()
252 spin_lock_irqsave(&cs->cmdlock, flags); gigaset_write_cmd()
253 cb->prev = cs->lastcmdbuf; gigaset_write_cmd()
254 if (cs->lastcmdbuf) gigaset_write_cmd()
255 cs->lastcmdbuf->next = cb; gigaset_write_cmd()
257 cs->cmdbuf = cb; gigaset_write_cmd()
258 cs->curlen = cb->len; gigaset_write_cmd()
260 cs->cmdbytes += cb->len; gigaset_write_cmd()
261 cs->lastcmdbuf = cb; gigaset_write_cmd()
262 spin_unlock_irqrestore(&cs->cmdlock, flags); gigaset_write_cmd()
264 spin_lock_irqsave(&cs->lock, flags); gigaset_write_cmd()
265 if (cs->connected) gigaset_write_cmd()
266 tasklet_schedule(&cs->write_tasklet); gigaset_write_cmd()
267 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_cmd()
279 static int gigaset_write_room(struct cardstate *cs) gigaset_write_room() argument
283 bytes = cs->cmdbytes; gigaset_write_room()
295 static int gigaset_chars_in_buffer(struct cardstate *cs) gigaset_chars_in_buffer() argument
297 return cs->cmdbytes; gigaset_chars_in_buffer()
307 static int gigaset_brkchars(struct cardstate *cs, const unsigned char buf[6]) gigaset_brkchars() argument
368 static void gigaset_freecshw(struct cardstate *cs) gigaset_freecshw() argument
370 tasklet_kill(&cs->write_tasklet); gigaset_freecshw()
371 if (!cs->hw.ser) gigaset_freecshw()
373 dev_set_drvdata(&cs->hw.ser->dev.dev, NULL); gigaset_freecshw()
374 platform_device_unregister(&cs->hw.ser->dev); gigaset_freecshw()
375 kfree(cs->hw.ser); gigaset_freecshw()
376 cs->hw.ser = NULL; gigaset_freecshw()
392 static int gigaset_initcshw(struct cardstate *cs) gigaset_initcshw() argument
402 cs->hw.ser = scs; gigaset_initcshw()
404 cs->hw.ser->dev.name = GIGASET_MODULENAME; gigaset_initcshw()
405 cs->hw.ser->dev.id = cs->minor_index; gigaset_initcshw()
406 cs->hw.ser->dev.dev.release = gigaset_device_release; gigaset_initcshw()
407 rc = platform_device_register(&cs->hw.ser->dev); gigaset_initcshw()
410 kfree(cs->hw.ser); gigaset_initcshw()
411 cs->hw.ser = NULL; gigaset_initcshw()
414 dev_set_drvdata(&cs->hw.ser->dev.dev, cs); gigaset_initcshw()
416 tasklet_init(&cs->write_tasklet, gigaset_initcshw()
417 gigaset_modem_fill, (unsigned long) cs); gigaset_initcshw()
429 static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state, gigaset_set_modem_ctrl() argument
432 struct tty_struct *tty = cs->hw.ser->tty; gigaset_set_modem_ctrl()
445 static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag) gigaset_baud_rate() argument
450 static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag) gigaset_set_line_ctrl() argument
481 struct cardstate *cs = tty->disc_data; cs_get() local
483 if (!cs || !cs->hw.ser) { cs_get()
487 atomic_inc(&cs->hw.ser->refcnt); cs_get()
488 return cs; cs_get()
491 static void cs_put(struct cardstate *cs) cs_put() argument
493 if (atomic_dec_and_test(&cs->hw.ser->refcnt)) cs_put()
494 complete(&cs->hw.ser->dead_cmp); cs_put()
504 struct cardstate *cs; gigaset_tty_open() local
517 cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME); gigaset_tty_open()
518 if (!cs) { gigaset_tty_open()
523 cs->dev = &cs->hw.ser->dev.dev; gigaset_tty_open()
524 cs->hw.ser->tty = tty; gigaset_tty_open()
525 atomic_set(&cs->hw.ser->refcnt, 1); gigaset_tty_open()
526 init_completion(&cs->hw.ser->dead_cmp); gigaset_tty_open()
527 tty->disc_data = cs; gigaset_tty_open()
543 cs->mstate = MS_LOCKED; gigaset_tty_open()
544 rc = gigaset_start(cs); gigaset_tty_open()
546 tasklet_kill(&cs->write_tasklet); gigaset_tty_open()
556 gigaset_freecs(cs); gigaset_tty_open()
567 struct cardstate *cs = tty->disc_data; gigaset_tty_close() local
571 if (!cs) { gigaset_tty_close()
579 if (!cs->hw.ser) gigaset_tty_close()
583 if (!atomic_dec_and_test(&cs->hw.ser->refcnt)) gigaset_tty_close()
584 wait_for_completion(&cs->hw.ser->dead_cmp); gigaset_tty_close()
588 gigaset_stop(cs); gigaset_tty_close()
589 tasklet_kill(&cs->write_tasklet); gigaset_tty_close()
590 flush_send_queue(cs); gigaset_tty_close()
591 cs->dev = NULL; gigaset_tty_close()
592 gigaset_freecs(cs); gigaset_tty_close()
640 struct cardstate *cs = cs_get(tty); gigaset_tty_ioctl() local
644 if (!cs) gigaset_tty_ioctl()
663 flush_send_queue(cs); gigaset_tty_ioctl()
673 cs_put(cs); gigaset_tty_ioctl()
693 struct cardstate *cs = cs_get(tty); gigaset_tty_receive() local
697 if (!cs) gigaset_tty_receive()
699 inbuf = cs->inbuf; gigaset_tty_receive()
701 dev_err(cs->dev, "%s: no inbuf\n", __func__); gigaset_tty_receive()
702 cs_put(cs); gigaset_tty_receive()
724 dev_err(cs->dev, gigaset_tty_receive()
738 gigaset_schedule_event(cs); gigaset_tty_receive()
739 cs_put(cs); gigaset_tty_receive()
748 struct cardstate *cs = cs_get(tty); gigaset_tty_wakeup() local
751 if (!cs) gigaset_tty_wakeup()
753 tasklet_schedule(&cs->write_tasklet); gigaset_tty_wakeup()
754 cs_put(cs); gigaset_tty_wakeup()
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| H A D | usb-gigaset.c | 154 static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state, gigaset_set_modem_ctrl() argument
157 struct usb_device *udev = cs->hw.usb->udev; gigaset_set_modem_ctrl()
178 static int set_value(struct cardstate *cs, u8 req, u16 val) set_value() argument
180 struct usb_device *udev = cs->hw.usb->udev; set_value()
200 0, 0, cs->hw.usb->bchars, 6, 2000 /*?*/); set_value()
211 static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag) gigaset_baud_rate() argument
231 dev_err(cs->dev, "unsupported baudrate request 0x%x," gigaset_baud_rate()
237 return set_value(cs, 1, val); gigaset_baud_rate()
244 static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag) gigaset_set_line_ctrl() argument
263 dev_err(cs->dev, "CSIZE was not CS5-CS8, using default of 8\n"); gigaset_set_line_ctrl()
276 return set_value(cs, 3, val); gigaset_set_line_ctrl()
295 static int write_modem(struct cardstate *cs);
296 static int send_cb(struct cardstate *cs);
304 struct cardstate *cs = (struct cardstate *) data; gigaset_modem_fill() local
305 struct bc_state *bcs = &cs->bcs[0]; /* only one channel */ gigaset_modem_fill()
309 if (cs->hw.usb->busy) { gigaset_modem_fill()
316 if (cs->cmdbuf) { /* commands to send? */ gigaset_modem_fill()
318 if (send_cb(cs) < 0) { gigaset_modem_fill()
336 if (write_modem(cs) < 0) { gigaset_modem_fill()
347 struct cardstate *cs = urb->context; gigaset_read_int_callback() local
348 struct inbuf_t *inbuf = cs->inbuf; gigaset_read_int_callback()
359 src = cs->hw.usb->rcvbuf; gigaset_read_int_callback()
361 dev_warn(cs->dev, gigaset_read_int_callback()
368 gigaset_schedule_event(inbuf->cs); gigaset_read_int_callback()
382 spin_lock_irqsave(&cs->lock, flags); gigaset_read_int_callback()
383 if (!cs->connected) { gigaset_read_int_callback()
384 spin_unlock_irqrestore(&cs->lock, flags); gigaset_read_int_callback()
389 spin_unlock_irqrestore(&cs->lock, flags); gigaset_read_int_callback()
391 dev_err(cs->dev, "error %d resubmitting URB\n", -r); gigaset_read_int_callback()
398 struct cardstate *cs = urb->context; gigaset_write_bulk_callback() local
407 cs->hw.usb->busy = 0; gigaset_write_bulk_callback()
410 dev_err(cs->dev, "bulk transfer failed (status %d)\n", gigaset_write_bulk_callback()
416 spin_lock_irqsave(&cs->lock, flags); gigaset_write_bulk_callback()
417 if (!cs->connected) { gigaset_write_bulk_callback()
420 cs->hw.usb->busy = 0; gigaset_write_bulk_callback()
421 tasklet_schedule(&cs->write_tasklet); gigaset_write_bulk_callback()
423 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_bulk_callback()
426 static int send_cb(struct cardstate *cs) send_cb() argument
428 struct cmdbuf_t *cb = cs->cmdbuf; send_cb()
432 struct usb_cardstate *ucs = cs->hw.usb; send_cb()
436 spin_lock_irqsave(&cs->cmdlock, flags); send_cb()
437 cs->cmdbytes -= cs->curlen; send_cb()
439 cs->curlen, cs->cmdbytes); send_cb()
440 cs->cmdbuf = cb->next; send_cb()
441 if (cs->cmdbuf) { send_cb()
442 cs->cmdbuf->prev = NULL; send_cb()
443 cs->curlen = cs->cmdbuf->len; send_cb()
445 cs->lastcmdbuf = NULL; send_cb()
446 cs->curlen = 0; send_cb()
448 spin_unlock_irqrestore(&cs->cmdlock, flags); send_cb()
454 cb = cs->cmdbuf; send_cb()
465 gigaset_write_bulk_callback, cs); send_cb()
471 spin_lock_irqsave(&cs->lock, flags); send_cb()
472 status = cs->connected ? send_cb()
475 spin_unlock_irqrestore(&cs->lock, flags); send_cb()
479 dev_err(cs->dev, send_cb()
492 static int gigaset_write_cmd(struct cardstate *cs, struct cmdbuf_t *cb) gigaset_write_cmd() argument
497 gigaset_dbg_buffer(cs->mstate != MS_LOCKED ? gigaset_write_cmd()
501 spin_lock_irqsave(&cs->cmdlock, flags); gigaset_write_cmd()
502 cb->prev = cs->lastcmdbuf; gigaset_write_cmd()
503 if (cs->lastcmdbuf) gigaset_write_cmd()
504 cs->lastcmdbuf->next = cb; gigaset_write_cmd()
506 cs->cmdbuf = cb; gigaset_write_cmd()
507 cs->curlen = cb->len; gigaset_write_cmd()
509 cs->cmdbytes += cb->len; gigaset_write_cmd()
510 cs->lastcmdbuf = cb; gigaset_write_cmd()
511 spin_unlock_irqrestore(&cs->cmdlock, flags); gigaset_write_cmd()
513 spin_lock_irqsave(&cs->lock, flags); gigaset_write_cmd()
515 if (cs->connected) gigaset_write_cmd()
516 tasklet_schedule(&cs->write_tasklet); gigaset_write_cmd()
517 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_cmd()
521 static int gigaset_write_room(struct cardstate *cs) gigaset_write_room() argument
525 bytes = cs->cmdbytes; gigaset_write_room()
529 static int gigaset_chars_in_buffer(struct cardstate *cs) gigaset_chars_in_buffer() argument
531 return cs->cmdbytes; gigaset_chars_in_buffer()
539 static int gigaset_brkchars(struct cardstate *cs, const unsigned char buf[6]) gigaset_brkchars() argument
541 struct usb_device *udev = cs->hw.usb->udev; gigaset_brkchars()
544 memcpy(cs->hw.usb->bchars, buf, 6); gigaset_brkchars()
567 static void gigaset_freecshw(struct cardstate *cs) gigaset_freecshw() argument
569 tasklet_kill(&cs->write_tasklet); gigaset_freecshw()
570 kfree(cs->hw.usb); gigaset_freecshw()
573 static int gigaset_initcshw(struct cardstate *cs) gigaset_initcshw() argument
577 cs->hw.usb = ucs = gigaset_initcshw()
593 tasklet_init(&cs->write_tasklet, gigaset_initcshw()
594 gigaset_modem_fill, (unsigned long) cs); gigaset_initcshw()
600 static int write_modem(struct cardstate *cs) write_modem() argument
604 struct bc_state *bcs = &cs->bcs[0]; /* only one channel */ write_modem()
605 struct usb_cardstate *ucs = cs->hw.usb; write_modem()
623 spin_lock_irqsave(&cs->lock, flags); write_modem()
624 if (cs->connected) { write_modem()
629 gigaset_write_bulk_callback, cs); write_modem()
634 spin_unlock_irqrestore(&cs->lock, flags); write_modem()
637 dev_err(cs->dev, "could not submit urb (error %d)\n", -ret); write_modem()
660 struct cardstate *cs = NULL; gigaset_probe() local
694 cs = gigaset_initcs(driver, 1, 1, 0, cidmode, GIGASET_MODULENAME); gigaset_probe()
695 if (!cs) gigaset_probe()
697 ucs = cs->hw.usb; gigaset_probe()
703 cs->dev = &interface->dev; gigaset_probe()
706 usb_set_intfdata(interface, cs); gigaset_probe()
715 dev_err(cs->dev, "Couldn't allocate bulk_out_buffer\n"); gigaset_probe()
722 dev_err(cs->dev, "Couldn't allocate bulk_out_urb\n"); gigaset_probe()
733 dev_err(cs->dev, "No free urbs available\n"); gigaset_probe()
741 dev_err(cs->dev, "Couldn't allocate rcvbuf\n"); gigaset_probe()
750 cs, endpoint->bInterval); gigaset_probe()
754 dev_err(cs->dev, "Could not submit URB (error %d)\n", -retval); gigaset_probe()
760 cs->mstate = MS_LOCKED; gigaset_probe()
762 retval = gigaset_start(cs); gigaset_probe()
764 tasklet_kill(&cs->write_tasklet); gigaset_probe()
781 gigaset_freecs(cs); gigaset_probe()
787 struct cardstate *cs; gigaset_disconnect() local
790 cs = usb_get_intfdata(interface); gigaset_disconnect()
791 ucs = cs->hw.usb; gigaset_disconnect()
793 dev_info(cs->dev, "disconnecting Gigaset USB adapter\n"); gigaset_disconnect()
797 gigaset_stop(cs); gigaset_disconnect()
800 tasklet_kill(&cs->write_tasklet); gigaset_disconnect()
814 cs->dev = NULL; gigaset_disconnect()
815 gigaset_freecs(cs); gigaset_disconnect()
823 struct cardstate *cs = usb_get_intfdata(intf); gigaset_suspend() local
826 cs->connected = 0; /* prevent rescheduling */ gigaset_suspend()
827 usb_kill_urb(cs->hw.usb->read_urb); gigaset_suspend()
828 tasklet_kill(&cs->write_tasklet); gigaset_suspend()
829 usb_kill_urb(cs->hw.usb->bulk_out_urb); gigaset_suspend()
840 struct cardstate *cs = usb_get_intfdata(intf); gigaset_resume() local
844 cs->connected = 1; gigaset_resume()
845 rc = usb_submit_urb(cs->hw.usb->read_urb, GFP_KERNEL); gigaset_resume()
847 dev_err(cs->dev, "Could not submit read URB (error %d)\n", -rc); gigaset_resume()
929 gigaset_shutdown(driver->cs + i); usb_gigaset_exit()
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| H A D | capi.c | 151 static inline void ignore_cstruct_param(struct cardstate *cs, _cstruct param, ignore_cstruct_param() argument
155 dev_warn(cs->dev, "%s: ignoring unsupported parameter: %s\n", ignore_cstruct_param()
326 static void send_data_b3_conf(struct cardstate *cs, struct capi_ctr *ctr, send_data_b3_conf() argument
335 dev_err(cs->dev, "%s: out of memory\n", __func__); send_data_b3_conf()
372 struct cardstate *cs = bcs->cs; gigaset_skb_sent() local
373 struct gigaset_capi_ctr *iif = cs->iif; gigaset_skb_sent()
398 send_data_b3_conf(cs, &iif->ctr, ap->id, CAPIMSG_MSGID(req), gigaset_skb_sent()
417 struct cardstate *cs = bcs->cs; gigaset_skb_rcvd() local
418 struct gigaset_capi_ctr *iif = cs->iif; gigaset_skb_rcvd()
497 struct cardstate *cs = at_state->cs; gigaset_isdn_icall() local
499 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_icall()
528 dev_warn(cs->dev, "RING ignored - bad BC %s\n", gigaset_isdn_icall()
556 dev_warn(cs->dev, "RING ignored - bad HLC %s\n", gigaset_isdn_icall()
581 dev_warn(cs->dev, "RING ignored - bad number %s\n", gigaset_isdn_icall()
596 dev_warn(cs->dev, "RING ignored - bad number %s\n", gigaset_isdn_icall()
631 dev_warn(cs->dev, "%s: channel not properly cleared (%p/%d)\n", gigaset_isdn_icall()
646 dev_err(cs->dev, "%s: out of memory\n", gigaset_isdn_icall()
652 dev_err(cs->dev, "%s: message parser failure\n", gigaset_isdn_icall()
686 struct cardstate *cs = bcs->cs; send_disconnect_ind() local
687 struct gigaset_capi_ctr *iif = cs->iif; send_disconnect_ind()
699 dev_err(cs->dev, "%s: out of memory\n", __func__); send_disconnect_ind()
704 dev_err(cs->dev, "%s: message parser failure\n", __func__); send_disconnect_ind()
720 struct cardstate *cs = bcs->cs; send_disconnect_b3_ind() local
721 struct gigaset_capi_ctr *iif = cs->iif; send_disconnect_b3_ind()
734 dev_err(cs->dev, "%s: out of memory\n", __func__); send_disconnect_b3_ind()
739 dev_err(cs->dev, "%s: message parser failure\n", __func__); send_disconnect_b3_ind()
756 struct cardstate *cs = bcs->cs; gigaset_isdn_connD() local
757 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_connD()
772 dev_warn(cs->dev, "%s: application %u not connected\n", gigaset_isdn_connD()
779 dev_warn(cs->dev, "%s: dropping extra application %u\n", gigaset_isdn_connD()
804 dev_err(cs->dev, "%s: out of memory\n", __func__); gigaset_isdn_connD()
808 dev_err(cs->dev, "%s: message parser failure\n", __func__); gigaset_isdn_connD()
855 struct cardstate *cs = bcs->cs; gigaset_isdn_connB() local
856 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_connB()
872 dev_warn(cs->dev, "%s: application %u not connected\n", gigaset_isdn_connB()
896 dev_warn(cs->dev, "%s: dropping extra application %u\n", gigaset_isdn_connB()
908 dev_err(cs->dev, "%s: out of memory\n", __func__); gigaset_isdn_connB()
912 dev_err(cs->dev, "%s: message parser failure\n", __func__); gigaset_isdn_connB()
943 * @cs: device descriptor structure.
948 void gigaset_isdn_start(struct cardstate *cs) gigaset_isdn_start() argument
950 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_start()
957 /* ToDo: check/assert cs->gotfwver? */ gigaset_isdn_start()
958 iif->ctr.version.majormanuversion = cs->fwver[0]; gigaset_isdn_start()
959 iif->ctr.version.minormanuversion = cs->fwver[1]; gigaset_isdn_start()
961 iif->ctr.profile.nbchannel = cs->channels; gigaset_isdn_start()
978 * @cs: device descriptor structure.
983 void gigaset_isdn_stop(struct cardstate *cs) gigaset_isdn_stop() argument
985 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_stop()
1002 struct cardstate *cs = ctr->driverdata; gigaset_register_appl() local
1010 dev_notice(cs->dev, gigaset_register_appl()
1017 dev_err(cs->dev, "%s: out of memory\n", __func__); gigaset_register_appl()
1024 dev_info(cs->dev, "application %u registered\n", ap->id); gigaset_register_appl()
1035 struct cardstate *cs = bcs->cs; remove_appl_from_channel() local
1061 dev_notice(cs->dev, "%s: hanging up channel %u\n", remove_appl_from_channel()
1063 gigaset_add_event(cs, &bcs->at_state, remove_appl_from_channel()
1065 gigaset_schedule_event(cs); remove_appl_from_channel()
1089 struct cardstate *cs = iif->ctr.driverdata; gigaset_release_appl() local
1098 for (ch = 0; ch < cs->channels; ch++) gigaset_release_appl()
1099 remove_appl_from_channel(&cs->bcs[ch], ap); gigaset_release_appl()
1104 dev_info(cs->dev, "application %u released\n", appl); gigaset_release_appl()
1122 struct cardstate *cs = iif->ctr.driverdata; send_conf() local
1131 dev_err(cs->dev, "%s: message parser failure\n", __func__); send_conf()
1147 struct cardstate *cs = iif->ctr.driverdata; do_facility_req() local
1157 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_facility_req()
1186 dev_notice(cs->dev, "%s: %s missing\n", "FACILITY_REQ", do_facility_req()
1204 dev_notice(cs->dev, "%s: %s missing\n", do_facility_req()
1211 dev_notice(cs->dev, do_facility_req()
1228 dev_notice(cs->dev, do_facility_req()
1266 dev_err(cs->dev, "%s: out of memory\n", __func__); do_facility_req()
1270 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_facility_req()
1287 struct cardstate *cs = iif->ctr.driverdata; do_listen_req() local
1291 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_listen_req()
1311 struct cardstate *cs = iif->ctr.driverdata; do_alert_req() local
1315 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_alert_req()
1332 struct cardstate *cs = iif->ctr.driverdata; do_connect_req() local
1344 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_connect_req()
1351 bcs = gigaset_get_free_channel(cs); do_connect_req()
1353 dev_notice(cs->dev, "%s: no B channel available\n", do_connect_req()
1360 dev_warn(cs->dev, "%s: channel not properly cleared (%p/%d)\n", do_connect_req()
1380 dev_notice(cs->dev, "%s: %s missing\n", do_connect_req()
1392 dev_notice(cs->dev, "%s: %s type/plan 0x%02x unsupported\n", do_connect_req()
1425 dev_notice(cs->dev, do_connect_req()
1434 dev_notice(cs->dev, "%s: %s IE truncated\n", do_connect_req()
1447 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_connect_req()
1471 dev_notice(cs->dev, "%s: unknown CIP value %d\n", do_connect_req()
1525 dev_notice(cs->dev, "%s: cannot set HLC without BC\n", do_connect_req()
1535 dev_warn(cs->dev, do_connect_req()
1546 dev_warn(cs->dev, do_connect_req()
1552 dev_warn(cs->dev, do_connect_req()
1556 dev_warn(cs->dev, do_connect_req()
1559 ignore_cstruct_param(cs, cmsg->B1configuration, do_connect_req()
1561 ignore_cstruct_param(cs, cmsg->B2configuration, do_connect_req()
1563 ignore_cstruct_param(cs, cmsg->B3configuration, do_connect_req()
1572 ignore_cstruct_param(cs, cmsg->CalledPartySubaddress, do_connect_req()
1574 ignore_cstruct_param(cs, cmsg->CallingPartySubaddress, do_connect_req()
1576 ignore_cstruct_param(cs, cmsg->LLC, do_connect_req()
1579 ignore_cstruct_param(cs, cmsg->BChannelinformation, do_connect_req()
1581 ignore_cstruct_param(cs, cmsg->Keypadfacility, do_connect_req()
1583 ignore_cstruct_param(cs, cmsg->Useruserdata, do_connect_req()
1585 ignore_cstruct_param(cs, cmsg->Facilitydataarray, do_connect_req()
1597 if (!gigaset_add_event(cs, &bcs->at_state, EV_DIAL, commands, do_connect_req()
1602 gigaset_schedule_event(cs); do_connect_req()
1607 dev_err(cs->dev, "%s: out of memory\n", __func__); do_connect_req()
1626 struct cardstate *cs = iif->ctr.driverdata; do_connect_resp() local
1635 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_connect_resp()
1644 if (!channel || channel > cs->channels) { do_connect_resp()
1645 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_connect_resp()
1649 bcs = cs->bcs + channel - 1; do_connect_resp()
1677 dev_warn(cs->dev, do_connect_resp()
1688 dev_warn(cs->dev, do_connect_resp()
1694 dev_warn(cs->dev, do_connect_resp()
1698 dev_warn(cs->dev, do_connect_resp()
1701 ignore_cstruct_param(cs, cmsg->B1configuration, do_connect_resp()
1703 ignore_cstruct_param(cs, cmsg->B2configuration, do_connect_resp()
1705 ignore_cstruct_param(cs, cmsg->B3configuration, do_connect_resp()
1710 ignore_cstruct_param(cs, cmsg->ConnectedNumber, do_connect_resp()
1712 ignore_cstruct_param(cs, cmsg->ConnectedSubaddress, do_connect_resp()
1714 ignore_cstruct_param(cs, cmsg->LLC, do_connect_resp()
1717 ignore_cstruct_param(cs, cmsg->BChannelinformation, do_connect_resp()
1719 ignore_cstruct_param(cs, cmsg->Keypadfacility, do_connect_resp()
1721 ignore_cstruct_param(cs, cmsg->Useruserdata, do_connect_resp()
1723 ignore_cstruct_param(cs, cmsg->Facilitydataarray, do_connect_resp()
1728 if (!gigaset_add_event(cs, &cs->bcs[channel - 1].at_state, do_connect_resp()
1731 gigaset_schedule_event(cs); do_connect_resp()
1758 dev_err(cs->dev, "%s: application %u not found\n", do_connect_resp()
1780 dev_info(cs->dev, "%s: Reject=%x\n", do_connect_resp()
1782 if (!gigaset_add_event(cs, &cs->bcs[channel - 1].at_state, do_connect_resp()
1785 gigaset_schedule_event(cs); do_connect_resp()
1798 struct cardstate *cs = iif->ctr.driverdata; do_connect_b3_req() local
1805 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_connect_b3_req()
1813 if (!channel || channel > cs->channels) { do_connect_b3_req()
1814 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_connect_b3_req()
1819 bcs = &cs->bcs[channel - 1]; do_connect_b3_req()
1828 ignore_cstruct_param(cs, cmsg->NCPI, "CONNECT_B3_REQ", "NCPI"); do_connect_b3_req()
1845 struct cardstate *cs = iif->ctr.driverdata; do_connect_b3_resp() local
1854 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_connect_b3_resp()
1862 if (!channel || channel > cs->channels || do_connect_b3_resp()
1864 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_connect_b3_resp()
1869 bcs = &cs->bcs[channel - 1]; do_connect_b3_resp()
1876 if (!gigaset_add_event(cs, &bcs->at_state, do_connect_b3_resp()
1881 gigaset_schedule_event(cs); do_connect_b3_resp()
1898 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_connect_b3_resp()
1915 struct cardstate *cs = iif->ctr.driverdata; do_disconnect_req() local
1924 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_disconnect_req()
1932 if (!channel || channel > cs->channels) { do_disconnect_req()
1933 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_disconnect_req()
1938 bcs = cs->bcs + channel - 1; do_disconnect_req()
1942 ignore_cstruct_param(cs, cmsg->BChannelinformation, do_disconnect_req()
1944 ignore_cstruct_param(cs, cmsg->Keypadfacility, do_disconnect_req()
1946 ignore_cstruct_param(cs, cmsg->Useruserdata, do_disconnect_req()
1948 ignore_cstruct_param(cs, cmsg->Facilitydataarray, do_disconnect_req()
1968 dev_err(cs->dev, "%s: out of memory\n", __func__); do_disconnect_req()
1978 dev_err(cs->dev, "%s: out of memory\n", __func__); do_disconnect_req()
1985 dev_err(cs->dev, "%s: message parser failure\n", do_disconnect_req()
1997 if (!gigaset_add_event(cs, &bcs->at_state, EV_HUP, NULL, 0, NULL)) { do_disconnect_req()
2001 gigaset_schedule_event(cs); do_disconnect_req()
2015 struct cardstate *cs = iif->ctr.driverdata; do_disconnect_b3_req() local
2022 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_disconnect_b3_req()
2030 if (!channel || channel > cs->channels || do_disconnect_b3_req()
2032 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_disconnect_b3_req()
2037 bcs = &cs->bcs[channel - 1]; do_disconnect_b3_req()
2047 if (!gigaset_add_event(cs, &bcs->at_state, EV_HUP, NULL, 0, NULL)) { do_disconnect_b3_req()
2051 gigaset_schedule_event(cs); do_disconnect_b3_req()
2054 ignore_cstruct_param(cs, cmsg->NCPI, do_disconnect_b3_req()
2068 struct cardstate *cs = iif->ctr.driverdata; do_data_b3_req() local
2082 if (channel == 0 || channel > cs->channels || ncci != 1) { do_data_b3_req()
2083 dev_notice(cs->dev, "%s: invalid %s 0x%02x\n", do_data_b3_req()
2088 bcs = &cs->bcs[channel - 1]; do_data_b3_req()
2090 dev_notice(cs->dev, "%s: unexpected length %d\n", do_data_b3_req()
2093 dev_notice(cs->dev, "%s: length mismatch (%d+%d!=%d)\n", do_data_b3_req()
2101 dev_notice(cs->dev, "%s: reserved flags set (%x)\n", do_data_b3_req()
2119 if (cs->ops->send_skb(bcs, skb) < 0) { do_data_b3_req()
2129 send_data_b3_conf(cs, &iif->ctr, ap->id, msgid, channel, handle, do_data_b3_req()
2142 struct cardstate *cs = iif->ctr.driverdata; do_reset_b3_req() local
2146 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_reset_b3_req()
2162 struct cardstate *cs = iif->ctr.driverdata; do_unsupported() local
2166 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_unsupported()
2181 struct cardstate *cs = iif->ctr.driverdata; do_nothing() local
2185 dev_err(cs->dev, "%s: message parser failure\n", __func__); do_nothing()
2272 struct cardstate *cs = ctr->driverdata; gigaset_send_message() local
2278 dev_warn(cs->dev, "%s: skb_linearize failed\n", __func__); gigaset_send_message()
2285 dev_notice(cs->dev, "%s: application %u not registered\n", gigaset_send_message()
2295 dev_notice(cs->dev, "%s: unsupported message %u\n", gigaset_send_message()
2315 dev_err(cs->dev, "%s: send queue empty\n", __func__); gigaset_send_message()
2321 dev_warn(cs->dev, "%s: application %u vanished\n", gigaset_send_message()
2328 dev_err(cs->dev, "%s: handler %x vanished\n", gigaset_send_message()
2352 struct cardstate *cs = ctr->driverdata; gigaset_proc_show() local
2358 dev_driver_string(cs->dev), dev_name(cs->dev)); gigaset_proc_show()
2359 seq_printf(m, "%-16s %d\n", "id", cs->myid); gigaset_proc_show()
2360 if (cs->gotfwver) gigaset_proc_show()
2362 cs->fwver[0], cs->fwver[1], cs->fwver[2], cs->fwver[3]); gigaset_proc_show()
2363 seq_printf(m, "%-16s %d\n", "channels", cs->channels); gigaset_proc_show()
2364 seq_printf(m, "%-16s %s\n", "onechannel", cs->onechannel ? "yes" : "no"); gigaset_proc_show()
2366 switch (cs->mode) { gigaset_proc_show()
2384 switch (cs->mstate) { gigaset_proc_show()
2408 seq_printf(m, "%-16s %s\n", "running", cs->running ? "yes" : "no"); gigaset_proc_show()
2409 seq_printf(m, "%-16s %s\n", "connected", cs->connected ? "yes" : "no"); gigaset_proc_show()
2410 seq_printf(m, "%-16s %s\n", "isdn_up", cs->isdn_up ? "yes" : "no"); gigaset_proc_show()
2411 seq_printf(m, "%-16s %s\n", "cidmode", cs->cidmode ? "yes" : "no"); gigaset_proc_show()
2413 for (i = 0; i < cs->channels; i++) { gigaset_proc_show()
2415 cs->bcs[i].corrupted); gigaset_proc_show()
2417 cs->bcs[i].trans_down); gigaset_proc_show()
2419 cs->bcs[i].trans_up); gigaset_proc_show()
2421 cs->bcs[i].chstate); gigaset_proc_show()
2422 switch (cs->bcs[i].proto2) { gigaset_proc_show()
2455 * @cs: device descriptor structure.
2460 int gigaset_isdn_regdev(struct cardstate *cs, const char *isdnid) gigaset_isdn_regdev() argument
2473 iif->ctr.driverdata = cs; gigaset_isdn_regdev()
2495 cs->iif = iif; gigaset_isdn_regdev()
2496 cs->hw_hdr_len = CAPI_DATA_B3_REQ_LEN; gigaset_isdn_regdev()
2502 * @cs: device descriptor structure.
2504 void gigaset_isdn_unregdev(struct cardstate *cs) gigaset_isdn_unregdev() argument
2506 struct gigaset_capi_ctr *iif = cs->iif; gigaset_isdn_unregdev()
2510 cs->iif = NULL; gigaset_isdn_unregdev()
|
| H A D | i4l.c | 46 struct cardstate *cs = gigaset_get_cs_by_id(driverID); writebuf_from_LL() local
51 if (!cs) { writebuf_from_LL()
55 if (channel < 0 || channel >= cs->channels) { writebuf_from_LL()
56 dev_err(cs->dev, "%s: invalid channel ID (%d)\n", writebuf_from_LL()
60 bcs = &cs->bcs[channel]; writebuf_from_LL()
64 dev_err(cs->dev, "%s: skb_linearize failed\n", __func__); writebuf_from_LL()
75 dev_notice(cs->dev, "%s: not ACKing empty packet\n", writebuf_from_LL()
80 dev_err(cs->dev, "%s: packet too large (%d bytes)\n", writebuf_from_LL()
88 dev_err(cs->dev, "%s: insufficient skb headroom\n", __func__); writebuf_from_LL()
104 return cs->ops->send_skb(bcs, skb); writebuf_from_LL()
117 isdn_if *iif = bcs->cs->iif; gigaset_skb_sent()
125 dev_warn(bcs->cs->dev, "%s: skb->len==%d\n", gigaset_skb_sent()
131 bcs->cs->myid, bcs->channel, len); gigaset_skb_sent()
133 response.driver = bcs->cs->myid; gigaset_skb_sent()
153 isdn_if *iif = bcs->cs->iif; gigaset_skb_rcvd()
155 iif->rcvcallb_skb(bcs->cs->myid, bcs->channel, skb); gigaset_skb_rcvd()
169 isdn_if *iif = bcs->cs->iif; gigaset_isdn_rcv_err()
183 response.driver = bcs->cs->myid; gigaset_isdn_rcv_err()
197 struct cardstate *cs; command_from_LL() local
208 cs = gigaset_get_cs_by_id(cntrl->driver); command_from_LL()
209 if (cs == NULL) { command_from_LL()
217 dev_warn(cs->dev, "ISDN_CMD_IOCTL not supported\n"); command_from_LL()
226 if (ch >= cs->channels) { command_from_LL()
227 dev_err(cs->dev, command_from_LL()
231 bcs = cs->bcs + ch; command_from_LL()
233 dev_err(cs->dev, "ISDN_CMD_DIAL: channel not free\n"); command_from_LL()
249 dev_err(cs->dev, "ISDN_CMD_DIAL: out of memory\n"); command_from_LL()
310 if (!gigaset_add_event(cs, &bcs->at_state, EV_DIAL, commands, command_from_LL()
318 gigaset_schedule_event(cs); command_from_LL()
322 if (ch >= cs->channels) { command_from_LL()
323 dev_err(cs->dev, command_from_LL()
327 bcs = cs->bcs + ch; command_from_LL()
337 if (!gigaset_add_event(cs, &bcs->at_state, command_from_LL()
340 gigaset_schedule_event(cs); command_from_LL()
345 if (ch >= cs->channels) { command_from_LL()
346 dev_err(cs->dev, command_from_LL()
350 bcs = cs->bcs + ch; command_from_LL()
351 if (!gigaset_add_event(cs, &bcs->at_state, command_from_LL()
354 gigaset_schedule_event(cs); command_from_LL()
358 dev_info(cs->dev, "ignoring ISDN_CMD_CLREAZ\n"); command_from_LL()
361 dev_info(cs->dev, "ignoring ISDN_CMD_SETEAZ (%s)\n", command_from_LL()
365 if (ch >= cs->channels) { command_from_LL()
366 dev_err(cs->dev, command_from_LL()
370 bcs = cs->bcs + ch; command_from_LL()
372 dev_err(cs->dev, command_from_LL()
386 dev_err(cs->dev, command_from_LL()
394 if (ch >= cs->channels) { command_from_LL()
395 dev_err(cs->dev, command_from_LL()
401 dev_err(cs->dev, command_from_LL()
418 dev_err(bcs->cs->dev, "out of memory\n"); command_from_LL()
426 static void gigaset_i4l_cmd(struct cardstate *cs, int cmd) gigaset_i4l_cmd() argument
428 isdn_if *iif = cs->iif; gigaset_i4l_cmd()
431 command.driver = cs->myid; gigaset_i4l_cmd()
439 isdn_if *iif = bcs->cs->iif; gigaset_i4l_channel_cmd()
442 command.driver = bcs->cs->myid; gigaset_i4l_channel_cmd()
459 struct cardstate *cs = at_state->cs; gigaset_isdn_icall() local
461 isdn_if *iif = cs->iif; gigaset_isdn_icall()
484 dev_warn(cs->dev, "RING ignored - unsupported BC %s\n", gigaset_isdn_icall()
500 dev_notice(cs->dev, "no channel for incoming call\n"); gigaset_isdn_icall()
508 response.driver = cs->myid; gigaset_isdn_icall()
520 dev_warn(cs->dev, gigaset_isdn_icall()
529 dev_warn(cs->dev, gigaset_isdn_icall()
533 dev_err(cs->dev, "LL error %d on ICALL\n", retval); gigaset_isdn_icall()
592 * @cs: device descriptor structure.
597 void gigaset_isdn_start(struct cardstate *cs) gigaset_isdn_start() argument
600 gigaset_i4l_cmd(cs, ISDN_STAT_RUN); gigaset_isdn_start()
605 * @cs: device descriptor structure.
610 void gigaset_isdn_stop(struct cardstate *cs) gigaset_isdn_stop() argument
613 gigaset_i4l_cmd(cs, ISDN_STAT_STOP); gigaset_isdn_stop()
618 * @cs: device descriptor structure.
623 int gigaset_isdn_regdev(struct cardstate *cs, const char *isdnid) gigaset_isdn_regdev() argument
633 if (snprintf(iif->id, sizeof iif->id, "%s_%u", isdnid, cs->minor_index) gigaset_isdn_regdev()
641 iif->channels = cs->channels; gigaset_isdn_regdev()
662 cs->iif = iif; gigaset_isdn_regdev()
663 cs->myid = iif->channels; /* Set my device id */ gigaset_isdn_regdev()
664 cs->hw_hdr_len = HW_HDR_LEN; gigaset_isdn_regdev()
670 * @cs: device descriptor structure.
672 void gigaset_isdn_unregdev(struct cardstate *cs) gigaset_isdn_unregdev() argument
675 gigaset_i4l_cmd(cs, ISDN_STAT_UNLOAD); gigaset_isdn_unregdev()
676 kfree(cs->iif); gigaset_isdn_unregdev()
677 cs->iif = NULL; gigaset_isdn_unregdev()
|
| H A D | bas-gigaset.c | 306 static int gigaset_set_modem_ctrl(struct cardstate *cs, unsigned old_state, gigaset_set_modem_ctrl() argument
312 static int gigaset_baud_rate(struct cardstate *cs, unsigned cflag) gigaset_baud_rate() argument
317 static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag) gigaset_set_line_ctrl() argument
341 * cs->lock must not be held.
347 struct cardstate *cs = bcs->cs; error_hangup() local
349 gigaset_add_event(cs, &bcs->at_state, EV_HUP, NULL, 0, NULL); error_hangup()
350 gigaset_schedule_event(cs); error_hangup()
357 * cs->hw.bas->lock must not be held.
361 static inline void error_reset(struct cardstate *cs) error_reset() argument
364 update_basstate(cs->hw.bas, BS_RESETTING, 0); error_reset()
365 if (req_submit(cs->bcs, HD_RESET_INTERRUPT_PIPE, 0, BAS_TIMEOUT)) error_reset()
367 usb_queue_reset_device(cs->hw.bas->interface); error_reset()
438 struct cardstate *cs = (struct cardstate *) data; cmd_in_timeout() local
439 struct bas_cardstate *ucs = cs->hw.bas; cmd_in_timeout()
448 dev_err(cs->dev, cmd_in_timeout()
454 error_reset(cs); cmd_in_timeout()
460 rc = atread_submit(cs, BAS_TIMEOUT); cmd_in_timeout()
466 error_reset(cs); cmd_in_timeout()
480 struct cardstate *cs = inbuf->cs; read_ctrl_callback() local
481 struct bas_cardstate *ucs = cs->hw.bas; read_ctrl_callback()
494 dev_warn(cs->dev, read_ctrl_callback()
504 gigaset_schedule_event(cs); read_ctrl_callback()
522 rc = atread_submit(cs, BAS_TIMEOUT); read_ctrl_callback()
530 dev_err(cs->dev, "control read: %s, giving up after %d tries\n", read_ctrl_callback()
532 error_reset(cs); read_ctrl_callback()
544 * cs controller state structure
551 static int atread_submit(struct cardstate *cs, int timeout) atread_submit() argument
553 struct bas_cardstate *ucs = cs->hw.bas; atread_submit()
562 dev_err(cs->dev, atread_submit()
568 dev_notice(cs->dev, atread_submit()
585 read_ctrl_callback, cs->inbuf); atread_submit()
590 dev_err(cs->dev, "could not submit HD_READ_ATMESSAGE: %s\n", atread_submit()
611 struct cardstate *cs = urb->context; int_in_work() local
627 dev_err(cs->dev, "clear halt failed: %s\n", get_usb_rcmsg(rc)); int_in_work()
644 struct cardstate *cs = (struct cardstate *) data; int_in_resubmit() local
645 struct bas_cardstate *ucs = cs->hw.bas; int_in_resubmit()
649 dev_err(cs->dev, "interrupt read: giving up after %d tries\n", int_in_resubmit()
658 dev_err(cs->dev, "could not resubmit interrupt URB: %s\n", int_in_resubmit()
673 struct cardstate *cs = urb->context; read_int_callback() local
674 struct bas_cardstate *ucs = cs->hw.bas; read_int_callback()
707 dev_warn(cs->dev, "interrupt read: %s\n", read_int_callback()
714 dev_warn(cs->dev, "incomplete interrupt packet (%d bytes)\n", read_int_callback()
736 start_cbsend(cs); read_int_callback()
742 bcs = cs->bcs + channel; read_int_callback()
749 start_cbsend(cs); read_int_callback()
755 bcs = cs->bcs + channel; read_int_callback()
768 bcs = cs->bcs + channel; read_int_callback()
779 dev_warn(cs->dev, read_int_callback()
783 spin_lock_irqsave(&cs->lock, flags); read_int_callback()
785 spin_unlock_irqrestore(&cs->lock, flags); read_int_callback()
786 dev_warn(cs->dev, read_int_callback()
793 dev_err(cs->dev, read_int_callback()
801 spin_unlock_irqrestore(&cs->lock, flags); read_int_callback()
802 dev_err(cs->dev, "out of memory receiving AT data\n"); read_int_callback()
807 rc = atread_submit(cs, BAS_TIMEOUT); read_int_callback()
813 spin_unlock_irqrestore(&cs->lock, flags); read_int_callback()
815 error_reset(cs); read_int_callback()
820 dev_notice(cs->dev, "interrupt pipe reset\n"); read_int_callback()
828 dev_warn(cs->dev, read_int_callback()
839 dev_err(cs->dev, "could not resubmit interrupt URB: %s\n", read_int_callback()
841 error_reset(cs); read_int_callback()
894 urb->dev = bcs->cs->hw.bas->udev; read_iso_callback()
899 dev_err(bcs->cs->dev, read_iso_callback()
975 urb->dev = bcs->cs->hw.bas->udev; starturbs()
1007 urb->dev = bcs->cs->hw.bas->udev; starturbs()
1088 urb->dev = ucx->bcs->cs->hw.bas->udev; submit_iso_write_urb()
1120 dev_err(ucx->bcs->cs->dev, submit_iso_write_urb()
1142 dev_err(ucx->bcs->cs->dev, submit_iso_write_urb()
1161 struct cardstate *cs = bcs->cs; write_iso_tasklet() local
1187 dev_err(cs->dev, "isoc write underrun\n"); write_iso_tasklet()
1211 dev_err(cs->dev, write_iso_tasklet()
1237 dev_warn(cs->dev, write_iso_tasklet()
1247 dev_err(cs->dev, "isoc write: stalled\n"); write_iso_tasklet()
1251 dev_warn(cs->dev, "isoc write: %s\n", write_iso_tasklet()
1304 struct cardstate *cs = bcs->cs; read_iso_tasklet() local
1324 dev_warn(cs->dev, read_iso_tasklet()
1355 dev_err(cs->dev, "isoc read: stalled\n"); read_iso_tasklet()
1359 dev_warn(cs->dev, "isoc read: %s\n", read_iso_tasklet()
1383 dev_warn(cs->dev, read_iso_tasklet()
1389 dev_warn(cs->dev, read_iso_tasklet()
1394 dev_warn(cs->dev, read_iso_tasklet()
1402 dev_warn(cs->dev, read_iso_tasklet()
1412 dev_warn(cs->dev, "isoc read: %d data bytes missing\n", read_iso_tasklet()
1422 urb->dev = bcs->cs->hw.bas->udev; read_iso_tasklet()
1427 dev_err(cs->dev, read_iso_tasklet()
1446 struct cardstate *cs = (struct cardstate *) data; req_timeout() local
1447 struct bas_cardstate *ucs = cs->hw.bas; req_timeout()
1464 dev_err(cs->dev, "timeout opening AT channel\n"); req_timeout()
1465 error_reset(cs); req_timeout()
1469 dev_err(cs->dev, "timeout opening channel 1\n"); req_timeout()
1470 error_hangup(&cs->bcs[0]); req_timeout()
1474 dev_err(cs->dev, "timeout opening channel 2\n"); req_timeout()
1475 error_hangup(&cs->bcs[1]); req_timeout()
1479 dev_err(cs->dev, "timeout closing AT channel\n"); req_timeout()
1480 error_reset(cs); req_timeout()
1484 dev_err(cs->dev, "timeout closing channel 1\n"); req_timeout()
1485 error_reset(cs); req_timeout()
1489 dev_err(cs->dev, "timeout closing channel 2\n"); req_timeout()
1490 error_reset(cs); req_timeout()
1495 dev_err(cs->dev, req_timeout()
1501 dev_warn(cs->dev, "request 0x%02x timed out, clearing\n", req_timeout()
1595 struct bas_cardstate *ucs = bcs->cs->hw.bas; req_submit()
1604 dev_err(bcs->cs->dev, req_submit()
1623 dev_err(bcs->cs->dev, "could not submit request 0x%02x: %s\n", req_submit()
1649 struct cardstate *cs = bcs->cs; gigaset_init_bchannel() local
1653 spin_lock_irqsave(&cs->lock, flags); gigaset_init_bchannel()
1654 if (unlikely(!cs->connected)) { gigaset_init_bchannel()
1656 spin_unlock_irqrestore(&cs->lock, flags); gigaset_init_bchannel()
1660 if (cs->hw.bas->basstate & BS_SUSPEND) { gigaset_init_bchannel()
1661 dev_notice(cs->dev, gigaset_init_bchannel()
1663 spin_unlock_irqrestore(&cs->lock, flags); gigaset_init_bchannel()
1669 spin_unlock_irqrestore(&cs->lock, flags); gigaset_init_bchannel()
1670 dev_err(cs->dev, gigaset_init_bchannel()
1682 dev_err(cs->dev, "could not open channel B%d\n", gigaset_init_bchannel()
1687 spin_unlock_irqrestore(&cs->lock, flags); gigaset_init_bchannel()
1705 struct cardstate *cs = bcs->cs; gigaset_close_bchannel() local
1709 spin_lock_irqsave(&cs->lock, flags); gigaset_close_bchannel()
1710 if (unlikely(!cs->connected)) { gigaset_close_bchannel()
1711 spin_unlock_irqrestore(&cs->lock, flags); gigaset_close_bchannel()
1716 if (!(cs->hw.bas->basstate & (bcs->channel ? BS_B2OPEN : BS_B1OPEN))) { gigaset_close_bchannel()
1718 spin_unlock_irqrestore(&cs->lock, flags); gigaset_close_bchannel()
1727 dev_err(cs->dev, "closing channel B%d failed\n", gigaset_close_bchannel()
1730 spin_unlock_irqrestore(&cs->lock, flags); gigaset_close_bchannel()
1739 * must be called with cs->cmdlock held
1741 * cs controller state structure
1743 static void complete_cb(struct cardstate *cs) complete_cb() argument
1745 struct cmdbuf_t *cb = cs->cmdbuf; complete_cb()
1748 cs->cmdbytes -= cs->curlen; complete_cb()
1750 cs->curlen, cs->cmdbytes); complete_cb()
1752 cs->cmdbuf = cb->next; complete_cb()
1753 cs->cmdbuf->prev = NULL; complete_cb()
1754 cs->curlen = cs->cmdbuf->len; complete_cb()
1756 cs->cmdbuf = NULL; complete_cb()
1757 cs->lastcmdbuf = NULL; complete_cb()
1758 cs->curlen = 0; complete_cb()
1776 struct cardstate *cs = urb->context; write_command_callback() local
1777 struct bas_cardstate *ucs = cs->hw.bas; write_command_callback()
1799 dev_warn(cs->dev, write_command_callback()
1807 dev_warn(cs->dev, write_command_callback()
1813 if (cs->cmdbuf == NULL) { write_command_callback()
1814 dev_warn(cs->dev, write_command_callback()
1820 dev_notice(cs->dev, "command write: %s, retry %d\n", write_command_callback()
1822 if (atwrite_submit(cs, cs->cmdbuf->buf, cs->cmdbuf->len) >= 0) write_command_callback()
1829 spin_lock_irqsave(&cs->cmdlock, flags); write_command_callback()
1830 if (cs->cmdbuf != NULL) write_command_callback()
1831 complete_cb(cs); write_command_callback()
1832 spin_unlock_irqrestore(&cs->cmdlock, flags); write_command_callback()
1842 struct cardstate *cs = (struct cardstate *) data; atrdy_timeout() local
1843 struct bas_cardstate *ucs = cs->hw.bas; atrdy_timeout()
1845 dev_warn(cs->dev, "timeout waiting for HD_READY_SEND_ATDATA\n"); atrdy_timeout()
1849 start_cbsend(cs); atrdy_timeout()
1855 * cs controller state structure
1863 static int atwrite_submit(struct cardstate *cs, unsigned char *buf, int len) atwrite_submit() argument
1865 struct bas_cardstate *ucs = cs->hw.bas; atwrite_submit()
1871 dev_err(cs->dev, atwrite_submit()
1884 write_command_callback, cs); atwrite_submit()
1888 dev_err(cs->dev, "could not submit HD_WRITE_ATMESSAGE: %s\n", atwrite_submit()
1905 * cs controller state structure
1910 static int start_cbsend(struct cardstate *cs) start_cbsend() argument
1913 struct bas_cardstate *ucs = cs->hw.bas; start_cbsend()
1927 rc = req_submit(cs->bcs, HD_OPEN_ATCHANNEL, 0, BAS_TIMEOUT); start_cbsend()
1930 spin_lock_irqsave(&cs->cmdlock, flags); start_cbsend()
1931 while (cs->cmdbuf != NULL) start_cbsend()
1932 complete_cb(cs); start_cbsend()
1933 spin_unlock_irqrestore(&cs->cmdlock, flags); start_cbsend()
1939 spin_lock_irqsave(&cs->cmdlock, flags); start_cbsend()
1941 while ((cb = cs->cmdbuf) != NULL && (ucs->basstate & BS_ATREADY)) { start_cbsend()
1943 rc = atwrite_submit(cs, cb->buf, cb->len); start_cbsend()
1946 complete_cb(cs); start_cbsend()
1950 spin_unlock_irqrestore(&cs->cmdlock, flags); start_cbsend()
1962 * cs controller state structure
1968 static int gigaset_write_cmd(struct cardstate *cs, struct cmdbuf_t *cb) gigaset_write_cmd() argument
1973 gigaset_dbg_buffer(cs->mstate != MS_LOCKED ? gigaset_write_cmd()
1994 spin_lock_irqsave(&cs->lock, flags); gigaset_write_cmd()
1995 if (!(cs->hw.bas->basstate & BS_ATRDPEND)) { gigaset_write_cmd()
1996 kfree(cs->hw.bas->rcvbuf); gigaset_write_cmd()
1997 cs->hw.bas->rcvbuf = NULL; gigaset_write_cmd()
1998 cs->hw.bas->rcvbuf_size = 0; gigaset_write_cmd()
1999 cs->hw.bas->retry_cmd_in = 0; gigaset_write_cmd()
2000 atread_submit(cs, 0); gigaset_write_cmd()
2002 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_cmd()
2004 rc = req_submit(cs->bcs, HD_CLOSE_ATCHANNEL, 0, BAS_TIMEOUT); gigaset_write_cmd()
2013 spin_lock_irqsave(&cs->cmdlock, flags); gigaset_write_cmd()
2014 cb->prev = cs->lastcmdbuf; gigaset_write_cmd()
2015 if (cs->lastcmdbuf) gigaset_write_cmd()
2016 cs->lastcmdbuf->next = cb; gigaset_write_cmd()
2018 cs->cmdbuf = cb; gigaset_write_cmd()
2019 cs->curlen = cb->len; gigaset_write_cmd()
2021 cs->cmdbytes += cb->len; gigaset_write_cmd()
2022 cs->lastcmdbuf = cb; gigaset_write_cmd()
2023 spin_unlock_irqrestore(&cs->cmdlock, flags); gigaset_write_cmd()
2025 spin_lock_irqsave(&cs->lock, flags); gigaset_write_cmd()
2026 if (unlikely(!cs->connected)) { gigaset_write_cmd()
2027 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_cmd()
2030 spin_lock_irqsave(&cs->cmdlock, flags); gigaset_write_cmd()
2031 while (cs->cmdbuf != NULL) gigaset_write_cmd()
2032 complete_cb(cs); gigaset_write_cmd()
2033 spin_unlock_irqrestore(&cs->cmdlock, flags); gigaset_write_cmd()
2036 rc = start_cbsend(cs); gigaset_write_cmd()
2037 spin_unlock_irqrestore(&cs->lock, flags); gigaset_write_cmd()
2050 static int gigaset_write_room(struct cardstate *cs) gigaset_write_room() argument
2063 static int gigaset_chars_in_buffer(struct cardstate *cs) gigaset_chars_in_buffer() argument
2065 return cs->cmdbytes; gigaset_chars_in_buffer()
2075 static int gigaset_brkchars(struct cardstate *cs, const unsigned char buf[6]) gigaset_brkchars() argument
2185 static void gigaset_freecshw(struct cardstate *cs) gigaset_freecshw() argument
2188 kfree(cs->hw.bas->int_in_buf); gigaset_freecshw()
2189 kfree(cs->hw.bas); gigaset_freecshw()
2190 cs->hw.bas = NULL; gigaset_freecshw()
2195 * cs cardstate structure
2199 static int gigaset_initcshw(struct cardstate *cs) gigaset_initcshw() argument
2203 cs->hw.bas = ucs = kmalloc(sizeof *ucs, GFP_KERNEL); gigaset_initcshw()
2224 setup_timer(&ucs->timer_ctrl, req_timeout, (unsigned long) cs); gigaset_initcshw()
2225 setup_timer(&ucs->timer_atrdy, atrdy_timeout, (unsigned long) cs); gigaset_initcshw()
2226 setup_timer(&ucs->timer_cmd_in, cmd_in_timeout, (unsigned long) cs); gigaset_initcshw()
2227 setup_timer(&ucs->timer_int_in, int_in_resubmit, (unsigned long) cs); gigaset_initcshw()
2238 * cs controller state structure
2240 static void freeurbs(struct cardstate *cs) freeurbs() argument
2242 struct bas_cardstate *ucs = cs->hw.bas; freeurbs()
2248 ubc = cs->bcs[j].hw.bas; freeurbs()
2283 struct cardstate *cs = NULL; gigaset_probe() local
2326 cs = gigaset_initcs(driver, BAS_CHANNELS, 0, 0, cidmode, gigaset_probe()
2328 if (!cs) gigaset_probe()
2330 ucs = cs->hw.bas; gigaset_probe()
2336 cs->dev = &interface->dev; gigaset_probe()
2350 ubc = cs->bcs[j].hw.bas; gigaset_probe()
2369 ucs->int_in_buf, IP_MSGSIZE, read_int_callback, cs, gigaset_probe()
2373 dev_err(cs->dev, "could not submit interrupt URB: %s\n", gigaset_probe()
2380 rc = req_submit(cs->bcs, HD_DEVICE_INIT_ACK, 0, 0); gigaset_probe()
2386 cs->mstate = MS_LOCKED; gigaset_probe()
2389 usb_set_intfdata(interface, cs); gigaset_probe()
2391 rc = gigaset_start(cs); gigaset_probe()
2398 dev_err(cs->dev, "could not allocate URBs\n"); gigaset_probe()
2401 freeurbs(cs); gigaset_probe()
2404 gigaset_freecs(cs); gigaset_probe()
2413 struct cardstate *cs; gigaset_disconnect() local
2417 cs = usb_get_intfdata(interface); gigaset_disconnect()
2419 ucs = cs->hw.bas; gigaset_disconnect()
2421 dev_info(cs->dev, "disconnecting Gigaset base\n"); gigaset_disconnect()
2428 gigaset_bchannel_down(cs->bcs + j); gigaset_disconnect()
2431 gigaset_stop(cs); gigaset_disconnect()
2439 freeurbs(cs); gigaset_disconnect()
2447 cs->dev = NULL; gigaset_disconnect()
2448 gigaset_freecs(cs); gigaset_disconnect()
2458 struct cardstate *cs = usb_get_intfdata(intf); gigaset_suspend() local
2459 struct bas_cardstate *ucs = cs->hw.bas; gigaset_suspend()
2477 dev_warn(cs->dev, "cannot suspend:\n"); gigaset_suspend()
2479 dev_warn(cs->dev, " B channel 1 open\n"); gigaset_suspend()
2481 dev_warn(cs->dev, " B channel 2 open\n"); gigaset_suspend()
2483 dev_warn(cs->dev, " receiving AT reply\n"); gigaset_suspend()
2485 dev_warn(cs->dev, " sending AT command\n"); gigaset_suspend()
2493 rc = req_submit(cs->bcs, HD_CLOSE_ATCHANNEL, 0, 0); gigaset_suspend()
2526 struct cardstate *cs = usb_get_intfdata(intf); gigaset_resume() local
2527 struct bas_cardstate *ucs = cs->hw.bas; gigaset_resume()
2533 dev_err(cs->dev, "could not resubmit interrupt URB: %s\n", gigaset_resume()
2631 if (gigaset_shutdown(driver->cs + i) < 0) bas_gigaset_exit()
2636 ucs = driver->cs[i].hw.bas; bas_gigaset_exit()
|
| H A D | dummyll.c | 53 void gigaset_isdn_start(struct cardstate *cs) gigaset_isdn_start() argument
57 void gigaset_isdn_stop(struct cardstate *cs) gigaset_isdn_stop() argument
61 int gigaset_isdn_regdev(struct cardstate *cs, const char *isdnid) gigaset_isdn_regdev() argument
66 void gigaset_isdn_unregdev(struct cardstate *cs) gigaset_isdn_unregdev() argument
|
| H A D | asyncdata.c | 52 struct cardstate *cs = inbuf->cs; cmd_loop() local
53 unsigned cbytes = cs->cbytes; cmd_loop()
63 if (cbytes == 0 && cs->respdata[0] == '\r') { cmd_loop()
65 cs->respdata[0] = 0; cmd_loop()
72 dev_warn(cs->dev, "response too large (%d)\n", cmd_loop()
76 cs->cbytes = cbytes; cmd_loop()
78 cbytes, cs->respdata); cmd_loop()
79 gigaset_handle_modem_response(cs); cmd_loop()
83 cs->respdata[0] = c; cmd_loop()
85 /* cs->dle may have changed */ cmd_loop()
86 if (cs->dle && !(inbuf->inputstate & INS_DLE_command)) cmd_loop()
96 } else if (cs->dle || cmd_loop()
107 cs->respdata[cbytes] = c; cmd_loop()
112 cs->cbytes = cbytes; cmd_loop()
126 gigaset_if_receive(inbuf->cs, src, numbytes); lock_loop()
140 struct cardstate *cs = inbuf->cs; hdlc_loop() local
141 struct bc_state *bcs = cs->bcs; hdlc_loop()
163 } else if (cs->dle || (inputstate & INS_DLE_command)) { hdlc_loop()
184 } else if (cs->dle || hdlc_loop()
209 dev_warn(cs->dev, hdlc_loop()
216 dev_err(cs->dev, hdlc_loop()
262 dev_warn(cs->dev, "received packet too long\n"); hdlc_loop()
287 struct cardstate *cs = inbuf->cs; iraw_loop() local
288 struct bc_state *bcs = cs->bcs; iraw_loop()
309 } else if (cs->dle || (inputstate & INS_DLE_command)) { iraw_loop()
340 struct cardstate *cs = inbuf->cs; handle_dle() local
342 if (cs->mstate == MS_LOCKED) handle_dle()
348 (cs->dle || inbuf->inputstate & INS_DLE_command)) { handle_dle()
369 dev_notice(cs->dev, handle_dle()
376 dev_notice(cs->dev, handle_dle()
380 if (cs->dle) handle_dle()
387 if (!(cs->dle || inbuf->inputstate & INS_DLE_command)) handle_dle()
388 dev_notice(cs->dev, handle_dle()
392 dev_notice(cs->dev, "received <DLE><%02x>\n", handle_dle()
409 struct cardstate *cs = inbuf->cs; gigaset_m10x_input() local
427 if (cs->mstate == MS_LOCKED) gigaset_m10x_input()
431 else if (cs->bcs->proto2 == L2_HDLC) gigaset_m10x_input()
587 struct cardstate *cs = bcs->cs; gigaset_m10x_send_skb() local
596 dev_err(cs->dev, gigaset_m10x_send_skb()
602 spin_lock_irqsave(&cs->lock, flags); gigaset_m10x_send_skb()
603 if (cs->connected) gigaset_m10x_send_skb()
604 tasklet_schedule(&cs->write_tasklet); gigaset_m10x_send_skb()
605 spin_unlock_irqrestore(&cs->lock, flags); gigaset_m10x_send_skb()
|
| H A D | gigaset.h | 281 struct cardstate *cs; member in struct:inbuf_t
348 struct cardstate *cs; member in struct:at_state_t
380 struct cardstate *cs; member in struct:bc_state
514 struct cardstate *cs; member in struct:gigaset_driver
570 int (*write_cmd)(struct cardstate *cs, struct cmdbuf_t *cb);
573 int (*write_room)(struct cardstate *cs);
574 int (*chars_in_buffer)(struct cardstate *cs);
575 int (*brkchars)(struct cardstate *cs, const unsigned char buf[6]);
594 /* Called by gigaset_initcs() for setting up cs->hw.xxx */
595 int (*initcshw)(struct cardstate *cs);
597 /* Called by gigaset_freecs() for freeing cs->hw.xxx */
598 void (*freecshw)(struct cardstate *cs);
602 int (*set_modem_ctrl)(struct cardstate *cs, unsigned old_state,
604 int (*baud_rate)(struct cardstate *cs, unsigned cflag);
605 int (*set_line_ctrl)(struct cardstate *cs, unsigned cflag);
672 int gigaset_isdn_regdev(struct cardstate *cs, const char *isdnid);
673 void gigaset_isdn_unregdev(struct cardstate *cs);
681 void gigaset_isdn_start(struct cardstate *cs);
682 void gigaset_isdn_stop(struct cardstate *cs);
698 void gigaset_handle_modem_response(struct cardstate *cs);
705 void gigaset_init_dev_sysfs(struct cardstate *cs);
706 void gigaset_free_dev_sysfs(struct cardstate *cs);
714 struct cardstate *cs, int cid);
716 struct bc_state *gigaset_get_free_channel(struct cardstate *cs);
718 int gigaset_get_channels(struct cardstate *cs);
719 void gigaset_free_channels(struct cardstate *cs);
720 void gigaset_block_channels(struct cardstate *cs);
737 gigaset_init[b]cs(). */
742 /* Free card state. Calls hardware dependent gigaset_free[b]cs(). */
743 void gigaset_freecs(struct cardstate *cs);
746 int gigaset_start(struct cardstate *cs);
749 void gigaset_stop(struct cardstate *cs);
752 int gigaset_shutdown(struct cardstate *cs);
758 struct event_t *gigaset_add_event(struct cardstate *cs,
763 int gigaset_enterconfigmode(struct cardstate *cs);
765 /* cs->lock must not be locked */ gigaset_schedule_event()
766 static inline void gigaset_schedule_event(struct cardstate *cs) gigaset_schedule_event() argument
769 spin_lock_irqsave(&cs->lock, flags); gigaset_schedule_event()
770 if (cs->running) gigaset_schedule_event()
771 tasklet_schedule(&cs->event_tasklet); gigaset_schedule_event()
772 spin_unlock_irqrestore(&cs->lock, flags); gigaset_schedule_event()
776 /* cs->lock must not be locked */ gigaset_bchannel_down()
779 gigaset_add_event(bcs->cs, &bcs->at_state, EV_BC_CLOSED, NULL, 0, NULL); gigaset_bchannel_down()
780 gigaset_schedule_event(bcs->cs); gigaset_bchannel_down()
784 /* cs->lock must not be locked */ gigaset_bchannel_up()
787 gigaset_add_event(bcs->cs, &bcs->at_state, EV_BC_OPEN, NULL, 0, NULL); gigaset_bchannel_up()
788 gigaset_schedule_event(bcs->cs); gigaset_bchannel_up()
794 struct cardstate *cs = bcs->cs; gigaset_new_rx_skb() local
795 unsigned short hw_hdr_len = cs->hw_hdr_len; gigaset_new_rx_skb()
802 dev_warn(cs->dev, "could not allocate skb\n"); gigaset_new_rx_skb()
823 void gigaset_if_init(struct cardstate *cs);
825 void gigaset_if_free(struct cardstate *cs);
827 void gigaset_if_receive(struct cardstate *cs,
|
| /linux-4.1.27/drivers/isdn/divert/ |
| H A D | isdn_divert.c | 61 struct call_struc *cs = (struct call_struc *) arg; deflect_timer_expire() local
64 del_timer(&cs->timer); /* delete active timer */ deflect_timer_expire()
67 switch (cs->akt_state) { deflect_timer_expire()
69 cs->ics.command = ISDN_CMD_HANGUP; /* cancel action */ deflect_timer_expire()
70 divert_if.ll_cmd(&cs->ics); deflect_timer_expire()
72 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ deflect_timer_expire()
73 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); deflect_timer_expire()
74 add_timer(&cs->timer); deflect_timer_expire()
79 cs->ics.command = ISDN_CMD_REDIR; /* protocol */ deflect_timer_expire()
80 strlcpy(cs->ics.parm.setup.phone, cs->deflect_dest, sizeof(cs->ics.parm.setup.phone)); deflect_timer_expire()
81 strcpy(cs->ics.parm.setup.eazmsn, "Testtext delayed"); deflect_timer_expire()
82 divert_if.ll_cmd(&cs->ics); deflect_timer_expire()
84 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ deflect_timer_expire()
85 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); deflect_timer_expire()
86 add_timer(&cs->timer); deflect_timer_expire()
93 if (cs->prev) deflect_timer_expire()
94 cs->prev->next = cs->next; /* forward link */ deflect_timer_expire()
96 divert_head = cs->next; deflect_timer_expire()
97 if (cs->next) deflect_timer_expire()
98 cs->next->prev = cs->prev; /* back link */ deflect_timer_expire()
100 kfree(cs); deflect_timer_expire()
119 struct call_struc *cs; cf_command() local
158 if (!(cs = kmalloc(sizeof(struct call_struc), GFP_ATOMIC))) cf_command()
160 init_timer(&cs->timer); cf_command()
161 cs->info[0] = '\0'; cf_command()
162 cs->timer.function = deflect_timer_expire; cf_command()
163 cs->timer.data = (ulong) cs; /* pointer to own structure */ cf_command()
164 cs->ics.driver = drvid; cf_command()
165 cs->ics.command = ISDN_CMD_PROT_IO; /* protocol specific io */ cf_command()
166 cs->ics.arg = DSS1_CMD_INVOKE; /* invoke supplementary service */ cf_command()
167 cs->ics.parm.dss1_io.proc = (mode == 1) ? 7 : (mode == 2) ? 11 : 8; /* operation */ cf_command()
168 cs->ics.parm.dss1_io.timeout = 4000; /* from ETS 300 207-1 */ cf_command()
169 cs->ics.parm.dss1_io.datalen = p - tmp; /* total len */ cf_command()
170 cs->ics.parm.dss1_io.data = tmp; /* start of buffer */ cf_command()
173 cs->ics.parm.dss1_io.ll_id = next_id++; /* id for callback */ cf_command()
175 *procid = cs->ics.parm.dss1_io.ll_id; cf_command()
177 sprintf(cs->info, "%d 0x%lx %s%s 0 %s %02x %d%s%s\n", cf_command()
179 cs->ics.parm.dss1_io.ll_id, cf_command()
181 divert_if.drv_to_name(cs->ics.driver), cf_command()
188 retval = divert_if.ll_cmd(&cs->ics); /* execute command */ cf_command()
191 cs->prev = NULL; cf_command()
193 cs->next = divert_head; cf_command()
194 divert_head = cs; cf_command()
197 kfree(cs); cf_command()
207 struct call_struc *cs; deflect_extern_action() local
213 cs = divert_head; /* start of parameter list */ deflect_extern_action()
214 while (cs) { deflect_extern_action()
215 if (cs->divert_id == callid) break; /* found */ deflect_extern_action()
216 cs = cs->next; deflect_extern_action()
218 if (!cs) return (-EINVAL); /* invalid callid */ deflect_extern_action()
220 ic.driver = cs->ics.driver; deflect_extern_action()
221 ic.arg = cs->ics.arg; deflect_extern_action()
223 if (cs->akt_state == DEFLECT_AUTODEL) return (i); /* no valid call */ deflect_extern_action()
226 del_timer(&cs->timer); deflect_extern_action()
230 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ deflect_extern_action()
231 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); deflect_extern_action()
232 add_timer(&cs->timer); deflect_extern_action()
237 if (cs->akt_state == DEFLECT_ALERT) return (0); deflect_extern_action()
239 del_timer(&cs->timer); deflect_extern_action()
243 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ deflect_extern_action()
244 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); deflect_extern_action()
245 add_timer(&cs->timer); deflect_extern_action()
248 cs->akt_state = DEFLECT_ALERT; deflect_extern_action()
252 del_timer(&cs->timer); deflect_extern_action()
253 strlcpy(cs->ics.parm.setup.phone, to_nr, sizeof(cs->ics.parm.setup.phone)); deflect_extern_action()
254 strcpy(cs->ics.parm.setup.eazmsn, "Testtext manual"); deflect_extern_action()
258 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ deflect_extern_action()
259 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); deflect_extern_action()
260 add_timer(&cs->timer); deflect_extern_action()
263 cs->akt_state = DEFLECT_ALERT; deflect_extern_action()
389 struct call_struc *cs = NULL; isdn_divert_icall() local
453 if (!(cs = kmalloc(sizeof(struct call_struc), GFP_ATOMIC))) isdn_divert_icall()
455 init_timer(&cs->timer); isdn_divert_icall()
456 cs->info[0] = '\0'; isdn_divert_icall()
457 cs->timer.function = deflect_timer_expire; isdn_divert_icall()
458 cs->timer.data = (ulong) cs; /* pointer to own structure */ isdn_divert_icall()
460 cs->ics = *ic; /* copy incoming data */ isdn_divert_icall()
461 if (!cs->ics.parm.setup.phone[0]) strcpy(cs->ics.parm.setup.phone, "0"); isdn_divert_icall()
462 if (!cs->ics.parm.setup.eazmsn[0]) strcpy(cs->ics.parm.setup.eazmsn, "0"); isdn_divert_icall()
463 cs->ics.parm.setup.screen = dv->rule.screen; isdn_divert_icall()
465 cs->timer.expires = jiffies + (HZ * dv->rule.waittime); isdn_divert_icall()
467 cs->timer.expires = jiffies + (HZ * extern_wait_max); isdn_divert_icall()
469 cs->timer.expires = 0; isdn_divert_icall()
470 cs->akt_state = dv->rule.action; isdn_divert_icall()
472 cs->divert_id = next_id++; /* new sequence number */ isdn_divert_icall()
474 cs->prev = NULL; isdn_divert_icall()
475 if (cs->akt_state == DEFLECT_ALERT) { isdn_divert_icall()
476 strcpy(cs->deflect_dest, dv->rule.to_nr); isdn_divert_icall()
477 if (!cs->timer.expires) { isdn_divert_icall()
482 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ isdn_divert_icall()
483 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); isdn_divert_icall()
488 cs->deflect_dest[0] = '\0'; isdn_divert_icall()
491 sprintf(cs->info, "%d 0x%lx %s %s %s %s 0x%x 0x%x %d %d %s\n", isdn_divert_icall()
492 cs->akt_state, isdn_divert_icall()
493 cs->divert_id, isdn_divert_icall()
494 divert_if.drv_to_name(cs->ics.driver), isdn_divert_icall()
496 cs->ics.parm.setup.phone, isdn_divert_icall()
497 cs->ics.parm.setup.eazmsn, isdn_divert_icall()
498 cs->ics.parm.setup.si1, isdn_divert_icall()
499 cs->ics.parm.setup.si2, isdn_divert_icall()
500 cs->ics.parm.setup.screen, isdn_divert_icall()
502 cs->deflect_dest); isdn_divert_icall()
505 put_info_buffer(cs->info); isdn_divert_icall()
506 kfree(cs); /* remove */ isdn_divert_icall()
517 if (cs) { isdn_divert_icall()
518 cs->prev = NULL; isdn_divert_icall()
520 cs->next = divert_head; isdn_divert_icall()
521 divert_head = cs; isdn_divert_icall()
522 if (cs->timer.expires) add_timer(&cs->timer); isdn_divert_icall()
525 put_info_buffer(cs->info); isdn_divert_icall()
534 struct call_struc *cs, *cs1; deleteprocs() local
538 cs = divert_head; deleteprocs()
540 while (cs) { deleteprocs()
541 del_timer(&cs->timer); deleteprocs()
542 cs1 = cs; deleteprocs()
543 cs = cs->next; deleteprocs()
593 static int interrogate_success(isdn_ctrl *ic, struct call_struc *cs) interrogate_success() argument
684 struct call_struc *cs, *cs1; prot_stat_callback() local
688 cs = divert_head; /* start of list */ prot_stat_callback()
690 while (cs) { prot_stat_callback()
691 if (ic->driver == cs->ics.driver) { prot_stat_callback()
692 switch (cs->ics.arg) { prot_stat_callback()
694 if ((cs->ics.parm.dss1_io.ll_id == ic->parm.dss1_io.ll_id) && prot_stat_callback()
695 (cs->ics.parm.dss1_io.hl_id == ic->parm.dss1_io.hl_id)) { prot_stat_callback()
698 sprintf(cs->info, "128 0x%lx 0x%x\n", prot_stat_callback()
701 put_info_buffer(cs->info); prot_stat_callback()
705 switch (cs->ics.parm.dss1_io.proc) { prot_stat_callback()
708 put_info_buffer(cs->info); prot_stat_callback()
712 i = interrogate_success(ic, cs); prot_stat_callback()
714 sprintf(cs->info, "%d 0x%lx %d\n", DIVERT_REPORT, prot_stat_callback()
716 put_info_buffer(cs->info); prot_stat_callback()
720 printk(KERN_WARNING "dss1_divert: unknown proc %d\n", cs->ics.parm.dss1_io.proc); prot_stat_callback()
730 cs1 = cs; /* remember structure */ prot_stat_callback()
731 cs = NULL; prot_stat_callback()
741 printk(KERN_WARNING "dss1_divert unknown cmd 0x%lx\n", cs->ics.arg); prot_stat_callback()
744 cs = cs->next; prot_stat_callback()
775 struct call_struc *cs, *cs1; isdn_divert_stat_callback() local
780 cs = divert_head; /* start of list */ isdn_divert_stat_callback()
781 while (cs) { isdn_divert_stat_callback()
782 if ((ic->driver == cs->ics.driver) && isdn_divert_stat_callback()
783 (ic->arg == cs->ics.arg)) { isdn_divert_stat_callback()
786 sprintf(cs->info, "129 0x%lx\n", cs->divert_id); isdn_divert_stat_callback()
787 del_timer(&cs->timer); isdn_divert_stat_callback()
788 cs->ics.driver = -1; isdn_divert_stat_callback()
792 sprintf(cs->info, "130 0x%lx %s\n", cs->divert_id, ic->parm.num); isdn_divert_stat_callback()
796 sprintf(cs->info, "131 0x%lx\n", cs->divert_id); isdn_divert_stat_callback()
797 del_timer(&cs->timer); isdn_divert_stat_callback()
798 cs->ics.driver = -1; isdn_divert_stat_callback()
802 sprintf(cs->info, "999 0x%lx 0x%x\n", cs->divert_id, (int)(ic->command)); isdn_divert_stat_callback()
805 put_info_buffer(cs->info); isdn_divert_stat_callback()
808 cs1 = cs; isdn_divert_stat_callback()
809 cs = cs->next; isdn_divert_stat_callback()
|
| /linux-4.1.27/arch/mips/bcm63xx/ |
| H A D | cs.c | 23 static int is_valid_cs(unsigned int cs) is_valid_cs() argument
25 if (cs > 6) is_valid_cs()
34 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) bcm63xx_set_cs_base() argument
39 if (!is_valid_cs(cs)) bcm63xx_set_cs_base()
54 bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); bcm63xx_set_cs_base()
65 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, bcm63xx_set_cs_timing() argument
71 if (!is_valid_cs(cs)) bcm63xx_set_cs_timing()
75 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_timing()
82 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_timing()
93 int bcm63xx_set_cs_param(unsigned int cs, u32 params) bcm63xx_set_cs_param() argument
98 if (!is_valid_cs(cs)) bcm63xx_set_cs_param()
102 if (cs == MPI_CS_PCMCIA_COMMON || bcm63xx_set_cs_param()
103 cs == MPI_CS_PCMCIA_ATTR || bcm63xx_set_cs_param()
104 cs == MPI_CS_PCMCIA_IO) bcm63xx_set_cs_param()
108 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_param()
114 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_param()
123 * set cs status (enable/disable)
125 int bcm63xx_set_cs_status(unsigned int cs, int enable) bcm63xx_set_cs_status() argument
130 if (!is_valid_cs(cs)) bcm63xx_set_cs_status()
134 val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); bcm63xx_set_cs_status()
139 bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); bcm63xx_set_cs_status()
|
| H A D | dev-pcmcia.c | 69 static int __init config_pcmcia_cs(unsigned int cs, config_pcmcia_cs() argument
74 ret = bcm63xx_set_cs_status(cs, 0); config_pcmcia_cs()
76 ret = bcm63xx_set_cs_base(cs, base, size); config_pcmcia_cs()
78 ret = bcm63xx_set_cs_status(cs, 1); config_pcmcia_cs()
83 unsigned int cs; member in struct:__anon1859
88 .cs = MPI_CS_PCMCIA_COMMON,
93 .cs = MPI_CS_PCMCIA_ATTR,
98 .cs = MPI_CS_PCMCIA_IO,
132 ret = config_pcmcia_cs(pcmcia_cs[i].cs, bcm63xx_pcmcia_register()
|
| H A D | dev-dsp.c | 45 val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1)); bcm63xx_dsp_register()
|
| /linux-4.1.27/arch/mips/include/asm/mach-bcm63xx/ |
| H A D | bcm63xx_cs.h | 4 int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
5 int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
7 int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
8 int bcm63xx_set_cs_status(unsigned int cs, int enable);
|
| H A D | bcm63xx_dev_dsp.h | 7 unsigned cs; member in struct:bcm63xx_dsp_platform_data
|
| /linux-4.1.27/tools/perf/util/ |
| H A D | comm.c | 15 static void comm_str__get(struct comm_str *cs) comm_str__get() argument
17 cs->ref++; comm_str__get()
20 static void comm_str__put(struct comm_str *cs) comm_str__put() argument
22 if (!--cs->ref) { comm_str__put()
23 rb_erase(&cs->rb_node, &comm_str_root); comm_str__put()
24 zfree(&cs->str); comm_str__put()
25 free(cs); comm_str__put()
31 struct comm_str *cs; comm_str__alloc() local
33 cs = zalloc(sizeof(*cs)); comm_str__alloc()
34 if (!cs) comm_str__alloc()
37 cs->str = strdup(str); comm_str__alloc()
38 if (!cs->str) { comm_str__alloc()
39 free(cs); comm_str__alloc()
43 return cs; comm_str__alloc()
|
| /linux-4.1.27/arch/powerpc/include/asm/ |
| H A D | exec.h | 2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
|
| H A D | runlatch.h | 2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
|
| /linux-4.1.27/arch/arm/mach-omap2/ |
| H A D | board-flash.c | 57 __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs) board_nor_init() argument
66 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1, board_nor_init()
71 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1, board_nor_init()
92 u8 nr_parts, u8 cs) board_onenand_init()
94 board_onenand_data.cs = cs; board_onenand_init()
136 __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, board_nand_init() argument
139 board_nand_data.cs = cs; board_nand_init()
151 * the various cs values.
155 u8 cs = 0; get_gpmc0_type() local
168 cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf; get_gpmc0_type()
173 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | get_gpmc0_type()
174 ((cs & 2) << 1) | ((cs & 1) << 3); get_gpmc0_type()
177 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); get_gpmc0_type()
180 return cs; get_gpmc0_type()
191 u8 cs = 0; board_flash_init() local
199 * for which cs configuration matches for 2430 SDP? board_flash_init()
203 pr_err("%s: Invalid chip select: %d\n", __func__, cs); board_flash_init()
208 while (cs < GPMC_CS_NUM) { board_flash_init()
209 switch (config_sel[cs]) { board_flash_init()
212 norcs = cs; board_flash_init()
216 nandcs = cs; board_flash_init()
220 onenandcs = cs; board_flash_init()
223 cs++; board_flash_init()
91 board_onenand_init(struct mtd_partition *onenand_parts, u8 nr_parts, u8 cs) board_onenand_init() argument
|
| H A D | gpmc-nand.c | 86 BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); gpmc_nand_init()
88 err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, gpmc_nand_init()
92 gpmc_nand_data->cs, err); gpmc_nand_init()
108 err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t, &s); gpmc_nand_init()
116 err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); gpmc_nand_init()
124 gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); gpmc_nand_init()
133 pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); gpmc_nand_init()
156 gpmc_cs_free(gpmc_nand_data->cs); gpmc_nand_init()
|
| H A D | board-flash.h | 42 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t);
46 u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t) board_nand_init()
55 u8 nr_parts, u8 cs);
58 u8 nr_parts, u8 cs) board_onenand_init()
45 board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type, struct gpmc_timings *gpmc_t) board_nand_init() argument
57 board_onenand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) board_onenand_init() argument
|
| H A D | gpmc-smsc911x.h | 18 int cs; member in struct:omap_smsc911x_platform_data
|
| H A D | gpmc-onenand.c | 292 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); omap2_onenand_setup_async()
296 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_async); omap2_onenand_setup_async()
330 ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync); omap2_onenand_setup_sync()
334 ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &onenand_sync); omap2_onenand_setup_sync()
387 err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, gpmc_onenand_init()
391 gpmc_onenand_data->cs, err); gpmc_onenand_init()
400 gpmc_cs_free(gpmc_onenand_data->cs); gpmc_onenand_init()
|
| /linux-4.1.27/arch/mips/include/asm/netlogic/xlr/ |
| H A D | flash.h | 37 #define FLASH_CSBASE_ADDR(cs) (cs)
38 #define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
39 #define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
40 #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
41 #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
48 #define FLASH_NAND_CLE(cs) (0x90 + (cs))
49 #define FLASH_NAND_ALE(cs) (0xa0 + (cs))
|
| /linux-4.1.27/kernel/time/ |
| H A D | clocksource.c | 120 static void __clocksource_change_rating(struct clocksource *cs, int rating);
137 static void __clocksource_unstable(struct clocksource *cs) __clocksource_unstable() argument
139 cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG); __clocksource_unstable()
140 cs->flags |= CLOCK_SOURCE_UNSTABLE; __clocksource_unstable()
147 * @cs: clocksource to be marked unstable
154 void clocksource_mark_unstable(struct clocksource *cs) clocksource_mark_unstable() argument
159 if (!(cs->flags & CLOCK_SOURCE_UNSTABLE)) { clocksource_mark_unstable()
160 if (list_empty(&cs->wd_list)) clocksource_mark_unstable()
161 list_add(&cs->wd_list, &watchdog_list); clocksource_mark_unstable()
162 __clocksource_unstable(cs); clocksource_mark_unstable()
169 struct clocksource *cs; clocksource_watchdog() local
180 list_for_each_entry(cs, &watchdog_list, wd_list) { clocksource_watchdog()
183 if (cs->flags & CLOCK_SOURCE_UNSTABLE) { clocksource_watchdog()
190 csnow = cs->read(cs); clocksource_watchdog()
195 if (!(cs->flags & CLOCK_SOURCE_WATCHDOG) || clocksource_watchdog()
197 cs->flags |= CLOCK_SOURCE_WATCHDOG; clocksource_watchdog()
198 cs->wd_last = wdnow; clocksource_watchdog()
199 cs->cs_last = csnow; clocksource_watchdog()
203 delta = clocksource_delta(wdnow, cs->wd_last, watchdog->mask); clocksource_watchdog()
207 delta = clocksource_delta(csnow, cs->cs_last, cs->mask); clocksource_watchdog()
208 cs_nsec = clocksource_cyc2ns(delta, cs->mult, cs->shift); clocksource_watchdog()
209 wdlast = cs->wd_last; /* save these in case we print them */ clocksource_watchdog()
210 cslast = cs->cs_last; clocksource_watchdog()
211 cs->cs_last = csnow; clocksource_watchdog()
212 cs->wd_last = wdnow; clocksource_watchdog()
219 pr_warn("timekeeping watchdog: Marking clocksource '%s' as unstable, because the skew is too large:\n", cs->name); clocksource_watchdog()
223 cs->name, csnow, cslast, cs->mask); clocksource_watchdog()
224 __clocksource_unstable(cs); clocksource_watchdog()
228 if (!(cs->flags & CLOCK_SOURCE_VALID_FOR_HRES) && clocksource_watchdog()
229 (cs->flags & CLOCK_SOURCE_IS_CONTINUOUS) && clocksource_watchdog()
232 cs->flags |= CLOCK_SOURCE_VALID_FOR_HRES; clocksource_watchdog()
249 if (cs != curr_clocksource) { clocksource_watchdog()
250 cs->flags |= CLOCK_SOURCE_RESELECT; clocksource_watchdog()
299 struct clocksource *cs; clocksource_reset_watchdog() local
301 list_for_each_entry(cs, &watchdog_list, wd_list) clocksource_reset_watchdog()
302 cs->flags &= ~CLOCK_SOURCE_WATCHDOG; clocksource_reset_watchdog()
310 static void clocksource_enqueue_watchdog(struct clocksource *cs) clocksource_enqueue_watchdog() argument
315 if (cs->flags & CLOCK_SOURCE_MUST_VERIFY) { clocksource_enqueue_watchdog()
316 /* cs is a clocksource to be watched. */ clocksource_enqueue_watchdog()
317 list_add(&cs->wd_list, &watchdog_list); clocksource_enqueue_watchdog()
318 cs->flags &= ~CLOCK_SOURCE_WATCHDOG; clocksource_enqueue_watchdog()
320 /* cs is a watchdog. */ clocksource_enqueue_watchdog()
321 if (cs->flags & CLOCK_SOURCE_IS_CONTINUOUS) clocksource_enqueue_watchdog()
322 cs->flags |= CLOCK_SOURCE_VALID_FOR_HRES; clocksource_enqueue_watchdog()
324 if (!watchdog || cs->rating > watchdog->rating) { clocksource_enqueue_watchdog()
325 watchdog = cs; clocksource_enqueue_watchdog()
335 static void clocksource_dequeue_watchdog(struct clocksource *cs) clocksource_dequeue_watchdog() argument
340 if (cs != watchdog) { clocksource_dequeue_watchdog()
341 if (cs->flags & CLOCK_SOURCE_MUST_VERIFY) { clocksource_dequeue_watchdog()
342 /* cs is a watched clocksource. */ clocksource_dequeue_watchdog()
343 list_del_init(&cs->wd_list); clocksource_dequeue_watchdog()
353 struct clocksource *cs, *tmp; __clocksource_watchdog_kthread() local
359 list_for_each_entry_safe(cs, tmp, &watchdog_list, wd_list) { __clocksource_watchdog_kthread()
360 if (cs->flags & CLOCK_SOURCE_UNSTABLE) { __clocksource_watchdog_kthread()
361 list_del_init(&cs->wd_list); __clocksource_watchdog_kthread()
362 list_add(&cs->wd_list, &unstable); __clocksource_watchdog_kthread()
365 if (cs->flags & CLOCK_SOURCE_RESELECT) { __clocksource_watchdog_kthread()
366 cs->flags &= ~CLOCK_SOURCE_RESELECT; __clocksource_watchdog_kthread()
375 list_for_each_entry_safe(cs, tmp, &unstable, wd_list) { __clocksource_watchdog_kthread()
376 list_del_init(&cs->wd_list); __clocksource_watchdog_kthread()
377 __clocksource_change_rating(cs, 0); __clocksource_watchdog_kthread()
391 static bool clocksource_is_watchdog(struct clocksource *cs) clocksource_is_watchdog() argument
393 return cs == watchdog; clocksource_is_watchdog()
398 static void clocksource_enqueue_watchdog(struct clocksource *cs) clocksource_enqueue_watchdog() argument
400 if (cs->flags & CLOCK_SOURCE_IS_CONTINUOUS) clocksource_enqueue_watchdog()
401 cs->flags |= CLOCK_SOURCE_VALID_FOR_HRES; clocksource_enqueue_watchdog()
404 static inline void clocksource_dequeue_watchdog(struct clocksource *cs) { } clocksource_resume_watchdog() argument
407 static bool clocksource_is_watchdog(struct clocksource *cs) { return false; } clocksource_mark_unstable() argument
408 void clocksource_mark_unstable(struct clocksource *cs) { } clocksource_mark_unstable() argument
417 struct clocksource *cs; clocksource_suspend() local
419 list_for_each_entry_reverse(cs, &clocksource_list, list) clocksource_suspend()
420 if (cs->suspend) clocksource_suspend()
421 cs->suspend(cs); clocksource_suspend()
429 struct clocksource *cs; clocksource_resume() local
431 list_for_each_entry(cs, &clocksource_list, list) clocksource_resume()
432 if (cs->resume) clocksource_resume()
433 cs->resume(cs); clocksource_resume()
452 * @cs: Pointer to clocksource
455 static u32 clocksource_max_adjustment(struct clocksource *cs) clocksource_max_adjustment() argument
461 ret = (u64)cs->mult * 11; clocksource_max_adjustment()
513 * @cs: Pointer to clocksource to be updated
516 static inline void clocksource_update_max_deferment(struct clocksource *cs) clocksource_update_max_deferment() argument
518 cs->max_idle_ns = clocks_calc_max_nsecs(cs->mult, cs->shift, clocksource_update_max_deferment()
519 cs->maxadj, cs->mask, clocksource_update_max_deferment()
520 &cs->max_cycles); clocksource_update_max_deferment()
527 struct clocksource *cs; clocksource_find_best() local
537 list_for_each_entry(cs, &clocksource_list, list) { clocksource_find_best()
538 if (skipcur && cs == curr_clocksource) clocksource_find_best()
540 if (oneshot && !(cs->flags & CLOCK_SOURCE_VALID_FOR_HRES)) clocksource_find_best()
542 return cs; clocksource_find_best()
550 struct clocksource *best, *cs; __clocksource_select() local
558 list_for_each_entry(cs, &clocksource_list, list) { __clocksource_select()
559 if (skipcur && cs == curr_clocksource) __clocksource_select()
561 if (strcmp(cs->name, override_name) != 0) __clocksource_select()
568 if (!(cs->flags & CLOCK_SOURCE_VALID_FOR_HRES) && oneshot) { __clocksource_select()
572 "HRT/NOHZ mode\n", cs->name); __clocksource_select()
576 best = cs; __clocksource_select()
636 static void clocksource_enqueue(struct clocksource *cs) clocksource_enqueue() argument
643 if (tmp->rating >= cs->rating) clocksource_enqueue()
645 list_add(&cs->list, entry); clocksource_enqueue()
650 * @cs: clocksource to be registered
660 void __clocksource_update_freq_scale(struct clocksource *cs, u32 scale, u32 freq) __clocksource_update_freq_scale() argument
678 sec = cs->mask; __clocksource_update_freq_scale()
683 else if (sec > 600 && cs->mask > UINT_MAX) __clocksource_update_freq_scale()
686 clocks_calc_mult_shift(&cs->mult, &cs->shift, freq, __clocksource_update_freq_scale()
693 cs->maxadj = clocksource_max_adjustment(cs); __clocksource_update_freq_scale()
694 while (freq && ((cs->mult + cs->maxadj < cs->mult) __clocksource_update_freq_scale()
695 || (cs->mult - cs->maxadj > cs->mult))) { __clocksource_update_freq_scale()
696 cs->mult >>= 1; __clocksource_update_freq_scale()
697 cs->shift--; __clocksource_update_freq_scale()
698 cs->maxadj = clocksource_max_adjustment(cs); __clocksource_update_freq_scale()
705 WARN_ONCE(cs->mult + cs->maxadj < cs->mult, __clocksource_update_freq_scale()
707 cs->name); __clocksource_update_freq_scale()
709 clocksource_update_max_deferment(cs); __clocksource_update_freq_scale()
712 cs->name, cs->mask, cs->max_cycles, cs->max_idle_ns); __clocksource_update_freq_scale()
718 * @cs: clocksource to be registered
727 int __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq) __clocksource_register_scale() argument
731 __clocksource_update_freq_scale(cs, scale, freq); __clocksource_register_scale()
735 clocksource_enqueue(cs); __clocksource_register_scale()
736 clocksource_enqueue_watchdog(cs); __clocksource_register_scale()
743 static void __clocksource_change_rating(struct clocksource *cs, int rating) __clocksource_change_rating() argument
745 list_del(&cs->list); __clocksource_change_rating()
746 cs->rating = rating; __clocksource_change_rating()
747 clocksource_enqueue(cs); __clocksource_change_rating()
752 * @cs: clocksource to be changed
755 void clocksource_change_rating(struct clocksource *cs, int rating) clocksource_change_rating() argument
758 __clocksource_change_rating(cs, rating); clocksource_change_rating()
765 * Unbind clocksource @cs. Called with clocksource_mutex held
767 static int clocksource_unbind(struct clocksource *cs) clocksource_unbind() argument
773 if (clocksource_is_watchdog(cs)) clocksource_unbind()
776 if (cs == curr_clocksource) { clocksource_unbind()
779 if (curr_clocksource == cs) clocksource_unbind()
782 clocksource_dequeue_watchdog(cs); clocksource_unbind()
783 list_del_init(&cs->list); clocksource_unbind()
789 * @cs: clocksource to be unregistered
791 int clocksource_unregister(struct clocksource *cs) clocksource_unregister() argument
796 if (!list_empty(&cs->list)) clocksource_unregister()
797 ret = clocksource_unbind(cs); clocksource_unregister()
882 struct clocksource *cs; sysfs_unbind_clocksource() local
892 list_for_each_entry(cs, &clocksource_list, list) { sysfs_unbind_clocksource()
893 if (strcmp(cs->name, name)) sysfs_unbind_clocksource()
895 ret = clocksource_unbind(cs); sysfs_unbind_clocksource()
|
| /linux-4.1.27/drivers/clocksource/ |
| H A D | mmio.c | 56 struct clocksource_mmio *cs; clocksource_mmio_init() local
61 cs = kzalloc(sizeof(struct clocksource_mmio), GFP_KERNEL); clocksource_mmio_init()
62 if (!cs) clocksource_mmio_init()
65 cs->reg = base; clocksource_mmio_init()
66 cs->clksrc.name = name; clocksource_mmio_init()
67 cs->clksrc.rating = rating; clocksource_mmio_init()
68 cs->clksrc.read = read; clocksource_mmio_init()
69 cs->clksrc.mask = CLOCKSOURCE_MASK(bits); clocksource_mmio_init()
70 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; clocksource_mmio_init()
72 return clocksource_register_hz(&cs->clksrc, hz); clocksource_mmio_init()
|
| H A D | em_sti.c | 45 struct clocksource cs; member in struct:em_sti_priv
196 static struct em_sti_priv *cs_to_em_sti(struct clocksource *cs) cs_to_em_sti() argument
198 return container_of(cs, struct em_sti_priv, cs); cs_to_em_sti()
201 static cycle_t em_sti_clocksource_read(struct clocksource *cs) em_sti_clocksource_read() argument
203 return em_sti_count(cs_to_em_sti(cs)); em_sti_clocksource_read()
206 static int em_sti_clocksource_enable(struct clocksource *cs) em_sti_clocksource_enable() argument
209 struct em_sti_priv *p = cs_to_em_sti(cs); em_sti_clocksource_enable()
213 __clocksource_update_freq_hz(cs, p->rate); em_sti_clocksource_enable()
217 static void em_sti_clocksource_disable(struct clocksource *cs) em_sti_clocksource_disable() argument
219 em_sti_stop(cs_to_em_sti(cs), USER_CLOCKSOURCE); em_sti_clocksource_disable()
222 static void em_sti_clocksource_resume(struct clocksource *cs) em_sti_clocksource_resume() argument
224 em_sti_clocksource_enable(cs); em_sti_clocksource_resume()
229 struct clocksource *cs = &p->cs; em_sti_register_clocksource() local
231 memset(cs, 0, sizeof(*cs)); em_sti_register_clocksource()
232 cs->name = dev_name(&p->pdev->dev); em_sti_register_clocksource()
233 cs->rating = 200; em_sti_register_clocksource()
234 cs->read = em_sti_clocksource_read; em_sti_register_clocksource()
235 cs->enable = em_sti_clocksource_enable; em_sti_register_clocksource()
236 cs->disable = em_sti_clocksource_disable; em_sti_register_clocksource()
237 cs->suspend = em_sti_clocksource_disable; em_sti_register_clocksource()
238 cs->resume = em_sti_clocksource_resume; em_sti_register_clocksource()
239 cs->mask = CLOCKSOURCE_MASK(48); em_sti_register_clocksource()
240 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; em_sti_register_clocksource()
245 clocksource_register_hz(cs, 1); em_sti_register_clocksource()
|
| H A D | timer-sun5i.c | 153 struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc); sun5i_clksrc_read() local
155 return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1)); sun5i_clksrc_read()
163 struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer); sun5i_rate_cb_clksrc() local
167 clocksource_unregister(&cs->clksrc); sun5i_rate_cb_clksrc()
171 clocksource_register_hz(&cs->clksrc, ndata->new_rate); sun5i_rate_cb_clksrc()
185 struct sun5i_timer_clksrc *cs; sun5i_setup_clocksource() local
189 cs = kzalloc(sizeof(*cs), GFP_KERNEL); sun5i_setup_clocksource()
190 if (!cs) sun5i_setup_clocksource()
201 cs->timer.base = base; sun5i_setup_clocksource()
202 cs->timer.clk = clk; sun5i_setup_clocksource()
203 cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc; sun5i_setup_clocksource()
204 cs->timer.clk_rate_cb.next = NULL; sun5i_setup_clocksource()
206 ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb); sun5i_setup_clocksource()
216 cs->clksrc.name = node->name; sun5i_setup_clocksource()
217 cs->clksrc.rating = 340; sun5i_setup_clocksource()
218 cs->clksrc.read = sun5i_clksrc_read; sun5i_setup_clocksource()
219 cs->clksrc.mask = CLOCKSOURCE_MASK(32); sun5i_setup_clocksource()
220 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; sun5i_setup_clocksource()
222 ret = clocksource_register_hz(&cs->clksrc, rate); sun5i_setup_clocksource()
231 clk_notifier_unregister(clk, &cs->timer.clk_rate_cb); sun5i_setup_clocksource()
235 kfree(cs); sun5i_setup_clocksource()
|
| H A D | sh_tmu.c | 52 struct clocksource cs; member in struct:sh_tmu_channel
253 static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) cs_to_sh_tmu() argument
255 return container_of(cs, struct sh_tmu_channel, cs); cs_to_sh_tmu()
258 static cycle_t sh_tmu_clocksource_read(struct clocksource *cs) sh_tmu_clocksource_read() argument
260 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); sh_tmu_clocksource_read()
265 static int sh_tmu_clocksource_enable(struct clocksource *cs) sh_tmu_clocksource_enable() argument
267 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); sh_tmu_clocksource_enable()
275 __clocksource_update_freq_hz(cs, ch->rate); sh_tmu_clocksource_enable()
282 static void sh_tmu_clocksource_disable(struct clocksource *cs) sh_tmu_clocksource_disable() argument
284 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); sh_tmu_clocksource_disable()
293 static void sh_tmu_clocksource_suspend(struct clocksource *cs) sh_tmu_clocksource_suspend() argument
295 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); sh_tmu_clocksource_suspend()
306 static void sh_tmu_clocksource_resume(struct clocksource *cs) sh_tmu_clocksource_resume() argument
308 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); sh_tmu_clocksource_resume()
322 struct clocksource *cs = &ch->cs; sh_tmu_register_clocksource() local
324 cs->name = name; sh_tmu_register_clocksource()
325 cs->rating = 200; sh_tmu_register_clocksource()
326 cs->read = sh_tmu_clocksource_read; sh_tmu_register_clocksource()
327 cs->enable = sh_tmu_clocksource_enable; sh_tmu_register_clocksource()
328 cs->disable = sh_tmu_clocksource_disable; sh_tmu_register_clocksource()
329 cs->suspend = sh_tmu_clocksource_suspend; sh_tmu_register_clocksource()
330 cs->resume = sh_tmu_clocksource_resume; sh_tmu_register_clocksource()
331 cs->mask = CLOCKSOURCE_MASK(32); sh_tmu_register_clocksource()
332 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; sh_tmu_register_clocksource()
338 clocksource_register_hz(cs, 1); sh_tmu_register_clocksource()
|
| H A D | dw_apb_timer_of.c | 88 struct dw_apb_clocksource *cs; add_clocksource() local
93 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); add_clocksource()
94 if (!cs) add_clocksource()
97 dw_apb_clocksource_start(cs); add_clocksource()
98 dw_apb_clocksource_register(cs); add_clocksource()
|
| H A D | dw_apb_timer.c | 47 clocksource_to_dw_apb_clocksource(struct clocksource *cs) clocksource_to_dw_apb_clocksource() argument
49 return container_of(cs, struct dw_apb_clocksource, cs); clocksource_to_dw_apb_clocksource()
319 static cycle_t __apbt_read_clocksource(struct clocksource *cs) __apbt_read_clocksource() argument
323 clocksource_to_dw_apb_clocksource(cs); __apbt_read_clocksource()
330 static void apbt_restart_clocksource(struct clocksource *cs) apbt_restart_clocksource() argument
333 clocksource_to_dw_apb_clocksource(cs); apbt_restart_clocksource()
361 dw_cs->cs.name = name; dw_apb_clocksource_init()
362 dw_cs->cs.rating = rating; dw_apb_clocksource_init()
363 dw_cs->cs.read = __apbt_read_clocksource; dw_apb_clocksource_init()
364 dw_cs->cs.mask = CLOCKSOURCE_MASK(32); dw_apb_clocksource_init()
365 dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; dw_apb_clocksource_init()
366 dw_cs->cs.resume = apbt_restart_clocksource; dw_apb_clocksource_init()
378 clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq); dw_apb_clocksource_register()
|
| H A D | qcom-timer.c | 106 static notrace cycle_t msm_read_timer_count(struct clocksource *cs) msm_read_timer_count() argument
196 struct clocksource *cs = &msm_clocksource; msm_timer_init() local
227 res = clocksource_register_hz(cs, dgt_hz); msm_timer_init()
308 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) msm_read_timer_count_shift() argument
314 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; msm_read_timer_count_shift()
319 struct clocksource *cs = &msm_clocksource; msm7x01_timer_init() local
323 cs->read = msm_read_timer_count_shift; msm7x01_timer_init()
324 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); msm7x01_timer_init()
|
| H A D | sh_cmt.c | 109 struct clocksource cs; member in struct:sh_cmt_channel
610 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) cs_to_sh_cmt() argument
612 return container_of(cs, struct sh_cmt_channel, cs); cs_to_sh_cmt()
615 static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) sh_cmt_clocksource_read() argument
617 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); sh_cmt_clocksource_read()
633 static int sh_cmt_clocksource_enable(struct clocksource *cs) sh_cmt_clocksource_enable() argument
636 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); sh_cmt_clocksource_enable()
644 __clocksource_update_freq_hz(cs, ch->rate); sh_cmt_clocksource_enable()
650 static void sh_cmt_clocksource_disable(struct clocksource *cs) sh_cmt_clocksource_disable() argument
652 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); sh_cmt_clocksource_disable()
660 static void sh_cmt_clocksource_suspend(struct clocksource *cs) sh_cmt_clocksource_suspend() argument
662 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); sh_cmt_clocksource_suspend()
668 static void sh_cmt_clocksource_resume(struct clocksource *cs) sh_cmt_clocksource_resume() argument
670 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); sh_cmt_clocksource_resume()
679 struct clocksource *cs = &ch->cs; sh_cmt_register_clocksource() local
681 cs->name = name; sh_cmt_register_clocksource()
682 cs->rating = 125; sh_cmt_register_clocksource()
683 cs->read = sh_cmt_clocksource_read; sh_cmt_register_clocksource()
684 cs->enable = sh_cmt_clocksource_enable; sh_cmt_register_clocksource()
685 cs->disable = sh_cmt_clocksource_disable; sh_cmt_register_clocksource()
686 cs->suspend = sh_cmt_clocksource_suspend; sh_cmt_register_clocksource()
687 cs->resume = sh_cmt_clocksource_resume; sh_cmt_register_clocksource()
688 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); sh_cmt_register_clocksource()
689 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; sh_cmt_register_clocksource()
695 clocksource_register_hz(cs, 1); sh_cmt_register_clocksource()
|
| /linux-4.1.27/arch/sh/include/asm/ |
| H A D | spi.h | 10 void (*chip_select)(struct sh_spi_info *spi, int cs, int state);
|
| /linux-4.1.27/arch/mips/include/asm/mach-au1x00/ |
| H A D | au1550_spi.h | 11 void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
12 void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
|
| /linux-4.1.27/arch/m68k/include/asm/ |
| H A D | string.h | 42 static inline int strcmp(const char *cs, const char *ct) strcmp() argument
47 "1: move.b (%0)+,%2\n" /* get *cs */ strcmp()
50 " tst.b %2\n" /* at end of cs? */ strcmp()
53 "2: sub.b -(%1),%2\n" /* *cs - *ct */ strcmp()
55 : "+a" (cs), "+a" (ct), "=d" (res)); strcmp()
|
| /linux-4.1.27/arch/m68k/lib/ |
| H A D | memset.c | 21 char *cs = s; memset() local
22 *cs++ = c; memset()
23 s = cs; memset()
69 char *cs = s; memset() local
70 *cs = c; memset()
|
| /linux-4.1.27/fs/fuse/ |
| H A D | dev.c | 724 static void fuse_copy_init(struct fuse_copy_state *cs, fuse_copy_init() argument
729 memset(cs, 0, sizeof(*cs)); fuse_copy_init()
730 cs->fc = fc; fuse_copy_init()
731 cs->write = write; fuse_copy_init()
732 cs->iter = iter; fuse_copy_init()
736 static void fuse_copy_finish(struct fuse_copy_state *cs) fuse_copy_finish() argument
738 if (cs->currbuf) { fuse_copy_finish()
739 struct pipe_buffer *buf = cs->currbuf; fuse_copy_finish()
741 if (cs->write) fuse_copy_finish()
742 buf->len = PAGE_SIZE - cs->len; fuse_copy_finish()
743 cs->currbuf = NULL; fuse_copy_finish()
744 } else if (cs->pg) { fuse_copy_finish()
745 if (cs->write) { fuse_copy_finish()
746 flush_dcache_page(cs->pg); fuse_copy_finish()
747 set_page_dirty_lock(cs->pg); fuse_copy_finish()
749 put_page(cs->pg); fuse_copy_finish()
751 cs->pg = NULL; fuse_copy_finish()
758 static int fuse_copy_fill(struct fuse_copy_state *cs) fuse_copy_fill() argument
763 unlock_request(cs->fc, cs->req); fuse_copy_fill()
764 fuse_copy_finish(cs); fuse_copy_fill()
765 if (cs->pipebufs) { fuse_copy_fill()
766 struct pipe_buffer *buf = cs->pipebufs; fuse_copy_fill()
768 if (!cs->write) { fuse_copy_fill()
769 err = buf->ops->confirm(cs->pipe, buf); fuse_copy_fill()
773 BUG_ON(!cs->nr_segs); fuse_copy_fill()
774 cs->currbuf = buf; fuse_copy_fill()
775 cs->pg = buf->page; fuse_copy_fill()
776 cs->offset = buf->offset; fuse_copy_fill()
777 cs->len = buf->len; fuse_copy_fill()
778 cs->pipebufs++; fuse_copy_fill()
779 cs->nr_segs--; fuse_copy_fill()
781 if (cs->nr_segs == cs->pipe->buffers) fuse_copy_fill()
792 cs->currbuf = buf; fuse_copy_fill()
793 cs->pg = page; fuse_copy_fill()
794 cs->offset = 0; fuse_copy_fill()
795 cs->len = PAGE_SIZE; fuse_copy_fill()
796 cs->pipebufs++; fuse_copy_fill()
797 cs->nr_segs++; fuse_copy_fill()
801 err = iov_iter_get_pages(cs->iter, &page, PAGE_SIZE, 1, &off); fuse_copy_fill()
805 cs->len = err; fuse_copy_fill()
806 cs->offset = off; fuse_copy_fill()
807 cs->pg = page; fuse_copy_fill()
808 cs->offset = off; fuse_copy_fill()
809 iov_iter_advance(cs->iter, err); fuse_copy_fill()
812 return lock_request(cs->fc, cs->req); fuse_copy_fill()
816 static int fuse_copy_do(struct fuse_copy_state *cs, void **val, unsigned *size) fuse_copy_do() argument
818 unsigned ncpy = min(*size, cs->len); fuse_copy_do()
820 void *pgaddr = kmap_atomic(cs->pg); fuse_copy_do()
821 void *buf = pgaddr + cs->offset; fuse_copy_do()
823 if (cs->write) fuse_copy_do()
832 cs->len -= ncpy; fuse_copy_do()
833 cs->offset += ncpy; fuse_copy_do()
856 static int fuse_try_move_page(struct fuse_copy_state *cs, struct page **pagep) fuse_try_move_page() argument
861 struct pipe_buffer *buf = cs->pipebufs; fuse_try_move_page()
863 unlock_request(cs->fc, cs->req); fuse_try_move_page()
864 fuse_copy_finish(cs); fuse_try_move_page()
866 err = buf->ops->confirm(cs->pipe, buf); fuse_try_move_page()
870 BUG_ON(!cs->nr_segs); fuse_try_move_page()
871 cs->currbuf = buf; fuse_try_move_page()
872 cs->len = buf->len; fuse_try_move_page()
873 cs->pipebufs++; fuse_try_move_page()
874 cs->nr_segs--; fuse_try_move_page()
876 if (cs->len != PAGE_SIZE) fuse_try_move_page()
879 if (buf->ops->steal(cs->pipe, buf) != 0) fuse_try_move_page()
917 spin_lock(&cs->fc->lock); fuse_try_move_page()
918 if (cs->req->aborted) fuse_try_move_page()
922 spin_unlock(&cs->fc->lock); fuse_try_move_page()
932 cs->len = 0; fuse_try_move_page()
939 cs->pg = buf->page; fuse_try_move_page()
940 cs->offset = buf->offset; fuse_try_move_page()
942 err = lock_request(cs->fc, cs->req); fuse_try_move_page()
949 static int fuse_ref_page(struct fuse_copy_state *cs, struct page *page, fuse_ref_page() argument
954 if (cs->nr_segs == cs->pipe->buffers) fuse_ref_page()
957 unlock_request(cs->fc, cs->req); fuse_ref_page()
958 fuse_copy_finish(cs); fuse_ref_page()
960 buf = cs->pipebufs; fuse_ref_page()
966 cs->pipebufs++; fuse_ref_page()
967 cs->nr_segs++; fuse_ref_page()
968 cs->len = 0; fuse_ref_page()
977 static int fuse_copy_page(struct fuse_copy_state *cs, struct page **pagep, fuse_copy_page() argument
987 if (cs->write && cs->pipebufs && page) { fuse_copy_page()
988 return fuse_ref_page(cs, page, offset, count); fuse_copy_page()
989 } else if (!cs->len) { fuse_copy_page()
990 if (cs->move_pages && page && fuse_copy_page()
992 err = fuse_try_move_page(cs, pagep); fuse_copy_page()
996 err = fuse_copy_fill(cs); fuse_copy_page()
1004 offset += fuse_copy_do(cs, &buf, &count); fuse_copy_page()
1007 offset += fuse_copy_do(cs, NULL, &count); fuse_copy_page()
1009 if (page && !cs->write) fuse_copy_page()
1015 static int fuse_copy_pages(struct fuse_copy_state *cs, unsigned nbytes, fuse_copy_pages() argument
1019 struct fuse_req *req = cs->req; fuse_copy_pages()
1026 err = fuse_copy_page(cs, &req->pages[i], offset, count, fuse_copy_pages()
1037 static int fuse_copy_one(struct fuse_copy_state *cs, void *val, unsigned size) fuse_copy_one() argument
1040 if (!cs->len) { fuse_copy_one()
1041 int err = fuse_copy_fill(cs); fuse_copy_one()
1045 fuse_copy_do(cs, &val, &size); fuse_copy_one()
1051 static int fuse_copy_args(struct fuse_copy_state *cs, unsigned numargs, fuse_copy_args() argument
1061 err = fuse_copy_pages(cs, arg->size, zeroing); fuse_copy_args()
1063 err = fuse_copy_one(cs, arg->value, arg->size); fuse_copy_args()
1108 static int fuse_read_interrupt(struct fuse_conn *fc, struct fuse_copy_state *cs,
1130 err = fuse_copy_one(cs, &ih, sizeof(ih));
1132 err = fuse_copy_one(cs, &arg, sizeof(arg));
1133 fuse_copy_finish(cs); variable
1161 struct fuse_copy_state *cs,
1182 err = fuse_copy_one(cs, &ih, sizeof(ih));
1184 err = fuse_copy_one(cs, &arg, sizeof(arg));
1185 fuse_copy_finish(cs); variable
1194 struct fuse_copy_state *cs, size_t nbytes)
1219 err = fuse_copy_one(cs, &ih, sizeof(ih));
1221 err = fuse_copy_one(cs, &arg, sizeof(arg));
1227 err = fuse_copy_one(cs, &forget->forget_one,
1234 fuse_copy_finish(cs); variable
1242 static int fuse_read_forget(struct fuse_conn *fc, struct fuse_copy_state *cs,
1247 return fuse_read_single_forget(fc, cs, nbytes);
1249 return fuse_read_batch_forget(fc, cs, nbytes);
1262 struct fuse_copy_state *cs, size_t nbytes) fuse_dev_do_read()
1287 return fuse_read_interrupt(fc, cs, nbytes, req); fuse_dev_do_read()
1292 return fuse_read_forget(fc, cs, nbytes); fuse_dev_do_read()
1314 cs->req = req; fuse_dev_do_read()
1315 err = fuse_copy_one(cs, &in->h, sizeof(in->h)); fuse_dev_do_read()
1317 err = fuse_copy_args(cs, in->numargs, in->argpages, fuse_dev_do_read()
1319 fuse_copy_finish(cs); fuse_dev_do_read()
1360 struct fuse_copy_state cs; fuse_dev_read() local
1369 fuse_copy_init(&cs, fc, 1, to); fuse_dev_read()
1371 return fuse_dev_do_read(fc, file, &cs, iov_iter_count(to)); fuse_dev_read()
1382 struct fuse_copy_state cs; fuse_dev_splice_read() local
1391 fuse_copy_init(&cs, fc, 1, NULL); fuse_dev_splice_read()
1392 cs.pipebufs = bufs; fuse_dev_splice_read()
1393 cs.pipe = pipe; fuse_dev_splice_read()
1394 ret = fuse_dev_do_read(fc, in, &cs, len); fuse_dev_splice_read()
1408 if (pipe->nrbufs + cs.nr_segs > pipe->buffers) { fuse_dev_splice_read()
1413 while (page_nr < cs.nr_segs) { fuse_dev_splice_read()
1445 for (; page_nr < cs.nr_segs; page_nr++) fuse_dev_splice_read()
1453 struct fuse_copy_state *cs) fuse_notify_poll()
1461 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_poll()
1465 fuse_copy_finish(cs); fuse_notify_poll()
1469 fuse_copy_finish(cs); fuse_notify_poll()
1474 struct fuse_copy_state *cs) fuse_notify_inval_inode()
1482 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_inval_inode()
1485 fuse_copy_finish(cs); fuse_notify_inval_inode()
1497 fuse_copy_finish(cs); fuse_notify_inval_inode()
1502 struct fuse_copy_state *cs) fuse_notify_inval_entry()
1517 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_inval_entry()
1531 err = fuse_copy_one(cs, buf, outarg.namelen + 1); fuse_notify_inval_entry()
1534 fuse_copy_finish(cs); fuse_notify_inval_entry()
1548 fuse_copy_finish(cs); fuse_notify_inval_entry()
1553 struct fuse_copy_state *cs) fuse_notify_delete()
1568 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_delete()
1582 err = fuse_copy_one(cs, buf, outarg.namelen + 1); fuse_notify_delete()
1585 fuse_copy_finish(cs); fuse_notify_delete()
1600 fuse_copy_finish(cs); fuse_notify_delete()
1605 struct fuse_copy_state *cs) fuse_notify_store()
1622 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_store()
1664 err = fuse_copy_page(cs, &page, offset, this_num, 0); fuse_notify_store()
1686 fuse_copy_finish(cs); fuse_notify_store()
1765 struct fuse_copy_state *cs) fuse_notify_retrieve()
1775 err = fuse_copy_one(cs, &outarg, sizeof(outarg)); fuse_notify_retrieve()
1779 fuse_copy_finish(cs); fuse_notify_retrieve()
1797 fuse_copy_finish(cs); fuse_notify_retrieve()
1802 unsigned int size, struct fuse_copy_state *cs) fuse_notify()
1805 cs->move_pages = 0; fuse_notify()
1809 return fuse_notify_poll(fc, size, cs); fuse_notify()
1812 return fuse_notify_inval_inode(fc, size, cs); fuse_notify()
1815 return fuse_notify_inval_entry(fc, size, cs); fuse_notify()
1818 return fuse_notify_store(fc, size, cs); fuse_notify()
1821 return fuse_notify_retrieve(fc, size, cs); fuse_notify()
1824 return fuse_notify_delete(fc, size, cs); fuse_notify()
1827 fuse_copy_finish(cs); fuse_notify()
1844 static int copy_out_args(struct fuse_copy_state *cs, struct fuse_out *out, copy_out_args() argument
1863 return fuse_copy_args(cs, out->numargs, out->argpages, out->args, copy_out_args()
1875 struct fuse_copy_state *cs, size_t nbytes) fuse_dev_do_write()
1884 err = fuse_copy_one(cs, &oh, sizeof(oh)); fuse_dev_do_write()
1897 err = fuse_notify(fc, oh.error, nbytes - sizeof(oh), cs); fuse_dev_do_write()
1916 fuse_copy_finish(cs); fuse_dev_do_write()
1933 fuse_copy_finish(cs); fuse_dev_do_write()
1941 cs->req = req; fuse_dev_do_write()
1943 cs->move_pages = 0; fuse_dev_do_write()
1946 err = copy_out_args(cs, &req->out, nbytes); fuse_dev_do_write()
1947 fuse_copy_finish(cs); fuse_dev_do_write()
1963 fuse_copy_finish(cs); fuse_dev_do_write()
1969 struct fuse_copy_state cs; fuse_dev_write() local
1977 fuse_copy_init(&cs, fc, 0, from); fuse_dev_write()
1979 return fuse_dev_do_write(fc, &cs, iov_iter_count(from)); fuse_dev_write()
1989 struct fuse_copy_state cs; fuse_dev_splice_write() local
2042 fuse_copy_init(&cs, fc, 0, NULL); fuse_dev_splice_write()
2043 cs.pipebufs = bufs; fuse_dev_splice_write()
2044 cs.nr_segs = nbuf; fuse_dev_splice_write()
2045 cs.pipe = pipe; fuse_dev_splice_write()
2048 cs.move_pages = 1; fuse_dev_splice_write()
2050 ret = fuse_dev_do_write(fc, &cs, len); fuse_dev_splice_write()
1261 fuse_dev_do_read(struct fuse_conn *fc, struct file *file, struct fuse_copy_state *cs, size_t nbytes) fuse_dev_do_read() argument
1452 fuse_notify_poll(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_poll() argument
1473 fuse_notify_inval_inode(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_inval_inode() argument
1501 fuse_notify_inval_entry(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_inval_entry() argument
1552 fuse_notify_delete(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_delete() argument
1604 fuse_notify_store(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_store() argument
1764 fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size, struct fuse_copy_state *cs) fuse_notify_retrieve() argument
1801 fuse_notify(struct fuse_conn *fc, enum fuse_notify_code code, unsigned int size, struct fuse_copy_state *cs) fuse_notify() argument
1874 fuse_dev_do_write(struct fuse_conn *fc, struct fuse_copy_state *cs, size_t nbytes) fuse_dev_do_write() argument
|
| /linux-4.1.27/net/core/ |
| H A D | netclassid_cgroup.c | 33 struct cgroup_cls_state *cs; cgrp_css_alloc() local
35 cs = kzalloc(sizeof(*cs), GFP_KERNEL); cgrp_css_alloc()
36 if (!cs) cgrp_css_alloc()
39 return &cs->css; cgrp_css_alloc()
44 struct cgroup_cls_state *cs = css_cls_state(css); cgrp_css_online() local
48 cs->classid = parent->classid; cgrp_css_online()
72 struct cgroup_cls_state *cs = css_cls_state(css); cgrp_attach() local
73 void *v = (void *)(unsigned long)cs->classid; cgrp_attach()
|
| /linux-4.1.27/arch/mips/netlogic/xlr/ |
| H A D | platform-flash.c | 91 int cs; member in struct:xlr_nand_flash_priv
102 FLASH_NAND_CLE(nand_priv.cs), cmd); xlr_nand_ctrl()
105 FLASH_NAND_ALE(nand_priv.cs), cmd); xlr_nand_ctrl()
147 uint64_t flash_map_base, int cs, struct resource *res) setup_flash_resource()
151 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); setup_flash_resource()
152 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); setup_flash_resource()
162 int cs, boot_nand, boot_nor; xlr_flash_init() local
191 cs = 0; xlr_flash_init()
194 nand_priv.cs = cs; xlr_flash_init()
196 setup_flash_resource(flash_mmio, flash_map_base, cs, xlr_flash_init()
200 nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs), xlr_flash_init()
202 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs), xlr_flash_init()
204 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs), xlr_flash_init()
207 pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res); xlr_flash_init()
212 setup_flash_resource(flash_mmio, flash_map_base, cs, xlr_flash_init()
214 pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res); xlr_flash_init()
146 setup_flash_resource(uint64_t flash_mmio, uint64_t flash_map_base, int cs, struct resource *res) setup_flash_resource() argument
|
| /linux-4.1.27/drivers/s390/char/ |
| H A D | raw3270.h | 223 struct string *cs, *tmp; alloc_string() local
227 list_for_each_entry(cs, free_list, list) { list_for_each_entry()
228 if (cs->size < size) list_for_each_entry()
230 if (cs->size > size + sizeof(struct string)) { list_for_each_entry()
231 char *endaddr = (char *) (cs + 1) + cs->size; list_for_each_entry()
234 cs->size -= size + sizeof(struct string); list_for_each_entry()
235 cs = tmp; list_for_each_entry()
237 list_del(&cs->list); list_for_each_entry()
238 cs->len = len; list_for_each_entry()
239 INIT_LIST_HEAD(&cs->list); list_for_each_entry()
240 INIT_LIST_HEAD(&cs->update); list_for_each_entry()
241 return cs; list_for_each_entry()
247 free_string(struct list_head *free_list, struct string *cs) free_string() argument
255 if (list_entry(p, struct string, list) > cs) list_for_each()
262 if ((char *) (cs + 1) + cs->size == (char *) tmp) {
264 cs->size += tmp->size + sizeof(struct string);
270 if ((char *) (tmp + 1) + tmp->size == (char *) cs) {
271 tmp->size += cs->size + sizeof(struct string);
275 __list_add(&cs->list, left, left->next);
276 return cs->size;
282 struct string *cs; add_string_memory() local
284 cs = (struct string *) mem; add_string_memory()
285 cs->size = size - sizeof(struct string); add_string_memory()
286 free_string(free_list, cs); add_string_memory()
|
| /linux-4.1.27/arch/mips/lasat/ |
| H A D | at93c.h | 13 u32 cs; member in struct:at93c_defs
|
| H A D | at93c.c | 96 at93c_reg_write((at93c_reg_read() | at93c->cs) & at93c_init_op()
103 at93c_reg_write(at93c_reg_read() & ~at93c->cs); at93c_end_op()
|
| H A D | prom.c | 70 .cs = AT93C_CS_M_100,
77 .cs = AT93C_CS_M_200,
|
| /linux-4.1.27/arch/x86/lib/ |
| H A D | strstr_32.c | 3 char *strstr(const char *cs, const char *ct) strstr() argument
27 : "0" (0), "1" (0xffffffff), "2" (cs), "g" (ct) strstr()
|
| H A D | string_32.c | 94 int strcmp(const char *cs, const char *ct) strcmp() argument
109 : "1" (cs), "2" (ct) strcmp()
117 int strncmp(const char *cs, const char *ct, size_t count) strncmp() argument
134 : "1" (cs), "2" (ct), "3" (count) strncmp()
179 void *memchr(const void *cs, int c, size_t count) memchr() argument
191 : "a" (c), "0" (cs), "1" (count) memchr()
|
| /linux-4.1.27/drivers/memory/ |
| H A D | omap-gpmc.c | 207 /* Structure to save gpmc cs context */
264 void gpmc_cs_write_reg(int cs, int idx, u32 val) gpmc_cs_write_reg() argument
268 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; gpmc_cs_write_reg()
272 static u32 gpmc_cs_read_reg(int cs, int idx) gpmc_cs_read_reg() argument
276 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; gpmc_cs_read_reg()
293 * @cs Chip Select Region.
296 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) gpmc_get_clk_period() argument
309 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); gpmc_get_clk_period()
324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, gpmc_ns_to_clk_ticks() argument
330 tick_ps = gpmc_get_clk_period(cs, cd); gpmc_ns_to_clk_ticks()
350 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs, gpmc_clk_ticks_to_ns() argument
353 return ticks * gpmc_get_clk_period(cs, cd) / 1000; gpmc_clk_ticks_to_ns()
373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) gpmc_cs_modify_reg() argument
377 l = gpmc_cs_read_reg(cs, reg); gpmc_cs_modify_reg()
382 gpmc_cs_write_reg(cs, reg, l); gpmc_cs_modify_reg()
385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) gpmc_cs_bool_timings() argument
387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, gpmc_cs_bool_timings()
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, gpmc_cs_bool_timings()
392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, gpmc_cs_bool_timings()
394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, gpmc_cs_bool_timings()
396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, gpmc_cs_bool_timings()
398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, gpmc_cs_bool_timings()
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, gpmc_cs_bool_timings()
409 * @cs: Chip Select Region
429 int cs, int reg, int st_bit, int end_bit, int max, get_gpmc_timing_reg()
441 l = gpmc_cs_read_reg(cs, reg); get_gpmc_timing_reg()
458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; get_gpmc_timing_reg()
459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); get_gpmc_timing_reg()
472 #define GPMC_PRINT_CONFIG(cs, config) \
473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
474 gpmc_cs_read_reg(cs, config))
476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
490 static void gpmc_show_regs(int cs, const char *desc) gpmc_show_regs() argument
492 pr_info("gpmc cs%i %s:\n", cs, desc); gpmc_show_regs()
493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); gpmc_show_regs()
494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); gpmc_show_regs()
495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); gpmc_show_regs()
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); gpmc_show_regs()
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); gpmc_show_regs()
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); gpmc_show_regs()
505 static void gpmc_cs_show_timings(int cs, const char *desc) gpmc_cs_show_timings() argument
507 gpmc_show_regs(cs, desc); gpmc_cs_show_timings()
509 pr_info("gpmc cs%i access configuration:\n", cs); gpmc_cs_show_timings()
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); gpmc_cs_show_timings()
536 pr_info("gpmc cs%i timings configuration:\n", cs); gpmc_cs_show_timings()
537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); gpmc_cs_show_timings()
538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); gpmc_cs_show_timings()
539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); gpmc_cs_show_timings()
570 static inline void gpmc_cs_show_timings(int cs, const char *desc) gpmc_cs_show_timings() argument
580 * @cs: Chip Select Region.
591 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, set_gpmc_timing_reg() argument
600 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); set_gpmc_timing_reg()
609 __func__, cs, name, time, ticks, max); set_gpmc_timing_reg()
614 l = gpmc_cs_read_reg(cs, reg); set_gpmc_timing_reg()
618 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, set_gpmc_timing_reg()
623 gpmc_cs_write_reg(cs, reg, l); set_gpmc_timing_reg()
629 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
688 * @cs: Chip Select Region.
693 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, gpmc_cs_set_timings() argument
699 gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings"); gpmc_cs_set_timings()
758 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); gpmc_cs_set_timings()
761 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); gpmc_cs_set_timings()
772 cs, (div * gpmc_get_fclk_period()) / 1000, div); gpmc_cs_set_timings()
775 gpmc_cs_bool_timings(cs, &t->bool_timings); gpmc_cs_set_timings()
776 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); gpmc_cs_set_timings()
781 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) gpmc_cs_set_memconf() argument
798 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); gpmc_cs_set_memconf()
803 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); gpmc_cs_set_memconf()
808 static void gpmc_cs_enable_mem(int cs) gpmc_cs_enable_mem() argument
812 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); gpmc_cs_enable_mem()
814 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); gpmc_cs_enable_mem()
817 static void gpmc_cs_disable_mem(int cs) gpmc_cs_disable_mem() argument
821 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); gpmc_cs_disable_mem()
823 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); gpmc_cs_disable_mem()
826 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) gpmc_cs_get_memconf() argument
831 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); gpmc_cs_get_memconf()
837 static int gpmc_cs_mem_enabled(int cs) gpmc_cs_mem_enabled() argument
841 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); gpmc_cs_mem_enabled()
845 static void gpmc_cs_set_reserved(int cs, int reserved) gpmc_cs_set_reserved() argument
847 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_set_reserved()
852 static bool gpmc_cs_reserved(int cs) gpmc_cs_reserved() argument
854 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_reserved()
859 static void gpmc_cs_set_name(int cs, const char *name) gpmc_cs_set_name() argument
861 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_set_name()
866 static const char *gpmc_cs_get_name(int cs) gpmc_cs_get_name() argument
868 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_get_name()
887 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) gpmc_cs_insert_mem() argument
889 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_insert_mem()
903 static int gpmc_cs_delete_mem(int cs) gpmc_cs_delete_mem() argument
905 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_delete_mem()
920 * @cs: chip-select to remap
927 static int gpmc_cs_remap(int cs, u32 base) gpmc_cs_remap() argument
932 if (cs > gpmc_cs_num) { gpmc_cs_remap()
944 gpmc_cs_get_memconf(cs, &old_base, &size); gpmc_cs_remap()
948 ret = gpmc_cs_delete_mem(cs); gpmc_cs_remap()
952 ret = gpmc_cs_insert_mem(cs, base, size); gpmc_cs_remap()
956 ret = gpmc_cs_set_memconf(cs, base, size); gpmc_cs_remap()
961 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) gpmc_cs_request() argument
963 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_request()
967 if (cs > gpmc_cs_num) { gpmc_cs_request()
976 if (gpmc_cs_reserved(cs)) { gpmc_cs_request()
980 if (gpmc_cs_mem_enabled(cs)) gpmc_cs_request()
989 gpmc_cs_disable_mem(cs); gpmc_cs_request()
991 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); gpmc_cs_request()
998 gpmc_cs_enable_mem(cs); gpmc_cs_request()
1000 gpmc_cs_set_reserved(cs, 1); gpmc_cs_request()
1007 void gpmc_cs_free(int cs) gpmc_cs_free() argument
1009 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; gpmc_cs_free()
1013 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { gpmc_cs_free()
1014 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); gpmc_cs_free()
1019 gpmc_cs_disable_mem(cs); gpmc_cs_free()
1022 gpmc_cs_set_reserved(cs, 0); gpmc_cs_free()
1064 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) gpmc_update_nand_reg() argument
1070 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; gpmc_update_nand_reg()
1072 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; gpmc_update_nand_reg()
1074 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; gpmc_update_nand_reg()
1213 int cs; gpmc_mem_exit() local
1215 for (cs = 0; cs < gpmc_cs_num; cs++) { gpmc_mem_exit()
1216 if (!gpmc_cs_mem_enabled(cs)) gpmc_mem_exit()
1218 gpmc_cs_delete_mem(cs); gpmc_mem_exit()
1225 int cs; gpmc_mem_init() local
1236 for (cs = 0; cs < gpmc_cs_num; cs++) { gpmc_mem_init()
1239 if (!gpmc_cs_mem_enabled(cs)) gpmc_mem_init()
1241 gpmc_cs_get_memconf(cs, &base, &size); gpmc_mem_init()
1242 if (gpmc_cs_insert_mem(cs, base, size)) { gpmc_mem_init()
1243 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", gpmc_mem_init()
1244 __func__, cs, base, base + size); gpmc_mem_init()
1245 gpmc_cs_disable_mem(cs); gpmc_mem_init()
1574 * @cs: GPMC chip-select to program
1584 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) gpmc_cs_program_settings() argument
1650 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); gpmc_cs_program_settings()
1719 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); gpmc_read_timings_dt()
1720 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); gpmc_read_timings_dt()
1721 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); gpmc_read_timings_dt()
1766 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); gpmc_read_timings_dt()
1799 gpmc_nand_data->cs = val; gpmc_probe_nand_child()
1888 gpmc_onenand_data->cs = val; gpmc_probe_onenand_child()
1923 int ret, cs; gpmc_probe_generic_child() local
1926 if (of_property_read_u32(child, "reg", &cs) < 0) { gpmc_probe_generic_child()
1943 name = gpmc_cs_get_name(cs); gpmc_probe_generic_child()
1947 ret = gpmc_cs_request(cs, resource_size(&res), &base); gpmc_probe_generic_child()
1949 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); gpmc_probe_generic_child()
1952 gpmc_cs_set_name(cs, child->name); gpmc_probe_generic_child()
1964 cs); gpmc_probe_generic_child()
1965 gpmc_cs_show_timings(cs, gpmc_probe_generic_child()
1971 gpmc_cs_disable_mem(cs); gpmc_probe_generic_child()
1981 ret = gpmc_cs_remap(cs, res.start); gpmc_probe_generic_child()
1984 cs, &res.start); gpmc_probe_generic_child()
1992 ret = gpmc_cs_program_settings(cs, &gpmc_s); gpmc_probe_generic_child()
1996 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); gpmc_probe_generic_child()
2009 gpmc_cs_enable_mem(cs); gpmc_probe_generic_child()
2032 gpmc_cs_free(cs); gpmc_probe_generic_child()
2047 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", gpmc_probe_dt()
427 get_gpmc_timing_reg( int cs, int reg, int st_bit, int end_bit, int max, const char *name, const enum gpmc_clk_domain cd, int shift, bool raw, bool noval) get_gpmc_timing_reg() argument
|
| H A D | ti-aemif.c | 86 * struct aemif_cs_data: structure to hold cs parameters
87 * @cs: chip-select number
100 u8 cs; member in struct:aemif_cs_data
119 * @cs_offset: start number of cs nodes
185 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; aemif_config_abus()
240 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; aemif_get_hw_params()
261 * configured in a cs device binding node.
268 u32 cs; of_aemif_parse_abus_config() local
271 if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) { of_aemif_parse_abus_config()
272 dev_dbg(&pdev->dev, "cs property is required"); of_aemif_parse_abus_config()
276 if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) { of_aemif_parse_abus_config()
277 dev_dbg(&pdev->dev, "cs number is incorrect %d", cs); of_aemif_parse_abus_config()
282 dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS); of_aemif_parse_abus_config()
287 data->cs = cs; of_aemif_parse_abus_config()
293 if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) of_aemif_parse_abus_config()
296 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) of_aemif_parse_abus_config()
299 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) of_aemif_parse_abus_config()
302 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) of_aemif_parse_abus_config()
305 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) of_aemif_parse_abus_config()
308 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) of_aemif_parse_abus_config()
311 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) of_aemif_parse_abus_config()
314 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) of_aemif_parse_abus_config()
317 data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode"); of_aemif_parse_abus_config()
318 data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode"); of_aemif_parse_abus_config()
367 * For every controller device node, there is a cs device node that aemif_probe()
369 * over these nodes and update the cs data array. aemif_probe()
381 aemif->cs_data[i].cs);
|
| /linux-4.1.27/kernel/ |
| H A D | cpuset.c | 146 static inline struct cpuset *parent_cs(struct cpuset *cs) parent_cs() argument
148 return css_cs(cs->css.parent); parent_cs()
177 static inline bool is_cpuset_online(const struct cpuset *cs) is_cpuset_online() argument
179 return test_bit(CS_ONLINE, &cs->flags); is_cpuset_online()
182 static inline int is_cpu_exclusive(const struct cpuset *cs) is_cpu_exclusive() argument
184 return test_bit(CS_CPU_EXCLUSIVE, &cs->flags); is_cpu_exclusive()
187 static inline int is_mem_exclusive(const struct cpuset *cs) is_mem_exclusive() argument
189 return test_bit(CS_MEM_EXCLUSIVE, &cs->flags); is_mem_exclusive()
192 static inline int is_mem_hardwall(const struct cpuset *cs) is_mem_hardwall() argument
194 return test_bit(CS_MEM_HARDWALL, &cs->flags); is_mem_hardwall()
197 static inline int is_sched_load_balance(const struct cpuset *cs) is_sched_load_balance() argument
199 return test_bit(CS_SCHED_LOAD_BALANCE, &cs->flags); is_sched_load_balance()
202 static inline int is_memory_migrate(const struct cpuset *cs) is_memory_migrate() argument
204 return test_bit(CS_MEMORY_MIGRATE, &cs->flags); is_memory_migrate()
207 static inline int is_spread_page(const struct cpuset *cs) is_spread_page() argument
209 return test_bit(CS_SPREAD_PAGE, &cs->flags); is_spread_page()
212 static inline int is_spread_slab(const struct cpuset *cs) is_spread_slab() argument
214 return test_bit(CS_SPREAD_SLAB, &cs->flags); is_spread_slab()
334 static void guarantee_online_cpus(struct cpuset *cs, struct cpumask *pmask) guarantee_online_cpus() argument
336 while (!cpumask_intersects(cs->effective_cpus, cpu_online_mask)) guarantee_online_cpus()
337 cs = parent_cs(cs); guarantee_online_cpus()
338 cpumask_and(pmask, cs->effective_cpus, cpu_online_mask); guarantee_online_cpus()
352 static void guarantee_online_mems(struct cpuset *cs, nodemask_t *pmask) guarantee_online_mems() argument
354 while (!nodes_intersects(cs->effective_mems, node_states[N_MEMORY])) guarantee_online_mems()
355 cs = parent_cs(cs); guarantee_online_mems()
356 nodes_and(*pmask, cs->effective_mems, node_states[N_MEMORY]); guarantee_online_mems()
364 static void cpuset_update_task_spread_flag(struct cpuset *cs, cpuset_update_task_spread_flag() argument
367 if (is_spread_page(cs)) cpuset_update_task_spread_flag()
372 if (is_spread_slab(cs)) cpuset_update_task_spread_flag()
396 * @cs: the cpuset that the trial cpuset duplicates
398 static struct cpuset *alloc_trial_cpuset(struct cpuset *cs) alloc_trial_cpuset() argument
402 trial = kmemdup(cs, sizeof(*cs), GFP_KERNEL); alloc_trial_cpuset()
411 cpumask_copy(trial->cpus_allowed, cs->cpus_allowed); alloc_trial_cpuset()
412 cpumask_copy(trial->effective_cpus, cs->effective_cpus); alloc_trial_cpuset()
837 * @cs: the cpuset in which each task's cpus_allowed mask needs to be changed
839 * Iterate through each task of @cs updating its cpus_allowed to the
843 static void update_tasks_cpumask(struct cpuset *cs) update_tasks_cpumask() argument
848 css_task_iter_start(&cs->css, &it); update_tasks_cpumask()
850 set_cpus_allowed_ptr(task, cs->effective_cpus); update_tasks_cpumask()
856 * @cs: the cpuset to consider
866 static void update_cpumasks_hier(struct cpuset *cs, struct cpumask *new_cpus) update_cpumasks_hier() argument
873 cpuset_for_each_descendant_pre(cp, pos_css, cs) { cpuset_for_each_descendant_pre()
923 * @cs: the cpuset to consider
927 static int update_cpumask(struct cpuset *cs, struct cpuset *trialcs, update_cpumask() argument
933 if (cs == &top_cpuset) update_cpumask()
955 if (cpumask_equal(cs->cpus_allowed, trialcs->cpus_allowed)) update_cpumask()
958 retval = validate_change(cs, trialcs); update_cpumask()
963 cpumask_copy(cs->cpus_allowed, trialcs->cpus_allowed); update_cpumask()
967 update_cpumasks_hier(cs, trialcs->cpus_allowed); update_cpumask()
1055 * @cs: the cpuset in which each task's mems_allowed mask needs to be changed
1057 * Iterate through each task of @cs updating its mems_allowed to the
1061 static void update_tasks_nodemask(struct cpuset *cs) update_tasks_nodemask() argument
1067 cpuset_being_rebound = cs; /* causes mpol_dup() rebind */ update_tasks_nodemask()
1069 guarantee_online_mems(cs, &newmems); update_tasks_nodemask()
1081 css_task_iter_start(&cs->css, &it); update_tasks_nodemask()
1092 migrate = is_memory_migrate(cs); update_tasks_nodemask()
1094 mpol_rebind_mm(mm, &cs->mems_allowed); update_tasks_nodemask()
1096 cpuset_migrate_mm(mm, &cs->old_mems_allowed, &newmems); update_tasks_nodemask()
1103 * cs->old_mems_allowed. update_tasks_nodemask()
1105 cs->old_mems_allowed = newmems; update_tasks_nodemask()
1113 * @cs: the cpuset to consider
1123 static void update_nodemasks_hier(struct cpuset *cs, nodemask_t *new_mems) update_nodemasks_hier() argument
1129 cpuset_for_each_descendant_pre(cp, pos_css, cs) { cpuset_for_each_descendant_pre()
1175 * Will take tasklist_lock, scan tasklist for tasks in cpuset cs,
1179 static int update_nodemask(struct cpuset *cs, struct cpuset *trialcs, update_nodemask() argument
1188 if (cs == &top_cpuset) { update_nodemask()
1213 if (nodes_equal(cs->mems_allowed, trialcs->mems_allowed)) { update_nodemask()
1217 retval = validate_change(cs, trialcs); update_nodemask()
1222 cs->mems_allowed = trialcs->mems_allowed; update_nodemask()
1226 update_nodemasks_hier(cs, &trialcs->mems_allowed); update_nodemask()
1242 static int update_relax_domain_level(struct cpuset *cs, s64 val) update_relax_domain_level() argument
1249 if (val != cs->relax_domain_level) { update_relax_domain_level()
1250 cs->relax_domain_level = val; update_relax_domain_level()
1251 if (!cpumask_empty(cs->cpus_allowed) && update_relax_domain_level()
1252 is_sched_load_balance(cs)) update_relax_domain_level()
1261 * @cs: the cpuset in which each task's spread flags needs to be changed
1263 * Iterate through each task of @cs updating its spread flags. As this
1267 static void update_tasks_flags(struct cpuset *cs) update_tasks_flags() argument
1272 css_task_iter_start(&cs->css, &it); update_tasks_flags()
1274 cpuset_update_task_spread_flag(cs, task); update_tasks_flags()
1281 * cs: the cpuset to update
1287 static int update_flag(cpuset_flagbits_t bit, struct cpuset *cs, update_flag() argument
1295 trialcs = alloc_trial_cpuset(cs); update_flag()
1304 err = validate_change(cs, trialcs); update_flag()
1308 balance_flag_changed = (is_sched_load_balance(cs) != update_flag()
1311 spread_flag_changed = ((is_spread_slab(cs) != is_spread_slab(trialcs)) update_flag()
1312 || (is_spread_page(cs) != is_spread_page(trialcs))); update_flag()
1315 cs->flags = trialcs->flags; update_flag()
1322 update_tasks_flags(cs); update_flag()
1432 struct cpuset *cs = css_cs(css); cpuset_can_attach() local
1444 (cpumask_empty(cs->cpus_allowed) || nodes_empty(cs->mems_allowed))) cpuset_can_attach()
1448 ret = task_can_attach(task, cs->cpus_allowed); cgroup_taskset_for_each()
1460 cs->attach_in_progress++;
1490 struct cpuset *cs = css_cs(css); cpuset_attach() local
1496 if (cs == &top_cpuset) cpuset_attach()
1499 guarantee_online_cpus(cs, cpus_attach); cpuset_attach()
1501 guarantee_online_mems(cs, &cpuset_attach_nodemask_to); cpuset_attach()
1511 cpuset_update_task_spread_flag(cs, task); cgroup_taskset_for_each()
1518 cpuset_attach_nodemask_to = cs->effective_mems;
1530 if (is_memory_migrate(cs)) {
1537 cs->old_mems_allowed = cpuset_attach_nodemask_to;
1539 cs->attach_in_progress--;
1540 if (!cs->attach_in_progress)
1568 struct cpuset *cs = css_cs(css); cpuset_write_u64() local
1573 if (!is_cpuset_online(cs)) { cpuset_write_u64()
1580 retval = update_flag(CS_CPU_EXCLUSIVE, cs, val); cpuset_write_u64()
1583 retval = update_flag(CS_MEM_EXCLUSIVE, cs, val); cpuset_write_u64()
1586 retval = update_flag(CS_MEM_HARDWALL, cs, val); cpuset_write_u64()
1589 retval = update_flag(CS_SCHED_LOAD_BALANCE, cs, val); cpuset_write_u64()
1592 retval = update_flag(CS_MEMORY_MIGRATE, cs, val); cpuset_write_u64()
1601 retval = update_flag(CS_SPREAD_PAGE, cs, val); cpuset_write_u64()
1604 retval = update_flag(CS_SPREAD_SLAB, cs, val); cpuset_write_u64()
1618 struct cpuset *cs = css_cs(css); cpuset_write_s64() local
1623 if (!is_cpuset_online(cs)) cpuset_write_s64()
1628 retval = update_relax_domain_level(cs, val); cpuset_write_s64()
1645 struct cpuset *cs = css_cs(of_css(of)); cpuset_write_resmask() local
1652 * CPU or memory hotunplug may leave @cs w/o any execution cpuset_write_resmask()
1657 * As writes to "cpus" or "mems" may restore @cs's execution cpuset_write_resmask()
1666 * protection is okay as we check whether @cs is online after cpuset_write_resmask()
1670 css_get(&cs->css); cpuset_write_resmask()
1675 if (!is_cpuset_online(cs)) cpuset_write_resmask()
1678 trialcs = alloc_trial_cpuset(cs); cpuset_write_resmask()
1686 retval = update_cpumask(cs, trialcs, buf); cpuset_write_resmask()
1689 retval = update_nodemask(cs, trialcs, buf); cpuset_write_resmask()
1700 css_put(&cs->css); cpuset_write_resmask()
1714 struct cpuset *cs = css_cs(seq_css(sf)); cpuset_common_seq_show() local
1722 seq_printf(sf, "%*pbl\n", cpumask_pr_args(cs->cpus_allowed)); cpuset_common_seq_show()
1725 seq_printf(sf, "%*pbl\n", nodemask_pr_args(&cs->mems_allowed)); cpuset_common_seq_show()
1728 seq_printf(sf, "%*pbl\n", cpumask_pr_args(cs->effective_cpus)); cpuset_common_seq_show()
1731 seq_printf(sf, "%*pbl\n", nodemask_pr_args(&cs->effective_mems)); cpuset_common_seq_show()
1743 struct cpuset *cs = css_cs(css); cpuset_read_u64() local
1747 return is_cpu_exclusive(cs); cpuset_read_u64()
1749 return is_mem_exclusive(cs); cpuset_read_u64()
1751 return is_mem_hardwall(cs); cpuset_read_u64()
1753 return is_sched_load_balance(cs); cpuset_read_u64()
1755 return is_memory_migrate(cs); cpuset_read_u64()
1759 return fmeter_getrate(&cs->fmeter); cpuset_read_u64()
1761 return is_spread_page(cs); cpuset_read_u64()
1763 return is_spread_slab(cs); cpuset_read_u64()
1774 struct cpuset *cs = css_cs(css); cpuset_read_s64() local
1778 return cs->relax_domain_level; cpuset_read_s64()
1904 struct cpuset *cs; cpuset_css_alloc() local
1909 cs = kzalloc(sizeof(*cs), GFP_KERNEL); cpuset_css_alloc()
1910 if (!cs) cpuset_css_alloc()
1912 if (!alloc_cpumask_var(&cs->cpus_allowed, GFP_KERNEL)) cpuset_css_alloc()
1914 if (!alloc_cpumask_var(&cs->effective_cpus, GFP_KERNEL)) cpuset_css_alloc()
1917 set_bit(CS_SCHED_LOAD_BALANCE, &cs->flags); cpuset_css_alloc()
1918 cpumask_clear(cs->cpus_allowed); cpuset_css_alloc()
1919 nodes_clear(cs->mems_allowed); cpuset_css_alloc()
1920 cpumask_clear(cs->effective_cpus); cpuset_css_alloc()
1921 nodes_clear(cs->effective_mems); cpuset_css_alloc()
1922 fmeter_init(&cs->fmeter); cpuset_css_alloc()
1923 cs->relax_domain_level = -1; cpuset_css_alloc()
1925 return &cs->css; cpuset_css_alloc()
1928 free_cpumask_var(cs->cpus_allowed); cpuset_css_alloc()
1930 kfree(cs); cpuset_css_alloc()
1936 struct cpuset *cs = css_cs(css); cpuset_css_online() local
1937 struct cpuset *parent = parent_cs(cs); cpuset_css_online()
1946 set_bit(CS_ONLINE, &cs->flags); cpuset_css_online()
1948 set_bit(CS_SPREAD_PAGE, &cs->flags); cpuset_css_online()
1950 set_bit(CS_SPREAD_SLAB, &cs->flags); cpuset_css_online()
1955 if (cgroup_on_dfl(cs->css.cgroup)) { cpuset_css_online()
1956 cpumask_copy(cs->effective_cpus, parent->effective_cpus); cpuset_css_online()
1957 cs->effective_mems = parent->effective_mems; cpuset_css_online()
1987 cs->mems_allowed = parent->mems_allowed;
1988 cs->effective_mems = parent->mems_allowed;
1989 cpumask_copy(cs->cpus_allowed, parent->cpus_allowed);
1990 cpumask_copy(cs->effective_cpus, parent->cpus_allowed);
2005 struct cpuset *cs = css_cs(css); cpuset_css_offline() local
2009 if (is_sched_load_balance(cs)) cpuset_css_offline()
2010 update_flag(CS_SCHED_LOAD_BALANCE, cs, 0); cpuset_css_offline()
2013 clear_bit(CS_ONLINE, &cs->flags); cpuset_css_offline()
2020 struct cpuset *cs = css_cs(css); cpuset_css_free() local
2022 free_cpumask_var(cs->effective_cpus); cpuset_css_free()
2023 free_cpumask_var(cs->cpus_allowed); cpuset_css_free()
2024 kfree(cs); cpuset_css_free()
2099 static void remove_tasks_in_empty_cpuset(struct cpuset *cs) remove_tasks_in_empty_cpuset() argument
2107 parent = parent_cs(cs); remove_tasks_in_empty_cpuset()
2112 if (cgroup_transfer_tasks(parent->css.cgroup, cs->css.cgroup)) { remove_tasks_in_empty_cpuset()
2114 pr_cont_cgroup_name(cs->css.cgroup); remove_tasks_in_empty_cpuset()
2120 hotplug_update_tasks_legacy(struct cpuset *cs, hotplug_update_tasks_legacy() argument
2127 cpumask_copy(cs->cpus_allowed, new_cpus); hotplug_update_tasks_legacy()
2128 cpumask_copy(cs->effective_cpus, new_cpus); hotplug_update_tasks_legacy()
2129 cs->mems_allowed = *new_mems; hotplug_update_tasks_legacy()
2130 cs->effective_mems = *new_mems; hotplug_update_tasks_legacy()
2137 if (cpus_updated && !cpumask_empty(cs->cpus_allowed)) hotplug_update_tasks_legacy()
2138 update_tasks_cpumask(cs); hotplug_update_tasks_legacy()
2139 if (mems_updated && !nodes_empty(cs->mems_allowed)) hotplug_update_tasks_legacy()
2140 update_tasks_nodemask(cs); hotplug_update_tasks_legacy()
2142 is_empty = cpumask_empty(cs->cpus_allowed) || hotplug_update_tasks_legacy()
2143 nodes_empty(cs->mems_allowed); hotplug_update_tasks_legacy()
2153 remove_tasks_in_empty_cpuset(cs); hotplug_update_tasks_legacy()
2159 hotplug_update_tasks(struct cpuset *cs, hotplug_update_tasks() argument
2164 cpumask_copy(new_cpus, parent_cs(cs)->effective_cpus); hotplug_update_tasks()
2166 *new_mems = parent_cs(cs)->effective_mems; hotplug_update_tasks()
2169 cpumask_copy(cs->effective_cpus, new_cpus); hotplug_update_tasks()
2170 cs->effective_mems = *new_mems; hotplug_update_tasks()
2174 update_tasks_cpumask(cs); hotplug_update_tasks()
2176 update_tasks_nodemask(cs); hotplug_update_tasks()
2181 * @cs: cpuset in interest
2183 * Compare @cs's cpu and mem masks against top_cpuset and if some have gone
2184 * offline, update @cs accordingly. If @cs ends up with no CPU or memory,
2187 static void cpuset_hotplug_update_tasks(struct cpuset *cs) cpuset_hotplug_update_tasks() argument
2194 wait_event(cpuset_attach_wq, cs->attach_in_progress == 0); cpuset_hotplug_update_tasks()
2202 if (cs->attach_in_progress) { cpuset_hotplug_update_tasks()
2207 cpumask_and(&new_cpus, cs->cpus_allowed, parent_cs(cs)->effective_cpus); cpuset_hotplug_update_tasks()
2208 nodes_and(new_mems, cs->mems_allowed, parent_cs(cs)->effective_mems); cpuset_hotplug_update_tasks()
2210 cpus_updated = !cpumask_equal(&new_cpus, cs->effective_cpus); cpuset_hotplug_update_tasks()
2211 mems_updated = !nodes_equal(new_mems, cs->effective_mems); cpuset_hotplug_update_tasks()
2213 if (cgroup_on_dfl(cs->css.cgroup)) cpuset_hotplug_update_tasks()
2214 hotplug_update_tasks(cs, &new_cpus, &new_mems, cpuset_hotplug_update_tasks()
2217 hotplug_update_tasks_legacy(cs, &new_cpus, &new_mems, cpuset_hotplug_update_tasks()
2279 struct cpuset *cs; cpuset_hotplug_workfn() local
2283 cpuset_for_each_descendant_pre(cs, pos_css, &top_cpuset) { cpuset_hotplug_workfn()
2284 if (cs == &top_cpuset || !css_tryget_online(&cs->css)) cpuset_hotplug_workfn()
2288 cpuset_hotplug_update_tasks(cs); cpuset_hotplug_workfn()
2291 css_put(&cs->css); cpuset_hotplug_workfn()
2382 * But we used cs && cs->cpus_allowed lockless and thus can cpuset_cpus_allowed_fallback()
2444 static struct cpuset *nearest_hardwall_ancestor(struct cpuset *cs) nearest_hardwall_ancestor() argument
2446 while (!(is_mem_exclusive(cs) || is_mem_hardwall(cs)) && parent_cs(cs)) nearest_hardwall_ancestor()
2447 cs = parent_cs(cs); nearest_hardwall_ancestor()
2448 return cs; nearest_hardwall_ancestor()
2493 struct cpuset *cs; /* current cpuset ancestors */ __cpuset_node_allowed() local
2517 cs = nearest_hardwall_ancestor(task_cs(current)); __cpuset_node_allowed()
2518 allowed = node_isset(node, cs->mems_allowed); __cpuset_node_allowed()
|
| /linux-4.1.27/drivers/net/slip/ |
| H A D | slhc.c | 232 register struct cstate *cs = lcs->next; slhc_compress() local
291 if( ip->saddr == cs->cs_ip.saddr slhc_compress()
292 && ip->daddr == cs->cs_ip.daddr slhc_compress()
293 && th->source == cs->cs_tcp.source slhc_compress()
294 && th->dest == cs->cs_tcp.dest) slhc_compress()
298 if ( cs == ocs ) slhc_compress()
300 lcs = cs; slhc_compress()
301 cs = cs->next; slhc_compress()
323 } else if (cs == ocs) { slhc_compress()
328 lcs->next = cs->next; slhc_compress()
329 cs->next = ocs->next; slhc_compress()
330 ocs->next = cs; slhc_compress()
345 oth = &cs->cs_tcp; slhc_compress()
347 if(ip->version != cs->cs_ip.version || ip->ihl != cs->cs_ip.ihl slhc_compress()
348 || ip->tos != cs->cs_ip.tos slhc_compress()
349 || (ip->frag_off & htons(0x4000)) != (cs->cs_ip.frag_off & htons(0x4000)) slhc_compress()
350 || ip->ttl != cs->cs_ip.ttl slhc_compress()
351 || th->doff != cs->cs_tcp.doff slhc_compress()
352 || (ip->ihl > 5 && memcmp(ip+1,cs->cs_ipopt,((ip->ihl)-5)*4) != 0) slhc_compress()
353 || (th->doff > 5 && memcmp(th+1,cs->cs_tcpopt,((th->doff)-5)*4) != 0)){ slhc_compress()
399 if(ip->tot_len != cs->cs_ip.tot_len && slhc_compress()
400 ntohs(cs->cs_ip.tot_len) == hlen) slhc_compress()
411 deltaS == ntohs(cs->cs_ip.tot_len) - hlen){ slhc_compress()
418 if(deltaS == ntohs(cs->cs_ip.tot_len) - hlen){ slhc_compress()
425 deltaS = ntohs(ip->id) - ntohs(cs->cs_ip.id); slhc_compress()
436 memcpy(&cs->cs_ip,ip,20); slhc_compress()
437 memcpy(&cs->cs_tcp,th,20); slhc_compress()
445 if(compress_cid == 0 || comp->xmit_current != cs->cs_this){ slhc_compress()
449 *cp++ = cs->cs_this; slhc_compress()
450 comp->xmit_current = cs->cs_this; slhc_compress()
465 /* Update connection state cs & send uncompressed packet (i.e., slhc_compress()
470 memcpy(&cs->cs_ip,ip,20); slhc_compress()
471 memcpy(&cs->cs_tcp,th,20); slhc_compress()
473 memcpy(cs->cs_ipopt, ip+1, ((ip->ihl) - 5) * 4); slhc_compress()
475 memcpy(cs->cs_tcpopt, th+1, ((th->doff) - 5) * 4); slhc_compress()
476 comp->xmit_current = cs->cs_this; slhc_compress()
480 ocp[9] = cs->cs_this; slhc_compress()
493 register struct cstate *cs; slhc_uncompress() local
523 cs = &comp->rstate[comp->recv_current]; slhc_uncompress()
524 thp = &cs->cs_tcp; slhc_uncompress()
525 ip = &cs->cs_ip; slhc_uncompress()
611 memcpy(cp, cs->cs_ipopt, (ip->ihl - 5) * 4); slhc_uncompress()
622 memcpy(cp, cs->cs_tcpopt, ((thp->doff) - 5) * 4); slhc_uncompress()
636 register struct cstate *cs; slhc_remember() local
667 cs = &comp->rstate[comp->recv_current = index]; slhc_remember()
669 memcpy(&cs->cs_ip,icp,20); slhc_remember()
670 memcpy(&cs->cs_tcp,icp + ihl*4,20); slhc_remember()
672 memcpy(cs->cs_ipopt, icp + sizeof(struct iphdr), (ihl - 5) * 4); slhc_remember()
673 if (cs->cs_tcp.doff > 5) slhc_remember()
674 memcpy(cs->cs_tcpopt, icp + ihl*4 + sizeof(struct tcphdr), (cs->cs_tcp.doff - 5) * 4); slhc_remember()
675 cs->cs_hsize = ihl*2 + cs->cs_tcp.doff*2; slhc_remember()
|
| /linux-4.1.27/drivers/spi/ |
| H A D | spi-fsl-spi.c | 89 struct spi_mpc8xxx_cs *cs = spi->controller_state; fsl_spi_change_mode() local
94 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) fsl_spi_change_mode()
101 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); fsl_spi_change_mode()
107 mpc8xxx_spi_write_reg(mode, cs->hw_mode); fsl_spi_change_mode()
116 struct spi_mpc8xxx_cs *cs = spi->controller_state; fsl_spi_chipselect() local
126 mpc8xxx_spi->rx_shift = cs->rx_shift; fsl_spi_chipselect()
127 mpc8xxx_spi->tx_shift = cs->tx_shift; fsl_spi_chipselect()
128 mpc8xxx_spi->get_rx = cs->get_rx; fsl_spi_chipselect()
129 mpc8xxx_spi->get_tx = cs->get_tx; fsl_spi_chipselect()
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, mspi_apply_cpu_mode_quirks() argument
177 cs->rx_shift = 0; mspi_apply_cpu_mode_quirks()
178 cs->tx_shift = 0; mspi_apply_cpu_mode_quirks()
180 cs->get_rx = mpc8xxx_spi_rx_buf_u8; mspi_apply_cpu_mode_quirks()
181 cs->get_tx = mpc8xxx_spi_tx_buf_u8; mspi_apply_cpu_mode_quirks()
183 cs->get_rx = mpc8xxx_spi_rx_buf_u16; mspi_apply_cpu_mode_quirks()
184 cs->get_tx = mpc8xxx_spi_tx_buf_u16; mspi_apply_cpu_mode_quirks()
186 cs->get_rx = mpc8xxx_spi_rx_buf_u32; mspi_apply_cpu_mode_quirks()
187 cs->get_tx = mpc8xxx_spi_tx_buf_u32; mspi_apply_cpu_mode_quirks()
192 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, mspi_apply_cpu_mode_quirks()
196 mpc8xxx_spi->rx_shift = cs->rx_shift; mspi_apply_cpu_mode_quirks()
197 mpc8xxx_spi->tx_shift = cs->tx_shift; mspi_apply_cpu_mode_quirks()
198 mpc8xxx_spi->get_rx = cs->get_rx; mspi_apply_cpu_mode_quirks()
199 mpc8xxx_spi->get_tx = cs->get_tx; mspi_apply_cpu_mode_quirks()
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, mspi_apply_qe_mode_quirks() argument
229 struct spi_mpc8xxx_cs *cs = spi->controller_state; fsl_spi_setup_transfer() local
246 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, fsl_spi_setup_transfer()
250 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, fsl_spi_setup_transfer()
262 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 fsl_spi_setup_transfer()
265 cs->hw_mode |= SPMODE_LEN(bits_per_word); fsl_spi_setup_transfer()
268 cs->hw_mode |= SPMODE_DIV16; fsl_spi_setup_transfer()
282 cs->hw_mode |= SPMODE_PM(pm); fsl_spi_setup_transfer()
428 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); fsl_spi_setup() local
433 if (!cs) { fsl_spi_setup()
434 cs = kzalloc(sizeof(*cs), GFP_KERNEL); fsl_spi_setup()
435 if (!cs) fsl_spi_setup()
437 spi_set_ctldata(spi, cs); fsl_spi_setup()
443 hw_mode = cs->hw_mode; /* Save original settings */ fsl_spi_setup()
444 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); fsl_spi_setup()
446 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH fsl_spi_setup()
450 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; fsl_spi_setup()
452 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; fsl_spi_setup()
454 cs->hw_mode |= SPMODE_REV; fsl_spi_setup()
456 cs->hw_mode |= SPMODE_LOOP; fsl_spi_setup()
460 cs->hw_mode = hw_mode; /* Restore settings */ fsl_spi_setup()
499 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); fsl_spi_cleanup() local
504 kfree(cs); fsl_spi_cleanup()
573 u16 cs = spi->chip_select; fsl_spi_grlib_cs_control() local
577 } else if (cs < mpc8xxx_spi->native_chipselects) { fsl_spi_grlib_cs_control()
579 slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs)); fsl_spi_grlib_cs_control()
715 u16 cs = spi->chip_select; fsl_spi_cs_control() local
716 int gpio = pinfo->gpios[cs]; fsl_spi_cs_control()
717 bool alow = pinfo->alow_flags[cs]; fsl_spi_cs_control()
|
| H A D | spi-bcm2835.c | 126 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); bcm2835_spi_reset_hw() local
129 cs &= ~(BCM2835_SPI_CS_INTR | bcm2835_spi_reset_hw()
133 cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; bcm2835_spi_reset_hw()
136 bcm2835_wr(bs, BCM2835_SPI_CS, cs); bcm2835_spi_reset_hw()
163 u32 cs, bcm2835_spi_transfer_one_poll()
171 bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); bcm2835_spi_transfer_one_poll()
199 u32 cs) bcm2835_spi_transfer_one_irq()
203 /* fill in fifo if we have gpio-cs bcm2835_spi_transfer_one_irq()
206 * with gpio-cs this does not happen, so it is implemented bcm2835_spi_transfer_one_irq()
214 cs | BCM2835_SPI_CS_TA); bcm2835_spi_transfer_one_irq()
225 cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA; bcm2835_spi_transfer_one_irq()
226 bcm2835_wr(bs, BCM2835_SPI_CS, cs); bcm2835_spi_transfer_one_irq()
239 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); bcm2835_spi_transfer_one() local
262 cs |= BCM2835_SPI_CS_REN; bcm2835_spi_transfer_one()
264 cs &= ~BCM2835_SPI_CS_REN; bcm2835_spi_transfer_one()
271 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; bcm2835_spi_transfer_one()
287 cs, xfer_time_us); bcm2835_spi_transfer_one()
289 return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); bcm2835_spi_transfer_one()
297 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); bcm2835_spi_prepare_message() local
299 cs &= ~(BCM2835_SPI_CS_CPOL | BCM2835_SPI_CS_CPHA); bcm2835_spi_prepare_message()
302 cs |= BCM2835_SPI_CS_CPOL; bcm2835_spi_prepare_message()
304 cs |= BCM2835_SPI_CS_CPHA; bcm2835_spi_prepare_message()
306 bcm2835_wr(bs, BCM2835_SPI_CS, cs); bcm2835_spi_prepare_message()
331 u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); bcm2835_spi_set_cs() local
340 cs |= BCM2835_SPI_CS_CSPOL; bcm2835_spi_set_cs()
341 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select; bcm2835_spi_set_cs()
344 cs &= ~BCM2835_SPI_CS_CSPOL; bcm2835_spi_set_cs()
345 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select); bcm2835_spi_set_cs()
350 /* set cs correctly */ bcm2835_spi_set_cs()
353 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; bcm2835_spi_set_cs()
356 cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01); bcm2835_spi_set_cs()
357 cs |= spi->chip_select; bcm2835_spi_set_cs()
361 cs &= ~BCM2835_SPI_CS_CSPOL; bcm2835_spi_set_cs()
363 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01; bcm2835_spi_set_cs()
367 bcm2835_wr(bs, BCM2835_SPI_CS, cs); bcm2835_spi_set_cs()
395 /* now translate native cs to GPIO */ bcm2835_spi_setup()
160 bcm2835_spi_transfer_one_poll(struct spi_master *master, struct spi_device *spi, struct spi_transfer *tfr, u32 cs, unsigned long xfer_time_us) bcm2835_spi_transfer_one_poll() argument
196 bcm2835_spi_transfer_one_irq(struct spi_master *master, struct spi_device *spi, struct spi_transfer *tfr, u32 cs) bcm2835_spi_transfer_one_irq() argument
|
| H A D | spi-omap2-mcspi.c | 127 struct list_head cs; member in struct:omap2_mcspi_regs
171 struct omap2_mcspi_cs *cs = spi->controller_state; mcspi_write_cs_reg() local
173 writel_relaxed(val, cs->base + idx); mcspi_write_cs_reg()
178 struct omap2_mcspi_cs *cs = spi->controller_state; mcspi_read_cs_reg() local
180 return readl_relaxed(cs->base + idx); mcspi_read_cs_reg()
185 struct omap2_mcspi_cs *cs = spi->controller_state; mcspi_cached_chconf0() local
187 return cs->chconf0; mcspi_cached_chconf0()
192 struct omap2_mcspi_cs *cs = spi->controller_state; mcspi_write_chconf0() local
194 cs->chconf0 = val; mcspi_write_chconf0()
231 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_set_enable() local
234 l = cs->chctrl0; omap2_mcspi_set_enable()
239 cs->chctrl0 = l; omap2_mcspi_set_enable()
240 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); omap2_mcspi_set_enable()
280 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_set_fifo() local
290 bytes_per_word = mcspi_bytes_per_word(cs->word_len); omap2_mcspi_set_fifo()
339 struct omap2_mcspi_cs *cs; omap2_mcspi_restore_ctx() local
345 list_for_each_entry(cs, &ctx->cs, node) omap2_mcspi_restore_ctx()
346 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); omap2_mcspi_restore_ctx()
438 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_rx_dma() local
447 word_len = cs->word_len; omap2_mcspi_rx_dma()
541 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_txrx_dma() local
560 if (cs->word_len <= 8) { omap2_mcspi_txrx_dma()
563 } else if (cs->word_len <= 16) { omap2_mcspi_txrx_dma()
582 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; omap2_mcspi_txrx_dma()
583 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; omap2_mcspi_txrx_dma()
616 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; omap2_mcspi_txrx_dma()
641 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_txrx_pio() local
644 void __iomem *base = cs->base; omap2_mcspi_txrx_pio()
653 word_len = cs->word_len; omap2_mcspi_txrx_pio()
845 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_setup_transfer() local
858 cs->word_len = word_len; omap2_mcspi_setup_transfer()
909 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; omap2_mcspi_setup_transfer()
910 cs->chctrl0 |= extclk << 8; omap2_mcspi_setup_transfer()
911 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); omap2_mcspi_setup_transfer()
926 cs->mode = spi->mode; omap2_mcspi_setup_transfer()
990 struct omap2_mcspi_cs *cs = spi->controller_state; omap2_mcspi_setup() local
994 if (!cs) { omap2_mcspi_setup()
995 cs = kzalloc(sizeof *cs, GFP_KERNEL); omap2_mcspi_setup()
996 if (!cs) omap2_mcspi_setup()
998 cs->base = mcspi->base + spi->chip_select * 0x14; omap2_mcspi_setup()
999 cs->phys = mcspi->phys + spi->chip_select * 0x14; omap2_mcspi_setup()
1000 cs->mode = 0; omap2_mcspi_setup()
1001 cs->chconf0 = 0; omap2_mcspi_setup()
1002 cs->chctrl0 = 0; omap2_mcspi_setup()
1003 spi->controller_state = cs; omap2_mcspi_setup()
1005 list_add_tail(&cs->node, &ctx->cs); omap2_mcspi_setup()
1029 struct omap2_mcspi_cs *cs; omap2_mcspi_cleanup() local
1035 cs = spi->controller_state; omap2_mcspi_cleanup()
1036 list_del(&cs->node); omap2_mcspi_cleanup()
1038 kfree(cs); omap2_mcspi_cleanup()
1070 struct omap2_mcspi_cs *cs; omap2_mcspi_work() local
1079 cs = spi->controller_state; omap2_mcspi_work()
1084 * it will be different from cs->mode (the current hardware setup). omap2_mcspi_work()
1089 if (spi->mode != cs->mode) omap2_mcspi_work()
1134 if (t->len > ((cs->word_len + 7) >> 3)) omap2_mcspi_work()
1151 writel_relaxed(0, cs->base omap2_mcspi_work()
1366 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); omap2_mcspi_probe()
1398 INIT_LIST_HEAD(&mcspi->ctx.cs); omap2_mcspi_probe()
1496 struct omap2_mcspi_cs *cs; omap2_mcspi_resume() local
1499 list_for_each_entry(cs, &ctx->cs, node) { omap2_mcspi_resume()
1500 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { omap2_mcspi_resume()
1505 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; omap2_mcspi_resume()
1506 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); omap2_mcspi_resume()
1507 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; omap2_mcspi_resume()
1508 writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); omap2_mcspi_resume()
|
| H A D | spi-fsl-espi.c | 37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
91 struct spi_mpc8xxx_cs *cs = spi->controller_state; fsl_espi_change_mode() local
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode); fsl_espi_change_mode()
138 struct spi_mpc8xxx_cs *cs = spi->controller_state; fsl_espi_setup_transfer() local
152 cs->rx_shift = 0; fsl_espi_setup_transfer()
153 cs->tx_shift = 0; fsl_espi_setup_transfer()
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32; fsl_espi_setup_transfer()
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32; fsl_espi_setup_transfer()
157 cs->rx_shift = 8 - bits_per_word; fsl_espi_setup_transfer()
159 cs->rx_shift = 16 - bits_per_word; fsl_espi_setup_transfer()
161 cs->get_tx = fsl_espi_tx_buf_lsb; fsl_espi_setup_transfer()
164 mpc8xxx_spi->rx_shift = cs->rx_shift; fsl_espi_setup_transfer()
165 mpc8xxx_spi->tx_shift = cs->tx_shift; fsl_espi_setup_transfer()
166 mpc8xxx_spi->get_rx = cs->get_rx; fsl_espi_setup_transfer()
167 mpc8xxx_spi->get_tx = cs->get_tx; fsl_espi_setup_transfer()
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); fsl_espi_setup_transfer()
174 cs->hw_mode |= CSMODE_LEN(bits_per_word); fsl_espi_setup_transfer()
177 cs->hw_mode |= CSMODE_DIV16; fsl_espi_setup_transfer()
193 cs->hw_mode |= CSMODE_PM(pm); fsl_espi_setup_transfer()
473 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); fsl_espi_setup() local
478 if (!cs) { fsl_espi_setup()
479 cs = kzalloc(sizeof(*cs), GFP_KERNEL); fsl_espi_setup()
480 if (!cs) fsl_espi_setup()
482 spi_set_ctldata(spi, cs); fsl_espi_setup()
488 hw_mode = cs->hw_mode; /* Save original settings */ fsl_espi_setup()
489 cs->hw_mode = mpc8xxx_spi_read_reg( fsl_espi_setup()
492 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH fsl_espi_setup()
496 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; fsl_espi_setup()
498 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; fsl_espi_setup()
500 cs->hw_mode |= CSMODE_REV; fsl_espi_setup()
511 cs->hw_mode = hw_mode; /* Restore settings */ fsl_espi_setup()
519 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); fsl_espi_cleanup() local
521 kfree(cs); fsl_espi_cleanup()
722 dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode); fsl_espi_probe()
|
| H A D | spi-bitbang.c | 139 struct spi_bitbang_cs *cs = spi->controller_state; spi_bitbang_setup_transfer() local
155 cs->txrx_bufs = bitbang_txrx_8; spi_bitbang_setup_transfer()
157 cs->txrx_bufs = bitbang_txrx_16; spi_bitbang_setup_transfer()
159 cs->txrx_bufs = bitbang_txrx_32; spi_bitbang_setup_transfer()
167 cs->nsecs = (1000000000/2) / hz; spi_bitbang_setup_transfer()
168 if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000)) spi_bitbang_setup_transfer()
181 struct spi_bitbang_cs *cs = spi->controller_state; spi_bitbang_setup() local
187 if (!cs) { spi_bitbang_setup()
188 cs = kzalloc(sizeof(*cs), GFP_KERNEL); spi_bitbang_setup()
189 if (!cs) spi_bitbang_setup()
191 spi->controller_state = cs; spi_bitbang_setup()
195 cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; spi_bitbang_setup()
196 if (!cs->txrx_word) spi_bitbang_setup()
205 dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs); spi_bitbang_setup()
216 ndelay(cs->nsecs); spi_bitbang_setup()
235 struct spi_bitbang_cs *cs = spi->controller_state; spi_bitbang_bufs() local
236 unsigned nsecs = cs->nsecs; spi_bitbang_bufs()
238 return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); spi_bitbang_bufs()
|
| H A D | spi-gpio.c | 219 unsigned long cs = spi_gpio->cs_gpios[spi->chip_select]; spi_gpio_chipselect() local
225 if (cs != SPI_GPIO_NO_CHIPSELECT) { spi_gpio_chipselect()
227 gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); spi_gpio_chipselect()
233 unsigned long cs; spi_gpio_setup() local
241 * initialized from the "cs-gpios" property of the node. spi_gpio_setup()
243 cs = spi_gpio->cs_gpios[spi->chip_select]; spi_gpio_setup()
248 cs = (uintptr_t) spi->controller_data; spi_gpio_setup()
252 if (cs != SPI_GPIO_NO_CHIPSELECT) { spi_gpio_setup()
253 status = gpio_request(cs, dev_name(&spi->dev)); spi_gpio_setup()
256 status = gpio_direction_output(cs, spi_gpio_setup()
262 spi_gpio->cs_gpios[spi->chip_select] = cs; spi_gpio_setup()
267 if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT) spi_gpio_setup()
268 gpio_free(cs); spi_gpio_setup()
276 unsigned long cs = spi_gpio->cs_gpios[spi->chip_select]; spi_gpio_cleanup() local
278 if (cs != SPI_GPIO_NO_CHIPSELECT) spi_gpio_cleanup()
279 gpio_free(cs); spi_gpio_cleanup()
462 * In DT environments, take the CS GPIO from the "cs-gpios" spi_gpio_probe()
470 status = of_get_named_gpio(np, "cs-gpios", i); spi_gpio_probe()
473 "invalid cs-gpios property\n"); spi_gpio_probe()
|
| H A D | spi-mpc512x-psc.c | 60 struct mpc512x_psc_spi_cs *cs = spi->controller_state; mpc512x_psc_spi_transfer_setup() local
62 cs->speed_hz = (t && t->speed_hz) mpc512x_psc_spi_transfer_setup()
64 cs->bits_per_word = (t && t->bits_per_word) mpc512x_psc_spi_transfer_setup()
66 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; mpc512x_psc_spi_transfer_setup()
72 struct mpc512x_psc_spi_cs *cs = spi->controller_state; mpc512x_psc_spi_activate_cs() local
101 speed = cs->speed_hz; mpc512x_psc_spi_activate_cs()
108 mps->bits_per_word = cs->bits_per_word; mpc512x_psc_spi_activate_cs()
349 struct mpc512x_psc_spi_cs *cs = spi->controller_state; mpc512x_psc_spi_setup() local
355 if (!cs) { mpc512x_psc_spi_setup()
356 cs = kzalloc(sizeof *cs, GFP_KERNEL); mpc512x_psc_spi_setup()
357 if (!cs) mpc512x_psc_spi_setup()
365 kfree(cs); mpc512x_psc_spi_setup()
372 spi->controller_state = cs; mpc512x_psc_spi_setup()
375 cs->bits_per_word = spi->bits_per_word; mpc512x_psc_spi_setup()
376 cs->speed_hz = spi->max_speed_hz; mpc512x_psc_spi_setup()
|
| H A D | spi-mpc52xx-psc.c | 66 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; mpc52xx_psc_spi_transfer_setup() local
68 cs->speed_hz = (t && t->speed_hz) mpc52xx_psc_spi_transfer_setup()
70 cs->bits_per_word = (t && t->bits_per_word) mpc52xx_psc_spi_transfer_setup()
72 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; mpc52xx_psc_spi_transfer_setup()
78 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; mpc52xx_psc_spi_activate_cs() local
108 if (cs->speed_hz) mpc52xx_psc_spi_activate_cs()
109 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; mpc52xx_psc_spi_activate_cs()
113 mps->bits_per_word = cs->bits_per_word; mpc52xx_psc_spi_activate_cs()
267 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; mpc52xx_psc_spi_setup() local
273 if (!cs) { mpc52xx_psc_spi_setup()
274 cs = kzalloc(sizeof *cs, GFP_KERNEL); mpc52xx_psc_spi_setup()
275 if (!cs) mpc52xx_psc_spi_setup()
277 spi->controller_state = cs; mpc52xx_psc_spi_setup()
280 cs->bits_per_word = spi->bits_per_word; mpc52xx_psc_spi_setup()
281 cs->speed_hz = spi->max_speed_hz; mpc52xx_psc_spi_setup()
|
| H A D | spi-ppc4xx.c | 172 struct spi_ppc4xx_cs *cs = spi->controller_state; spi_ppc4xx_setupxfer() local
200 out_8(&hw->regs->mode, cs->mode); spi_ppc4xx_setupxfer()
225 struct spi_ppc4xx_cs *cs = spi->controller_state; spi_ppc4xx_setup() local
232 if (cs == NULL) { spi_ppc4xx_setup()
233 cs = kzalloc(sizeof *cs, GFP_KERNEL); spi_ppc4xx_setup()
234 if (!cs) spi_ppc4xx_setup()
236 spi->controller_state = cs; spi_ppc4xx_setup()
243 cs->mode = SPI_PPC4XX_MODE_SPE; spi_ppc4xx_setup()
247 cs->mode |= SPI_CLK_MODE0; spi_ppc4xx_setup()
250 cs->mode |= SPI_CLK_MODE1; spi_ppc4xx_setup()
253 cs->mode |= SPI_CLK_MODE2; spi_ppc4xx_setup()
256 cs->mode |= SPI_CLK_MODE3; spi_ppc4xx_setup()
261 cs->mode |= SPI_PPC4XX_MODE_RD; spi_ppc4xx_setup()
269 unsigned int cs = spi->chip_select; spi_ppc4xx_chipsel() local
277 if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST) spi_ppc4xx_chipsel()
284 gpio_set_value(hw->gpios[cs], cspol); spi_ppc4xx_chipsel()
|
| H A D | spi-s3c24xx.c | 71 int cs, int pol);
92 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) s3c24xx_spi_gpiocs() argument
99 struct s3c24xx_spi_devstate *cs = spi->controller_state; s3c24xx_spi_chipsel() local
108 writeb(cs->spcon, hw->regs + S3C2410_SPCON); s3c24xx_spi_chipsel()
112 writeb(cs->spcon | S3C2410_SPCON_ENSCK, s3c24xx_spi_chipsel()
123 struct s3c24xx_spi_devstate *cs = spi->controller_state; s3c24xx_spi_update_state() local
133 if (spi->mode != cs->mode) { s3c24xx_spi_update_state()
142 cs->mode = spi->mode; s3c24xx_spi_update_state()
143 cs->spcon = spcon; s3c24xx_spi_update_state()
146 if (cs->hz != hz) { s3c24xx_spi_update_state()
156 cs->hz = hz; s3c24xx_spi_update_state()
157 cs->sppre = div; s3c24xx_spi_update_state()
166 struct s3c24xx_spi_devstate *cs = spi->controller_state; s3c24xx_spi_setupxfer() local
172 writeb(cs->sppre, hw->regs + S3C2410_SPPRE); s3c24xx_spi_setupxfer()
179 struct s3c24xx_spi_devstate *cs = spi->controller_state; s3c24xx_spi_setup() local
184 if (!cs) { s3c24xx_spi_setup()
185 cs = devm_kzalloc(&spi->dev, s3c24xx_spi_setup()
188 if (!cs) s3c24xx_spi_setup()
191 cs->spcon = SPCON_DEFAULT; s3c24xx_spi_setup()
192 cs->hz = -1; s3c24xx_spi_setup()
193 spi->controller_state = cs; s3c24xx_spi_setup()
584 dev_err(&pdev->dev, "Failed to get gpio for cs\n"); s3c24xx_spi_probe()
|
| H A D | spi-omap-100k.c | 190 struct omap1_spi100k_cs *cs = spi->controller_state; omap1_spi100k_txrx_pio() local
196 word_len = cs->word_len; omap1_spi100k_txrx_pio()
246 struct omap1_spi100k_cs *cs = spi->controller_state; omap1_spi100k_setup_transfer() local
256 cs->word_len = word_len; omap1_spi100k_setup_transfer()
273 struct omap1_spi100k_cs *cs = spi->controller_state; omap1_spi100k_setup() local
277 if (!cs) { omap1_spi100k_setup()
278 cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); omap1_spi100k_setup()
279 if (!cs) omap1_spi100k_setup()
281 cs->base = spi100k->base + spi->chip_select * 0x14; omap1_spi100k_setup()
282 spi->controller_state = cs; omap1_spi100k_setup()
|
| H A D | spi-imx.c | 64 u8 cs; member in struct:spi_imx_config
218 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
222 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
223 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
224 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
225 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
226 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
331 ctrl |= MX51_ECSPI_CTRL_CS(config->cs); mx51_ecspi_config()
335 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); mx51_ecspi_config()
338 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); mx51_ecspi_config()
341 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); mx51_ecspi_config()
342 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); mx51_ecspi_config()
345 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); mx51_ecspi_config()
452 int cs = spi_imx->chipselect[config->cs]; mx31_config() local
470 if (cs < 0) mx31_config()
471 reg |= (cs + 32) << mx31_config()
530 int cs = spi_imx->chipselect[config->cs]; mx21_config() local
543 if (cs < 0) mx21_config()
544 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; mx21_config()
776 config.cs = spi->chip_select; spi_imx_setupxfer()
1114 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); spi_imx_probe()
1125 dev_err(&pdev->dev, "can't get cs gpios\n"); spi_imx_probe()
|
| H A D | spi-fsl-dspi.c | 128 u8 cs; member in struct:fsl_dspi
140 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val); is_double_byte_mode()
233 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), dspi_transfer_write()
251 SPI_PUSHR_PCS(dspi->cs) | dspi_transfer_write()
252 SPI_PUSHR_CTAS(dspi->cs) | dspi_transfer_write()
266 SPI_PUSHR_PCS(dspi->cs) | dspi_transfer_write()
267 SPI_PUSHR_CTAS(dspi->cs) | dspi_transfer_write()
343 dspi->cs = spi->chip_select; dspi_transfer_one_message()
367 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi_transfer_one_message()
370 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi_transfer_one_message()
414 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", dspi_setup()
417 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", dspi_setup()
471 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs), dspi_interrupt()
|
| H A D | spi-st-ssc4.c | 204 int cs = spi->cs_gpio; spi_st_cleanup() local
206 if (gpio_is_valid(cs)) spi_st_cleanup()
207 devm_gpio_free(&spi->dev, cs); spi_st_cleanup()
217 int cs = spi->cs_gpio; spi_st_setup() local
225 if (!gpio_is_valid(cs)) { spi_st_setup()
226 dev_err(&spi->dev, "%d is not a valid gpio\n", cs); spi_st_setup()
230 if (devm_gpio_request(&spi->dev, cs, dev_name(&spi->dev))) { spi_st_setup()
231 dev_err(&spi->dev, "could not request gpio:%d\n", cs); spi_st_setup()
235 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH); spi_st_setup()
|
| /linux-4.1.27/drivers/usb/host/ |
| H A D | xhci-mvebu.c | 34 const struct mbus_dram_window *cs = dram->cs + win; xhci_mvebu_mbus_config() local
36 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | xhci_mvebu_mbus_config()
40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); xhci_mvebu_mbus_config()
|
| /linux-4.1.27/arch/arm/mach-footbridge/ |
| H A D | dc21285-timer.c | 22 static cycle_t cksrc_dc21285_read(struct clocksource *cs) cksrc_dc21285_read() argument
24 return cs->mask - *CSR_TIMER2_VALUE; cksrc_dc21285_read()
27 static int cksrc_dc21285_enable(struct clocksource *cs) cksrc_dc21285_enable() argument
29 *CSR_TIMER2_LOAD = cs->mask; cksrc_dc21285_enable()
35 static void cksrc_dc21285_disable(struct clocksource *cs) cksrc_dc21285_disable() argument
|
| /linux-4.1.27/include/linux/ |
| H A D | clocksource.h | 71 cycle_t (*read)(struct clocksource *cs);
84 int (*enable)(struct clocksource *cs);
85 void (*disable)(struct clocksource *cs);
87 void (*suspend)(struct clocksource *cs);
88 void (*resume)(struct clocksource *cs);
185 extern void clocksource_change_rating(struct clocksource *cs, int rating);
189 extern void clocksource_mark_unstable(struct clocksource *cs);
201 __clocksource_register_scale(struct clocksource *cs, u32 scale, u32 freq);
203 __clocksource_update_freq_scale(struct clocksource *cs, u32 scale, u32 freq);
209 static inline int __clocksource_register(struct clocksource *cs) __clocksource_register() argument
211 return __clocksource_register_scale(cs, 1, 0); __clocksource_register()
214 static inline int clocksource_register_hz(struct clocksource *cs, u32 hz) clocksource_register_hz() argument
216 return __clocksource_register_scale(cs, 1, hz); clocksource_register_hz()
219 static inline int clocksource_register_khz(struct clocksource *cs, u32 khz) clocksource_register_khz() argument
221 return __clocksource_register_scale(cs, 1000, khz); clocksource_register_khz()
224 static inline void __clocksource_update_freq_hz(struct clocksource *cs, u32 hz) __clocksource_update_freq_hz() argument
226 __clocksource_update_freq_scale(cs, 1, hz); __clocksource_update_freq_hz()
229 static inline void __clocksource_update_freq_khz(struct clocksource *cs, u32 khz) __clocksource_update_freq_khz() argument
231 __clocksource_update_freq_scale(cs, 1000, khz); __clocksource_update_freq_khz()
|
| /linux-4.1.27/arch/x86/kvm/ |
| H A D | tss.h | 24 u32 cs; member in struct:tss_segment_32
53 u16 cs; member in struct:tss_segment_16
|
| /linux-4.1.27/include/net/irda/ |
| H A D | crc.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | ircomm_lmp.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | ircomm_ttp.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | irlan_eth.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | irlan_filter.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | iriap_event.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>, All Rights Reserved.
|
| H A D | irlan_client.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998 Dag Brattli <dagb@cs.uit.no>, All Rights Reserved.
|
| H A D | irlan_event.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1997 Dag Brattli <dagb@cs.uit.no>, All Rights Reserved.
|
| H A D | irlan_provider.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>, All Rights Reserved.
|
| H A D | irlmp_frame.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1997, 1999 Dag Brattli <dagb@cs.uit.no>,
|
| H A D | wrapper.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>,
|
| H A D | iriap.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1997-1999 Dag Brattli <dagb@cs.uit.no>,
|
| H A D | irlap_event.h | 8 * Author: Dag Brattli <dagb@cs.uit.no>
11 * Modified by: Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998-1999 Dag Brattli <dagb@cs.uit.no>,
|
| H A D | irlmp_event.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1997, 1999 Dag Brattli <dagb@cs.uit.no>,
|
| H A D | ircomm_event.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| H A D | irqueue.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (C) 1998-1999, Aage Kvalnes <aage@cs.uit.no>
|
| H A D | timer.h | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1997, 1998-1999 Dag Brattli <dagb@cs.uit.no>,
|
| /linux-4.1.27/include/linux/spi/ |
| H A D | s3c24xx.h | 16 int pin_cs; /* simple gpio cs */
23 void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
|
| /linux-4.1.27/arch/arm/mach-at91/ |
| H A D | sam9_smc.c | 34 void sam9_smc_write_mode(int id, int cs, sam9_smc_write_mode() argument
37 sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); sam9_smc_write_mode()
68 void sam9_smc_configure(int id, int cs, sam9_smc_configure() argument
71 sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); sam9_smc_configure()
84 void sam9_smc_read_mode(int id, int cs, sam9_smc_read_mode() argument
87 sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); sam9_smc_read_mode()
122 void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) sam9_smc_read() argument
124 sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); sam9_smc_read()
|
| /linux-4.1.27/include/trace/events/ |
| H A D | mce.h | 30 __field( u8, cs )
48 __entry->cs = m->cs;
58 __entry->cs, __entry->ip,
|
| /linux-4.1.27/arch/arm/boot/compressed/ |
| H A D | string.c | 68 int memcmp(const void *cs, const void *ct, size_t count) memcmp() argument
70 const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count; memcmp()
81 int strcmp(const char *cs, const char *ct) strcmp() argument
87 c1 = *cs++; strcmp()
|
| /linux-4.1.27/drivers/mtd/maps/ |
| H A D | pismo.c | 33 struct pismo_cs_block cs[PISMO_NUM_CS]; member in struct:pismo_eeprom
159 const struct pismo_cs_block *cs, phys_addr_t base) pismo_add_one()
165 region.type = cs->type; pismo_add_one()
166 region.width = pismo_width_to_bytes(cs->width); pismo_add_one()
167 region.access = le16_to_cpu(cs->access); pismo_add_one()
168 region.size = le32_to_cpu(cs->size); pismo_add_one()
171 dev_err(dev, "cs%u: bad width: %02x, ignoring\n", i, cs->width); pismo_add_one()
181 dev_info(dev, "cs%u: %.32s: type %02x access %u00ps size %uK\n", pismo_add_one()
182 i, cs->device, region.type, region.access, region.size / 1024); pismo_add_one()
247 for (i = 0; i < ARRAY_SIZE(eeprom.cs); i++) pismo_probe()
248 if (eeprom.cs[i].type != 0xff) pismo_probe()
249 pismo_add_one(pismo, i, &eeprom.cs[i], pismo_probe()
158 pismo_add_one(struct pismo_data *pismo, int i, const struct pismo_cs_block *cs, phys_addr_t base) pismo_add_one() argument
|
| /linux-4.1.27/arch/powerpc/platforms/chrp/ |
| H A D | smp.c | 4 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
7 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
|
| /linux-4.1.27/arch/blackfin/include/asm/ |
| H A D | string.h | 21 extern int strcmp(const char *cs, const char *ct);
24 extern int strncmp(const char *cs, const char *ct, size_t count);
|
| /linux-4.1.27/arch/arm/mach-imx/ |
| H A D | mx31.h | 111 #define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
112 #define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
113 #define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
114 #define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
|
| H A D | mx27.h | 117 #define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
118 #define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
119 #define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
120 #define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
|
| /linux-4.1.27/arch/x86/kernel/kprobes/ |
| H A D | common.h | 8 /* Skip cs, ip, orig_ax. */ \
41 /* Skip orig_ax, ip, cs */ \
45 /* Skip cs, ip, orig_ax and gs. */ \
65 /* Skip ds, es, fs, gs, orig_ax, and ip. Note: don't pop cs here*/\
|
| /linux-4.1.27/arch/arm/mach-sa1100/include/mach/ |
| H A D | neponset.h | 9 * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
|
| /linux-4.1.27/fs/coda/ |
| H A D | coda_cache.h | 7 * <coda@cs.cmu.edu>
|
| H A D | sysctl.c | 7 * the Coda project. Contact Peter Braam (coda@cs.cmu.edu).
|
| /linux-4.1.27/block/partitions/ |
| H A D | sgi.c | 36 __be32 *ui, cs; sgi_partition() local
55 cs = *ui--; sgi_partition()
56 csum += be32_to_cpu(cs); sgi_partition()
|
| /linux-4.1.27/arch/mips/kernel/ |
| H A D | csrc-bcm1480.c | 28 static cycle_t bcm1480_hpt_read(struct clocksource *cs) bcm1480_hpt_read() argument
48 struct clocksource *cs = &bcm1480_clocksource; sb1480_clocksource_init() local
54 clocksource_register_hz(cs, zbbus); sb1480_clocksource_init()
|
| H A D | csrc-sb1250.c | 44 static cycle_t sb1250_hpt_read(struct clocksource *cs) sb1250_hpt_read() argument
64 struct clocksource *cs = &bcm1250_clocksource; sb1250_clocksource_init() local
77 clocksource_register_hz(cs, V_SCD_TIMER_FREQ); sb1250_clocksource_init()
|
| H A D | cevt-txx9.c | 26 struct clocksource cs; member in struct:txx9_clocksource
30 static cycle_t txx9_cs_read(struct clocksource *cs) txx9_cs_read() argument
33 container_of(cs, struct txx9_clocksource, cs); txx9_cs_read()
41 .cs = {
60 clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); txx9_clocksource_init()
|
| H A D | csrc-r4k.c | 14 static cycle_t c0_hpt_read(struct clocksource *cs) c0_hpt_read() argument
|
| /linux-4.1.27/arch/arm/mach-orion5x/ |
| H A D | common.h | 22 #define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
23 #define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
|
| /linux-4.1.27/sound/usb/ |
| H A D | clock.c | 41 struct uac_clock_source_descriptor *cs = NULL; snd_usb_find_clock_source() local
43 while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, snd_usb_find_clock_source()
45 cs, UAC2_CLOCK_SOURCE))) { snd_usb_find_clock_source()
46 if (cs->bClockID == clock_id) snd_usb_find_clock_source()
47 return cs; snd_usb_find_clock_source()
57 struct uac_clock_selector_descriptor *cs = NULL; snd_usb_find_clock_selector() local
59 while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, snd_usb_find_clock_selector()
61 cs, UAC2_CLOCK_SELECTOR))) { snd_usb_find_clock_selector()
62 if (cs->bClockID == clock_id) snd_usb_find_clock_selector()
63 return cs; snd_usb_find_clock_selector()
73 struct uac_clock_multiplier_descriptor *cs = NULL; snd_usb_find_clock_multiplier() local
75 while ((cs = snd_usb_find_csint_desc(ctrl_iface->extra, snd_usb_find_clock_multiplier()
77 cs, UAC2_CLOCK_MULTIPLIER))) { snd_usb_find_clock_multiplier()
78 if (cs->bClockID == clock_id) snd_usb_find_clock_multiplier()
79 return cs; snd_usb_find_clock_multiplier()
|
| /linux-4.1.27/arch/mips/cavium-octeon/ |
| H A D | octeon-platform.c | 775 int cs, bootbus; octeon_prune_device_tree() local
796 for (cs = 0; cs < 8; cs++) { octeon_prune_device_tree()
797 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); octeon_prune_device_tree()
806 if (cs >= 7) { octeon_prune_device_tree()
807 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ octeon_prune_device_tree()
820 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); octeon_prune_device_tree()
836 new_reg[0] = cpu_to_be32(cs); octeon_prune_device_tree()
839 new_reg[3] = cpu_to_be32(cs + 1); octeon_prune_device_tree()
852 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); octeon_prune_device_tree()
853 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); octeon_prune_device_tree()
854 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); octeon_prune_device_tree()
856 cs++; octeon_prune_device_tree()
857 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); octeon_prune_device_tree()
858 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); octeon_prune_device_tree()
859 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); octeon_prune_device_tree()
875 int cs, bootbus; octeon_prune_device_tree() local
885 for (cs = 0; cs < 8; cs++) { octeon_prune_device_tree()
886 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); octeon_prune_device_tree()
894 if (cs > 7) octeon_prune_device_tree()
897 new_reg[0] = cpu_to_be32(cs); octeon_prune_device_tree()
900 new_reg[3] = cpu_to_be32(cs); octeon_prune_device_tree()
913 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); octeon_prune_device_tree()
914 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); octeon_prune_device_tree()
915 ranges[(cs * 5) + 4] = cpu_to_be32(region_size); octeon_prune_device_tree()
|
| H A D | flash_setup.c | 73 u32 cs; octeon_flash_probe() local
77 r = of_property_read_u32(np, "reg", &cs); octeon_flash_probe()
85 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); octeon_flash_probe()
|
| /linux-4.1.27/drivers/ata/ |
| H A D | ahci_mvebu.c | 43 const struct mbus_dram_window *cs = dram->cs + i; ahci_mvebu_mbus_config() local
45 writel((cs->mbus_attr << 8) | ahci_mvebu_mbus_config()
48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); ahci_mvebu_mbus_config()
49 writel(((cs->size - 1) & 0xffff0000), ahci_mvebu_mbus_config()
|
| /linux-4.1.27/drivers/mtd/nand/ |
| H A D | pxa3xx_nand.c | 170 int cs; member in struct:pxa3xx_nand_host
214 int cs; member in struct:pxa3xx_nand_info
627 if (info->cs == 0) { pxa3xx_nand_irq()
742 struct pxa3xx_nand_host *host = info->host[info->cs]; prepare_start_command()
795 host = info->host[info->cs]; prepare_set_command()
800 if (info->cs != 0) prepare_set_command()
983 if (info->cs != host->cs) { nand_cmdfunc()
984 info->cs = host->cs; nand_cmdfunc()
1031 if (info->cs != host->cs) { nand_cmdfunc_extended()
1032 info->cs = host->cs; nand_cmdfunc_extended()
1239 struct pxa3xx_nand_host *host = info->host[info->cs]; pxa3xx_nand_config_flash()
1376 mtd = info->host[info->cs]->mtd; pxa3xx_nand_sensing()
1483 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", pxa3xx_nand_scan()
1484 info->cs); pxa3xx_nand_scan()
1623 int ret, irq, cs; alloc_nand_resource() local
1635 for (cs = 0; cs < pdata->num_cs; cs++) { alloc_nand_resource()
1637 (sizeof(*mtd) + sizeof(*host)) * cs); alloc_nand_resource()
1640 info->host[cs] = host; alloc_nand_resource()
1642 host->cs = cs; alloc_nand_resource()
1752 int irq, cs; pxa3xx_nand_remove() local
1766 for (cs = 0; cs < pdata->num_cs; cs++) pxa3xx_nand_remove()
1767 nand_release(info->host[cs]->mtd); pxa3xx_nand_remove()
1789 of_property_read_u32(np, "num-cs", &pdata->num_cs); pxa3xx_nand_probe_dt()
1810 int ret, cs, probe_success; pxa3xx_nand_probe() local
1837 for (cs = 0; cs < pdata->num_cs; cs++) { pxa3xx_nand_probe()
1838 struct mtd_info *mtd = info->host[cs]->mtd; pxa3xx_nand_probe()
1846 info->cs = cs; pxa3xx_nand_probe()
1849 dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", pxa3xx_nand_probe()
1850 cs); pxa3xx_nand_probe()
1856 &ppdata, pdata->parts[cs], pxa3xx_nand_probe()
1857 pdata->nr_parts[cs]); pxa3xx_nand_probe()
1876 int cs; pxa3xx_nand_suspend() local
1884 for (cs = 0; cs < pdata->num_cs; cs++) { pxa3xx_nand_suspend()
1885 mtd = info->host[cs]->mtd; pxa3xx_nand_suspend()
1897 int cs; pxa3xx_nand_resume() local
1908 info->cs = 0xff; pxa3xx_nand_resume()
1917 for (cs = 0; cs < pdata->num_cs; cs++) { pxa3xx_nand_resume()
1918 mtd = info->host[cs]->mtd; pxa3xx_nand_resume()
|
| H A D | xway_nand.c | 137 const __be32 *cs = of_get_property(pdev->dev.of_node, xway_nand_probe() local
138 "lantiq,cs", NULL); xway_nand_probe()
142 if (cs && (*cs == 1)) xway_nand_probe()
|
| /linux-4.1.27/drivers/bus/ |
| H A D | imx-weim.c | 76 int cs = 0; imx_weim_gpr_setup() local
79 gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr"); imx_weim_gpr_setup()
81 dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n"); imx_weim_gpr_setup()
87 cs = val; imx_weim_gpr_setup()
90 gprval |= val << cs * 3; imx_weim_gpr_setup()
126 ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", weim_timing_setup()
|
| /linux-4.1.27/arch/mips/include/asm/ |
| H A D | msa.h | 85 #define __BUILD_MSA_CTL_REG(name, cs) \
92 " cfcmsa %0, $" #cs "\n" \
103 " ctcmsa $" #cs ", %0\n" \
123 #define __BUILD_MSA_CTL_REG(name, cs) \
131 " .word %1 | (" #cs " << 11)\n" \
145 " .word %1 | (" #cs " << 6)\n" \
|
| /linux-4.1.27/arch/x86/include/asm/xen/ |
| H A D | interface_32.h | 59 uint16_t cs; member in struct:cpu_user_regs
80 unsigned long cs; member in struct:xen_callback
86 ((struct xen_callback){ .cs = (__cs), .eip = (unsigned long)(__eip) })
|
| /linux-4.1.27/arch/mips/txx9/generic/ |
| H A D | mem_tx4927.c | 45 unsigned int cs = 0; tx4927_process_sdccr() local
60 cs = 256 << sdccr_cs; tx4927_process_sdccr()
64 return rs * cs * mw * bs; tx4927_process_sdccr()
|
| /linux-4.1.27/include/linux/platform_data/ |
| H A D | mtd-onenand-omap2.h | 21 int cs; member in struct:omap_onenand_platform_data
|
| /linux-4.1.27/arch/s390/lib/ |
| H A D | string.c | 196 * @cs: One string
199 * returns 0 if @cs and @ct are equal,
200 * < 0 if @cs is less than @ct
201 * > 0 if @cs is greater than @ct
203 int strcmp(const char *cs, const char *ct) strcmp() argument
215 : "+d" (ret), "+d" (r0), "+a" (cs), "+a" (ct) strcmp()
299 * @cs: One area of memory
303 int memcmp(const void *cs, const void *ct, size_t n) memcmp() argument
305 register unsigned long r2 asm("2") = (unsigned long) cs; memcmp()
|
| /linux-4.1.27/arch/mn10300/kernel/ |
| H A D | csrc-mn10300.c | 16 static cycle_t mn10300_read(struct clocksource *cs) mn10300_read() argument
|
| /linux-4.1.27/arch/nios2/kernel/ |
| H A D | time.c | 45 struct clocksource cs; member in struct:nios2_clocksource
55 to_nios2_clksource(struct clocksource *cs) to_nios2_clksource() argument
57 return container_of(cs, struct nios2_clocksource, cs); to_nios2_clksource()
81 static cycle_t nios2_timer_read(struct clocksource *cs) nios2_timer_read() argument
83 struct nios2_clocksource *nios2_cs = to_nios2_clksource(cs); nios2_timer_read()
96 .cs = {
107 return nios2_timer_read(&nios2_cs.cs); get_cycles()
261 clocksource_register_hz(&nios2_cs.cs, freq); nios2_clocksource_init()
|
| /linux-4.1.27/arch/arm/mach-at91/include/mach/ |
| H A D | at91sam9_smc.h | 42 extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config);
43 extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
44 extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config);
45 extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config);
|
| /linux-4.1.27/include/linux/mtd/ |
| H A D | latch-addr-flash.h | 20 int (*init)(void *data, int cs);
|
| /linux-4.1.27/drivers/leds/ |
| H A D | leds-locomo.c | 4 * Copyright (C) 2005 John Lenz <lenz@cs.wisc.edu>
95 MODULE_AUTHOR("John Lenz <lenz@cs.wisc.edu>");
|
| /linux-4.1.27/arch/x86/include/asm/ |
| H A D | ptrace.h | 25 unsigned long cs; member in struct:pt_regs
61 unsigned long cs; member in struct:pt_regs
110 return ((regs->cs & SEGMENT_RPL_MASK) | (regs->flags & X86_VM_MASK)) >= USER_RPL; user_mode()
112 return !!(regs->cs & 3); user_mode()
133 return regs->cs == __USER_CS; user_64bit_mode()
136 return regs->cs == __USER_CS || regs->cs == pv_info.extra_user_64bit_cs; user_64bit_mode()
184 regs->cs == __KERNEL_CS) regs_get_register()
|
| H A D | a.out-core.h | 55 dump->regs.cs = (u16)regs->cs; aout_dump_thread()
|
| H A D | apm.h | 37 "lcall *%%cs:apm_bios_entry\n\t" apm_bios_call_asm()
61 "lcall *%%cs:apm_bios_entry\n\t" apm_bios_call_simple_asm()
|
| /linux-4.1.27/arch/microblaze/mm/ |
| H A D | mmu_context.c | 12 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
13 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
|
| /linux-4.1.27/arch/s390/include/asm/ |
| H A D | futex.h | 14 "2: cs %1,%2,0(%6)\n" \
85 "0: cs %1,%4,0(%5)\n" futex_atomic_cmpxchg_inatomic()
|
| /linux-4.1.27/net/irda/irlan/ |
| H A D | irlan_event.c | 7 * Author: Dag Brattli <dagb@cs.uit.no>
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
|
| /linux-4.1.27/drivers/ps3/ |
| H A D | ps3av_cmd.c | 40 int cs; member in struct:__anon8358
45 .cs = PS3AV_CMD_VIDEO_CS_RGB_8,
49 .cs = PS3AV_CMD_VIDEO_CS_RGB_10,
53 .cs = PS3AV_CMD_VIDEO_CS_RGB_12,
57 .cs = PS3AV_CMD_VIDEO_CS_YUV444_8,
61 .cs = PS3AV_CMD_VIDEO_CS_YUV444_10,
65 .cs = PS3AV_CMD_VIDEO_CS_YUV444_12,
69 .cs = PS3AV_CMD_VIDEO_CS_YUV422_8,
73 .cs = PS3AV_CMD_VIDEO_CS_YUV422_10,
77 .cs = PS3AV_CMD_VIDEO_CS_YUV422_12,
81 .cs = PS3AV_CMD_VIDEO_CS_XVYCC_8,
85 .cs = PS3AV_CMD_VIDEO_CS_XVYCC_10,
89 .cs = PS3AV_CMD_VIDEO_CS_XVYCC_12,
95 static u32 ps3av_cs_video2av(int cs) ps3av_cs_video2av() argument
100 if (ps3av_cs_video2av_table[i].cs == cs) ps3av_cs_video2av()
106 static u32 ps3av_cs_video2av_bitlen(int cs) ps3av_cs_video2av_bitlen() argument
111 if (ps3av_cs_video2av_table[i].cs == cs) ps3av_cs_video2av_bitlen()
663 /* default cs val */
|
| /linux-4.1.27/drivers/gpio/ |
| H A D | gpio-spear-spics.c | 24 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
41 * @use_count: use count of a spi controller cs lines
146 if (of_property_read_u32(np, "st-spics,cs-value-bit", spics_gpio_probe()
149 if (of_property_read_u32(np, "st-spics,cs-enable-mask", spics_gpio_probe()
152 if (of_property_read_u32(np, "st-spics,cs-enable-shift", spics_gpio_probe()
|
| /linux-4.1.27/drivers/input/joystick/iforce/ |
| H A D | iforce-serio.c | 32 unsigned char cs; iforce_serial_xmit() local
50 cs = 0x2b; iforce_serial_xmit()
55 cs ^= iforce->xmit.buf[iforce->xmit.tail]; iforce_serial_xmit()
60 cs ^= iforce->xmit.buf[iforce->xmit.tail]; iforce_serial_xmit()
64 serio_write(iforce->serio, cs); iforce_serial_xmit()
|
| /linux-4.1.27/arch/avr32/mach-at32ap/ |
| H A D | hsmc.c | 138 int smc_set_configuration(int cs, const struct smc_config *config) smc_set_configuration() argument
145 if (cs >= NR_CHIP_SELECTS) smc_set_configuration()
203 pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n", smc_set_configuration()
204 cs, setup, pulse, cycle, mode); smc_set_configuration()
206 offset = cs * 0x10; smc_set_configuration()
|
| /linux-4.1.27/tools/testing/selftests/x86/ |
| H A D | sigreturn.c | 278 unsigned short cs, gs, fs, ss; member in struct:selectors
290 return &sels->cs; csptr()
368 int cs_bitness(unsigned short cs) cs_bitness() argument
371 asm ("lar %[cs], %[ar]\n\t" cs_bitness()
376 : [cs] "r" (cs)); cs_bitness()
402 asm ("mov %%cs,%0" : "=r" (my_cs)); find_cs()
419 int cs = find_cs(cs_bits); test_valid_sigreturn() local
420 if (cs == -1) { test_valid_sigreturn()
441 sig_cs = cs; test_valid_sigreturn()
484 if (req_sels->cs != res_sels->cs) { test_valid_sigreturn()
486 req_sels->cs, res_sels->cs); test_valid_sigreturn()
532 int cs = force_cs == -1 ? find_cs(cs_bits) : force_cs; test_bad_iret() local
533 if (cs == -1) test_bad_iret()
536 sig_cs = cs; test_bad_iret()
589 asm volatile ("mov %%cs,%0" : "=r" (my_cs)); main()
|
| /linux-4.1.27/arch/powerpc/boot/ |
| H A D | cuboot-pq2.c | 84 int cs = cs_ranges_buf[i].csnum; update_cs_ranges() local
85 if (cs >= ctrl_size / 8) update_cs_ranges()
91 base = in_be32(&ctrl_addr[cs * 2]); update_cs_ranges()
98 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; update_cs_ranges()
104 out_be32(&ctrl_addr[cs * 2], 0); update_cs_ranges()
105 out_be32(&ctrl_addr[cs * 2 + 1], update_cs_ranges()
107 out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr); update_cs_ranges()
|
| /linux-4.1.27/arch/arm/plat-orion/ |
| H A D | pcie.c | 155 const struct mbus_dram_window *cs = dram->cs + i; orion_pcie_setup_wins() local
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); orion_pcie_setup_wins()
159 writel(((cs->size - 1) & 0xffff0000) | orion_pcie_setup_wins()
160 (cs->mbus_attr << 8) | orion_pcie_setup_wins()
164 size += cs->size; orion_pcie_setup_wins()
176 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); orion_pcie_setup_wins()
|
| /linux-4.1.27/sound/soc/kirkwood/ |
| H A D | kirkwood-dma.c | 91 /* try to find matching cs for current dma address */ kirkwood_dma_conf_mbus_windows()
93 const struct mbus_dram_window *cs = dram->cs + i; kirkwood_dma_conf_mbus_windows() local
94 if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { kirkwood_dma_conf_mbus_windows()
95 writel(cs->base & 0xffff0000, kirkwood_dma_conf_mbus_windows()
97 writel(((cs->size - 1) & 0xffff0000) | kirkwood_dma_conf_mbus_windows()
98 (cs->mbus_attr << 8) | kirkwood_dma_conf_mbus_windows()
|
| /linux-4.1.27/arch/x86/include/uapi/asm/ |
| H A D | mce.h | 20 __u8 cs; /* code segment */ member in struct:mce
|
| /linux-4.1.27/include/uapi/video/ |
| H A D | uvesafb.h | 17 __u16 cs; member in struct:v86_regs
|