1/*
2 * SuperH Timer Support - TMU
3 *
4 *  Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/delay.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pm_domain.h>
30#include <linux/pm_runtime.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33#include <linux/spinlock.h>
34
35enum sh_tmu_model {
36	SH_TMU,
37	SH_TMU_SH3,
38};
39
40struct sh_tmu_device;
41
42struct sh_tmu_channel {
43	struct sh_tmu_device *tmu;
44	unsigned int index;
45
46	void __iomem *base;
47	int irq;
48
49	unsigned long rate;
50	unsigned long periodic;
51	struct clock_event_device ced;
52	struct clocksource cs;
53	bool cs_enabled;
54	unsigned int enable_count;
55};
56
57struct sh_tmu_device {
58	struct platform_device *pdev;
59
60	void __iomem *mapbase;
61	struct clk *clk;
62
63	enum sh_tmu_model model;
64
65	raw_spinlock_t lock; /* Protect the shared start/stop register */
66
67	struct sh_tmu_channel *channels;
68	unsigned int num_channels;
69
70	bool has_clockevent;
71	bool has_clocksource;
72};
73
74#define TSTR -1 /* shared register */
75#define TCOR  0 /* channel register */
76#define TCNT 1 /* channel register */
77#define TCR 2 /* channel register */
78
79#define TCR_UNF			(1 << 8)
80#define TCR_UNIE		(1 << 5)
81#define TCR_TPSC_CLK4		(0 << 0)
82#define TCR_TPSC_CLK16		(1 << 0)
83#define TCR_TPSC_CLK64		(2 << 0)
84#define TCR_TPSC_CLK256		(3 << 0)
85#define TCR_TPSC_CLK1024	(4 << 0)
86#define TCR_TPSC_MASK		(7 << 0)
87
88static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr)
89{
90	unsigned long offs;
91
92	if (reg_nr == TSTR) {
93		switch (ch->tmu->model) {
94		case SH_TMU_SH3:
95			return ioread8(ch->tmu->mapbase + 2);
96		case SH_TMU:
97			return ioread8(ch->tmu->mapbase + 4);
98		}
99	}
100
101	offs = reg_nr << 2;
102
103	if (reg_nr == TCR)
104		return ioread16(ch->base + offs);
105	else
106		return ioread32(ch->base + offs);
107}
108
109static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr,
110				unsigned long value)
111{
112	unsigned long offs;
113
114	if (reg_nr == TSTR) {
115		switch (ch->tmu->model) {
116		case SH_TMU_SH3:
117			return iowrite8(value, ch->tmu->mapbase + 2);
118		case SH_TMU:
119			return iowrite8(value, ch->tmu->mapbase + 4);
120		}
121	}
122
123	offs = reg_nr << 2;
124
125	if (reg_nr == TCR)
126		iowrite16(value, ch->base + offs);
127	else
128		iowrite32(value, ch->base + offs);
129}
130
131static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start)
132{
133	unsigned long flags, value;
134
135	/* start stop register shared by multiple timer channels */
136	raw_spin_lock_irqsave(&ch->tmu->lock, flags);
137	value = sh_tmu_read(ch, TSTR);
138
139	if (start)
140		value |= 1 << ch->index;
141	else
142		value &= ~(1 << ch->index);
143
144	sh_tmu_write(ch, TSTR, value);
145	raw_spin_unlock_irqrestore(&ch->tmu->lock, flags);
146}
147
148static int __sh_tmu_enable(struct sh_tmu_channel *ch)
149{
150	int ret;
151
152	/* enable clock */
153	ret = clk_enable(ch->tmu->clk);
154	if (ret) {
155		dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock\n",
156			ch->index);
157		return ret;
158	}
159
160	/* make sure channel is disabled */
161	sh_tmu_start_stop_ch(ch, 0);
162
163	/* maximum timeout */
164	sh_tmu_write(ch, TCOR, 0xffffffff);
165	sh_tmu_write(ch, TCNT, 0xffffffff);
166
167	/* configure channel to parent clock / 4, irq off */
168	ch->rate = clk_get_rate(ch->tmu->clk) / 4;
169	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
170
171	/* enable channel */
172	sh_tmu_start_stop_ch(ch, 1);
173
174	return 0;
175}
176
177static int sh_tmu_enable(struct sh_tmu_channel *ch)
178{
179	if (ch->enable_count++ > 0)
180		return 0;
181
182	pm_runtime_get_sync(&ch->tmu->pdev->dev);
183	dev_pm_syscore_device(&ch->tmu->pdev->dev, true);
184
185	return __sh_tmu_enable(ch);
186}
187
188static void __sh_tmu_disable(struct sh_tmu_channel *ch)
189{
190	/* disable channel */
191	sh_tmu_start_stop_ch(ch, 0);
192
193	/* disable interrupts in TMU block */
194	sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
195
196	/* stop clock */
197	clk_disable(ch->tmu->clk);
198}
199
200static void sh_tmu_disable(struct sh_tmu_channel *ch)
201{
202	if (WARN_ON(ch->enable_count == 0))
203		return;
204
205	if (--ch->enable_count > 0)
206		return;
207
208	__sh_tmu_disable(ch);
209
210	dev_pm_syscore_device(&ch->tmu->pdev->dev, false);
211	pm_runtime_put(&ch->tmu->pdev->dev);
212}
213
214static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta,
215			    int periodic)
216{
217	/* stop timer */
218	sh_tmu_start_stop_ch(ch, 0);
219
220	/* acknowledge interrupt */
221	sh_tmu_read(ch, TCR);
222
223	/* enable interrupt */
224	sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
225
226	/* reload delta value in case of periodic timer */
227	if (periodic)
228		sh_tmu_write(ch, TCOR, delta);
229	else
230		sh_tmu_write(ch, TCOR, 0xffffffff);
231
232	sh_tmu_write(ch, TCNT, delta);
233
234	/* start timer */
235	sh_tmu_start_stop_ch(ch, 1);
236}
237
238static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
239{
240	struct sh_tmu_channel *ch = dev_id;
241
242	/* disable or acknowledge interrupt */
243	if (ch->ced.mode == CLOCK_EVT_MODE_ONESHOT)
244		sh_tmu_write(ch, TCR, TCR_TPSC_CLK4);
245	else
246		sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4);
247
248	/* notify clockevent layer */
249	ch->ced.event_handler(&ch->ced);
250	return IRQ_HANDLED;
251}
252
253static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs)
254{
255	return container_of(cs, struct sh_tmu_channel, cs);
256}
257
258static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
259{
260	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
261
262	return sh_tmu_read(ch, TCNT) ^ 0xffffffff;
263}
264
265static int sh_tmu_clocksource_enable(struct clocksource *cs)
266{
267	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
268	int ret;
269
270	if (WARN_ON(ch->cs_enabled))
271		return 0;
272
273	ret = sh_tmu_enable(ch);
274	if (!ret) {
275		__clocksource_update_freq_hz(cs, ch->rate);
276		ch->cs_enabled = true;
277	}
278
279	return ret;
280}
281
282static void sh_tmu_clocksource_disable(struct clocksource *cs)
283{
284	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
285
286	if (WARN_ON(!ch->cs_enabled))
287		return;
288
289	sh_tmu_disable(ch);
290	ch->cs_enabled = false;
291}
292
293static void sh_tmu_clocksource_suspend(struct clocksource *cs)
294{
295	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
296
297	if (!ch->cs_enabled)
298		return;
299
300	if (--ch->enable_count == 0) {
301		__sh_tmu_disable(ch);
302		pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev);
303	}
304}
305
306static void sh_tmu_clocksource_resume(struct clocksource *cs)
307{
308	struct sh_tmu_channel *ch = cs_to_sh_tmu(cs);
309
310	if (!ch->cs_enabled)
311		return;
312
313	if (ch->enable_count++ == 0) {
314		pm_genpd_syscore_poweron(&ch->tmu->pdev->dev);
315		__sh_tmu_enable(ch);
316	}
317}
318
319static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch,
320				       const char *name)
321{
322	struct clocksource *cs = &ch->cs;
323
324	cs->name = name;
325	cs->rating = 200;
326	cs->read = sh_tmu_clocksource_read;
327	cs->enable = sh_tmu_clocksource_enable;
328	cs->disable = sh_tmu_clocksource_disable;
329	cs->suspend = sh_tmu_clocksource_suspend;
330	cs->resume = sh_tmu_clocksource_resume;
331	cs->mask = CLOCKSOURCE_MASK(32);
332	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
333
334	dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n",
335		 ch->index);
336
337	/* Register with dummy 1 Hz value, gets updated in ->enable() */
338	clocksource_register_hz(cs, 1);
339	return 0;
340}
341
342static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced)
343{
344	return container_of(ced, struct sh_tmu_channel, ced);
345}
346
347static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic)
348{
349	struct clock_event_device *ced = &ch->ced;
350
351	sh_tmu_enable(ch);
352
353	clockevents_config(ced, ch->rate);
354
355	if (periodic) {
356		ch->periodic = (ch->rate + HZ/2) / HZ;
357		sh_tmu_set_next(ch, ch->periodic, 1);
358	}
359}
360
361static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
362				    struct clock_event_device *ced)
363{
364	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
365	int disabled = 0;
366
367	/* deal with old setting first */
368	switch (ced->mode) {
369	case CLOCK_EVT_MODE_PERIODIC:
370	case CLOCK_EVT_MODE_ONESHOT:
371		sh_tmu_disable(ch);
372		disabled = 1;
373		break;
374	default:
375		break;
376	}
377
378	switch (mode) {
379	case CLOCK_EVT_MODE_PERIODIC:
380		dev_info(&ch->tmu->pdev->dev,
381			 "ch%u: used for periodic clock events\n", ch->index);
382		sh_tmu_clock_event_start(ch, 1);
383		break;
384	case CLOCK_EVT_MODE_ONESHOT:
385		dev_info(&ch->tmu->pdev->dev,
386			 "ch%u: used for oneshot clock events\n", ch->index);
387		sh_tmu_clock_event_start(ch, 0);
388		break;
389	case CLOCK_EVT_MODE_UNUSED:
390		if (!disabled)
391			sh_tmu_disable(ch);
392		break;
393	case CLOCK_EVT_MODE_SHUTDOWN:
394	default:
395		break;
396	}
397}
398
399static int sh_tmu_clock_event_next(unsigned long delta,
400				   struct clock_event_device *ced)
401{
402	struct sh_tmu_channel *ch = ced_to_sh_tmu(ced);
403
404	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
405
406	/* program new delta value */
407	sh_tmu_set_next(ch, delta, 0);
408	return 0;
409}
410
411static void sh_tmu_clock_event_suspend(struct clock_event_device *ced)
412{
413	pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
414}
415
416static void sh_tmu_clock_event_resume(struct clock_event_device *ced)
417{
418	pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev);
419}
420
421static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch,
422				       const char *name)
423{
424	struct clock_event_device *ced = &ch->ced;
425	int ret;
426
427	ced->name = name;
428	ced->features = CLOCK_EVT_FEAT_PERIODIC;
429	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
430	ced->rating = 200;
431	ced->cpumask = cpu_possible_mask;
432	ced->set_next_event = sh_tmu_clock_event_next;
433	ced->set_mode = sh_tmu_clock_event_mode;
434	ced->suspend = sh_tmu_clock_event_suspend;
435	ced->resume = sh_tmu_clock_event_resume;
436
437	dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n",
438		 ch->index);
439
440	clockevents_config_and_register(ced, 1, 0x300, 0xffffffff);
441
442	ret = request_irq(ch->irq, sh_tmu_interrupt,
443			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
444			  dev_name(&ch->tmu->pdev->dev), ch);
445	if (ret) {
446		dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n",
447			ch->index, ch->irq);
448		return;
449	}
450}
451
452static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name,
453			   bool clockevent, bool clocksource)
454{
455	if (clockevent) {
456		ch->tmu->has_clockevent = true;
457		sh_tmu_register_clockevent(ch, name);
458	} else if (clocksource) {
459		ch->tmu->has_clocksource = true;
460		sh_tmu_register_clocksource(ch, name);
461	}
462
463	return 0;
464}
465
466static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index,
467				bool clockevent, bool clocksource,
468				struct sh_tmu_device *tmu)
469{
470	/* Skip unused channels. */
471	if (!clockevent && !clocksource)
472		return 0;
473
474	ch->tmu = tmu;
475	ch->index = index;
476
477	if (tmu->model == SH_TMU_SH3)
478		ch->base = tmu->mapbase + 4 + ch->index * 12;
479	else
480		ch->base = tmu->mapbase + 8 + ch->index * 12;
481
482	ch->irq = platform_get_irq(tmu->pdev, index);
483	if (ch->irq < 0) {
484		dev_err(&tmu->pdev->dev, "ch%u: failed to get irq\n",
485			ch->index);
486		return ch->irq;
487	}
488
489	ch->cs_enabled = false;
490	ch->enable_count = 0;
491
492	return sh_tmu_register(ch, dev_name(&tmu->pdev->dev),
493			       clockevent, clocksource);
494}
495
496static int sh_tmu_map_memory(struct sh_tmu_device *tmu)
497{
498	struct resource *res;
499
500	res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0);
501	if (!res) {
502		dev_err(&tmu->pdev->dev, "failed to get I/O memory\n");
503		return -ENXIO;
504	}
505
506	tmu->mapbase = ioremap_nocache(res->start, resource_size(res));
507	if (tmu->mapbase == NULL)
508		return -ENXIO;
509
510	return 0;
511}
512
513static int sh_tmu_parse_dt(struct sh_tmu_device *tmu)
514{
515	struct device_node *np = tmu->pdev->dev.of_node;
516
517	tmu->model = SH_TMU;
518	tmu->num_channels = 3;
519
520	of_property_read_u32(np, "#renesas,channels", &tmu->num_channels);
521
522	if (tmu->num_channels != 2 && tmu->num_channels != 3) {
523		dev_err(&tmu->pdev->dev, "invalid number of channels %u\n",
524			tmu->num_channels);
525		return -EINVAL;
526	}
527
528	return 0;
529}
530
531static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev)
532{
533	unsigned int i;
534	int ret;
535
536	tmu->pdev = pdev;
537
538	raw_spin_lock_init(&tmu->lock);
539
540	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
541		ret = sh_tmu_parse_dt(tmu);
542		if (ret < 0)
543			return ret;
544	} else if (pdev->dev.platform_data) {
545		const struct platform_device_id *id = pdev->id_entry;
546		struct sh_timer_config *cfg = pdev->dev.platform_data;
547
548		tmu->model = id->driver_data;
549		tmu->num_channels = hweight8(cfg->channels_mask);
550	} else {
551		dev_err(&tmu->pdev->dev, "missing platform data\n");
552		return -ENXIO;
553	}
554
555	/* Get hold of clock. */
556	tmu->clk = clk_get(&tmu->pdev->dev, "fck");
557	if (IS_ERR(tmu->clk)) {
558		dev_err(&tmu->pdev->dev, "cannot get clock\n");
559		return PTR_ERR(tmu->clk);
560	}
561
562	ret = clk_prepare(tmu->clk);
563	if (ret < 0)
564		goto err_clk_put;
565
566	/* Map the memory resource. */
567	ret = sh_tmu_map_memory(tmu);
568	if (ret < 0) {
569		dev_err(&tmu->pdev->dev, "failed to remap I/O memory\n");
570		goto err_clk_unprepare;
571	}
572
573	/* Allocate and setup the channels. */
574	tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels,
575				GFP_KERNEL);
576	if (tmu->channels == NULL) {
577		ret = -ENOMEM;
578		goto err_unmap;
579	}
580
581	/*
582	 * Use the first channel as a clock event device and the second channel
583	 * as a clock source.
584	 */
585	for (i = 0; i < tmu->num_channels; ++i) {
586		ret = sh_tmu_channel_setup(&tmu->channels[i], i,
587					   i == 0, i == 1, tmu);
588		if (ret < 0)
589			goto err_unmap;
590	}
591
592	platform_set_drvdata(pdev, tmu);
593
594	return 0;
595
596err_unmap:
597	kfree(tmu->channels);
598	iounmap(tmu->mapbase);
599err_clk_unprepare:
600	clk_unprepare(tmu->clk);
601err_clk_put:
602	clk_put(tmu->clk);
603	return ret;
604}
605
606static int sh_tmu_probe(struct platform_device *pdev)
607{
608	struct sh_tmu_device *tmu = platform_get_drvdata(pdev);
609	int ret;
610
611	if (!is_early_platform_device(pdev)) {
612		pm_runtime_set_active(&pdev->dev);
613		pm_runtime_enable(&pdev->dev);
614	}
615
616	if (tmu) {
617		dev_info(&pdev->dev, "kept as earlytimer\n");
618		goto out;
619	}
620
621	tmu = kzalloc(sizeof(*tmu), GFP_KERNEL);
622	if (tmu == NULL)
623		return -ENOMEM;
624
625	ret = sh_tmu_setup(tmu, pdev);
626	if (ret) {
627		kfree(tmu);
628		pm_runtime_idle(&pdev->dev);
629		return ret;
630	}
631	if (is_early_platform_device(pdev))
632		return 0;
633
634 out:
635	if (tmu->has_clockevent || tmu->has_clocksource)
636		pm_runtime_irq_safe(&pdev->dev);
637	else
638		pm_runtime_idle(&pdev->dev);
639
640	return 0;
641}
642
643static int sh_tmu_remove(struct platform_device *pdev)
644{
645	return -EBUSY; /* cannot unregister clockevent and clocksource */
646}
647
648static const struct platform_device_id sh_tmu_id_table[] = {
649	{ "sh-tmu", SH_TMU },
650	{ "sh-tmu-sh3", SH_TMU_SH3 },
651	{ }
652};
653MODULE_DEVICE_TABLE(platform, sh_tmu_id_table);
654
655static const struct of_device_id sh_tmu_of_table[] __maybe_unused = {
656	{ .compatible = "renesas,tmu" },
657	{ }
658};
659MODULE_DEVICE_TABLE(of, sh_tmu_of_table);
660
661static struct platform_driver sh_tmu_device_driver = {
662	.probe		= sh_tmu_probe,
663	.remove		= sh_tmu_remove,
664	.driver		= {
665		.name	= "sh_tmu",
666		.of_match_table = of_match_ptr(sh_tmu_of_table),
667	},
668	.id_table	= sh_tmu_id_table,
669};
670
671static int __init sh_tmu_init(void)
672{
673	return platform_driver_register(&sh_tmu_device_driver);
674}
675
676static void __exit sh_tmu_exit(void)
677{
678	platform_driver_unregister(&sh_tmu_device_driver);
679}
680
681early_platform_init("earlytimer", &sh_tmu_device_driver);
682subsys_initcall(sh_tmu_init);
683module_exit(sh_tmu_exit);
684
685MODULE_AUTHOR("Magnus Damm");
686MODULE_DESCRIPTION("SuperH TMU Timer Driver");
687MODULE_LICENSE("GPL v2");
688